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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
4 *
5 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2014 Collabora Ltd.
8 * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
9 * Anand Moon <linux.amoon@gmail.com>
10 */
11
12#include <dt-bindings/input/input.h>
13#include "exynos5422-odroid-core.dtsi"
14
15/ {
16 gpio-keys {
17 compatible = "gpio-keys";
18 pinctrl-names = "default";
19 pinctrl-0 = <&power_key>;
20
21 power-key {
22 /*
23 * The power button (SW2) is connected to the PWRON
24 * pin (active high) of the S2MPS11 PMIC, which acts
25 * as a 16ms debouce filter and signal inverter with
26 * output on ONOB pin (active low). ONOB PMIC pin is
27 * then connected to XEINT3 SoC pin.
28 */
29 gpios = <&gpx0 3 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_POWER>;
31 label = "power key";
32 debounce-interval = <0>;
33 wakeup-source;
34 };
35 };
36
37 emmc_pwrseq: pwrseq {
38 pinctrl-0 = <&emmc_nrst_pin>;
39 pinctrl-names = "default";
40 compatible = "mmc-pwrseq-emmc";
41 reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
42 };
43
44 fan0: pwm-fan {
45 compatible = "pwm-fan";
46 pwms = <&pwm 0 20972 0>;
47 #cooling-cells = <2>;
48 cooling-levels = <0 130 170 230>;
49 };
50
51 thermal-zones {
52 cpu0_thermal: cpu0-thermal {
53 thermal-sensors = <&tmu_cpu0 0>;
54 polling-delay-passive = <250>;
55 polling-delay = <0>;
56 trips {
57 cpu0_alert0: cpu-alert-0 {
58 temperature = <50000>; /* millicelsius */
59 hysteresis = <5000>; /* millicelsius */
60 type = "active";
61 };
62 cpu0_alert1: cpu-alert-1 {
63 temperature = <60000>; /* millicelsius */
64 hysteresis = <5000>; /* millicelsius */
65 type = "active";
66 };
67 cpu0_alert2: cpu-alert-2 {
68 temperature = <70000>; /* millicelsius */
69 hysteresis = <5000>; /* millicelsius */
70 type = "active";
71 };
72 cpu0_crit0: cpu-crit-0 {
73 temperature = <120000>; /* millicelsius */
74 hysteresis = <0>; /* millicelsius */
75 type = "critical";
76 };
77 /*
78 * Exynos542x supports only 4 trip-points
79 * so for these polling mode is required.
80 * Start polling at temperature level of last
81 * interrupt-driven trip: cpu0_alert2
82 */
83 cpu0_alert3: cpu-alert-3 {
84 temperature = <70000>; /* millicelsius */
85 hysteresis = <10000>; /* millicelsius */
86 type = "passive";
87 };
88 cpu0_alert4: cpu-alert-4 {
89 temperature = <85000>; /* millicelsius */
90 hysteresis = <10000>; /* millicelsius */
91 type = "passive";
92 };
93 };
94 cooling-maps {
95 map0 {
96 trip = <&cpu0_alert0>;
97 cooling-device = <&fan0 0 1>;
98 };
99 map1 {
100 trip = <&cpu0_alert1>;
101 cooling-device = <&fan0 1 2>;
102 };
103 map2 {
104 trip = <&cpu0_alert2>;
105 cooling-device = <&fan0 2 3>;
106 };
107 /*
108 * When reaching cpu0_alert3, reduce CPU
109 * by 2 steps. On Exynos5422/5800 that would
110 * (usually) be: 1800 MHz and 1200 MHz.
111 */
112 map3 {
113 trip = <&cpu0_alert3>;
114 cooling-device = <&cpu0 0 2>,
115 <&cpu1 0 2>,
116 <&cpu2 0 2>,
117 <&cpu3 0 2>,
118 <&cpu4 0 2>,
119 <&cpu5 0 2>,
120 <&cpu6 0 2>,
121 <&cpu7 0 2>;
122 };
123 /*
124 * When reaching cpu0_alert4, reduce CPU
125 * further, down to 600 MHz (14 steps for big,
126 * 8 steps for LITTLE).
127 */
128 cpu0_cooling_map4: map4 {
129 trip = <&cpu0_alert4>;
130 cooling-device = <&cpu0 3 8>,
131 <&cpu1 3 8>,
132 <&cpu2 3 8>,
133 <&cpu3 3 8>,
134 <&cpu4 3 14>,
135 <&cpu5 3 14>,
136 <&cpu6 3 14>,
137 <&cpu7 3 14>;
138 };
139 };
140 };
141 cpu1_thermal: cpu1-thermal {
142 thermal-sensors = <&tmu_cpu1 0>;
143 polling-delay-passive = <250>;
144 polling-delay = <0>;
145 trips {
146 cpu1_alert0: cpu-alert-0 {
147 temperature = <50000>;
148 hysteresis = <5000>;
149 type = "active";
150 };
151 cpu1_alert1: cpu-alert-1 {
152 temperature = <60000>;
153 hysteresis = <5000>;
154 type = "active";
155 };
156 cpu1_alert2: cpu-alert-2 {
157 temperature = <70000>;
158 hysteresis = <5000>;
159 type = "active";
160 };
161 cpu1_crit0: cpu-crit-0 {
162 temperature = <120000>;
163 hysteresis = <0>;
164 type = "critical";
165 };
166 cpu1_alert3: cpu-alert-3 {
167 temperature = <70000>;
168 hysteresis = <10000>;
169 type = "passive";
170 };
171 cpu1_alert4: cpu-alert-4 {
172 temperature = <85000>;
173 hysteresis = <10000>;
174 type = "passive";
175 };
176 };
177 cooling-maps {
178 map0 {
179 trip = <&cpu1_alert0>;
180 cooling-device = <&fan0 0 1>;
181 };
182 map1 {
183 trip = <&cpu1_alert1>;
184 cooling-device = <&fan0 1 2>;
185 };
186 map2 {
187 trip = <&cpu1_alert2>;
188 cooling-device = <&fan0 2 3>;
189 };
190 map3 {
191 trip = <&cpu1_alert3>;
192 cooling-device = <&cpu0 0 2>,
193 <&cpu1 0 2>,
194 <&cpu2 0 2>,
195 <&cpu3 0 2>,
196 <&cpu4 0 2>,
197 <&cpu5 0 2>,
198 <&cpu6 0 2>,
199 <&cpu7 0 2>;
200 };
201 cpu1_cooling_map4: map4 {
202 trip = <&cpu1_alert4>;
203 cooling-device = <&cpu0 3 8>,
204 <&cpu1 3 8>,
205 <&cpu2 3 8>,
206 <&cpu3 3 8>,
207 <&cpu4 3 14>,
208 <&cpu5 3 14>,
209 <&cpu6 3 14>,
210 <&cpu7 3 14>;
211 };
212 };
213 };
214 cpu2_thermal: cpu2-thermal {
215 thermal-sensors = <&tmu_cpu2 0>;
216 polling-delay-passive = <250>;
217 polling-delay = <0>;
218 trips {
219 cpu2_alert0: cpu-alert-0 {
220 temperature = <50000>;
221 hysteresis = <5000>;
222 type = "active";
223 };
224 cpu2_alert1: cpu-alert-1 {
225 temperature = <60000>;
226 hysteresis = <5000>;
227 type = "active";
228 };
229 cpu2_alert2: cpu-alert-2 {
230 temperature = <70000>;
231 hysteresis = <5000>;
232 type = "active";
233 };
234 cpu2_crit0: cpu-crit-0 {
235 temperature = <120000>;
236 hysteresis = <0>;
237 type = "critical";
238 };
239 cpu2_alert3: cpu-alert-3 {
240 temperature = <70000>;
241 hysteresis = <10000>;
242 type = "passive";
243 };
244 cpu2_alert4: cpu-alert-4 {
245 temperature = <85000>;
246 hysteresis = <10000>;
247 type = "passive";
248 };
249 };
250 cooling-maps {
251 map0 {
252 trip = <&cpu2_alert0>;
253 cooling-device = <&fan0 0 1>;
254 };
255 map1 {
256 trip = <&cpu2_alert1>;
257 cooling-device = <&fan0 1 2>;
258 };
259 map2 {
260 trip = <&cpu2_alert2>;
261 cooling-device = <&fan0 2 3>;
262 };
263 map3 {
264 trip = <&cpu2_alert3>;
265 cooling-device = <&cpu0 0 2>,
266 <&cpu1 0 2>,
267 <&cpu2 0 2>,
268 <&cpu3 0 2>,
269 <&cpu4 0 2>,
270 <&cpu5 0 2>,
271 <&cpu6 0 2>,
272 <&cpu7 0 2>;
273 };
274 cpu2_cooling_map4: map4 {
275 trip = <&cpu2_alert4>;
276 cooling-device = <&cpu0 3 8>,
277 <&cpu1 3 8>,
278 <&cpu2 3 8>,
279 <&cpu3 3 8>,
280 <&cpu4 3 14>,
281 <&cpu5 3 14>,
282 <&cpu6 3 14>,
283 <&cpu7 3 14>;
284 };
285 };
286 };
287 cpu3_thermal: cpu3-thermal {
288 thermal-sensors = <&tmu_cpu3 0>;
289 polling-delay-passive = <250>;
290 polling-delay = <0>;
291 trips {
292 cpu3_alert0: cpu-alert-0 {
293 temperature = <50000>;
294 hysteresis = <5000>;
295 type = "active";
296 };
297 cpu3_alert1: cpu-alert-1 {
298 temperature = <60000>;
299 hysteresis = <5000>;
300 type = "active";
301 };
302 cpu3_alert2: cpu-alert-2 {
303 temperature = <70000>;
304 hysteresis = <5000>;
305 type = "active";
306 };
307 cpu3_crit0: cpu-crit-0 {
308 temperature = <120000>;
309 hysteresis = <0>;
310 type = "critical";
311 };
312 cpu3_alert3: cpu-alert-3 {
313 temperature = <70000>;
314 hysteresis = <10000>;
315 type = "passive";
316 };
317 cpu3_alert4: cpu-alert-4 {
318 temperature = <85000>;
319 hysteresis = <10000>;
320 type = "passive";
321 };
322 };
323 cooling-maps {
324 map0 {
325 trip = <&cpu3_alert0>;
326 cooling-device = <&fan0 0 1>;
327 };
328 map1 {
329 trip = <&cpu3_alert1>;
330 cooling-device = <&fan0 1 2>;
331 };
332 map2 {
333 trip = <&cpu3_alert2>;
334 cooling-device = <&fan0 2 3>;
335 };
336 map3 {
337 trip = <&cpu3_alert3>;
338 cooling-device = <&cpu0 0 2>,
339 <&cpu1 0 2>,
340 <&cpu2 0 2>,
341 <&cpu3 0 2>,
342 <&cpu4 0 2>,
343 <&cpu5 0 2>,
344 <&cpu6 0 2>,
345 <&cpu7 0 2>;
346 };
347 cpu3_cooling_map4: map4 {
348 trip = <&cpu3_alert4>;
349 cooling-device = <&cpu0 3 8>,
350 <&cpu1 3 8>,
351 <&cpu2 3 8>,
352 <&cpu3 3 8>,
353 <&cpu4 3 14>,
354 <&cpu5 3 14>,
355 <&cpu6 3 14>,
356 <&cpu7 3 14>;
357 };
358 };
359 };
360 gpu_thermal: gpu-thermal {
361 thermal-sensors = <&tmu_gpu 0>;
362 polling-delay-passive = <250>;
363 polling-delay = <0>;
364 trips {
365 gpu_alert0: gpu-alert-0 {
366 temperature = <50000>;
367 hysteresis = <5000>;
368 type = "active";
369 };
370 gpu_alert1: gpu-alert-1 {
371 temperature = <60000>;
372 hysteresis = <5000>;
373 type = "active";
374 };
375 gpu_alert2: gpu-alert-2 {
376 temperature = <70000>;
377 hysteresis = <5000>;
378 type = "active";
379 };
380 gpu_crit0: gpu-crit-0 {
381 temperature = <120000>;
382 hysteresis = <0>;
383 type = "critical";
384 };
385 gpu_alert3: gpu-alert-3 {
386 temperature = <70000>;
387 hysteresis = <10000>;
388 type = "passive";
389 };
390 gpu_alert4: gpu-alert-4 {
391 temperature = <85000>;
392 hysteresis = <10000>;
393 type = "passive";
394 };
395 };
396 cooling-maps {
397 map0 {
398 trip = <&gpu_alert0>;
399 cooling-device = <&fan0 0 1>;
400 };
401 map1 {
402 trip = <&gpu_alert1>;
403 cooling-device = <&fan0 1 2>;
404 };
405 map2 {
406 trip = <&gpu_alert2>;
407 cooling-device = <&fan0 2 3>;
408 };
409 map3 {
410 trip = <&gpu_alert3>;
411 cooling-device = <&gpu 0 2>;
412 };
413 map4 {
414 trip = <&gpu_alert4>;
415 cooling-device = <&gpu 3 6>;
416 };
417 };
418 };
419 };
420};
421
422&buck10_reg {
423 /* Supplies vmmc-supply of mmc_0 */
424 regulator-always-on;
425 regulator-boot-on;
426};
427
428&hdmi {
429 status = "okay";
430 ddc = <&i2c_2>;
431 hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&hdmi_hpd_irq>;
434
435 vdd_osc-supply = <&ldo7_reg>;
436 vdd_pll-supply = <&ldo6_reg>;
437 vdd-supply = <&ldo6_reg>;
438};
439
440&hdmicec {
441 status = "okay";
442 needs-hpd;
443};
444
445&i2c_2 {
446 samsung,i2c-sda-delay = <100>;
447 samsung,i2c-max-bus-freq = <66000>;
448 /* used by HDMI DDC */
449 status = "okay";
450};
451
452&ldo26_reg {
453 regulator-min-microvolt = <3000000>;
454 regulator-max-microvolt = <3000000>;
455 regulator-always-on;
456};
457
458&mixer {
459 status = "okay";
460};
461
462&mmc_0 {
463 status = "okay";
464 mmc-pwrseq = <&emmc_pwrseq>;
465 card-detect-delay = <200>;
466 samsung,dw-mshc-ciu-div = <3>;
467 samsung,dw-mshc-sdr-timing = <0 4>;
468 samsung,dw-mshc-ddr-timing = <0 2>;
469 samsung,dw-mshc-hs400-timing = <0 2>;
470 samsung,read-strobe-delay = <90>;
471 pinctrl-names = "default";
472 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
473 bus-width = <8>;
474 cap-mmc-highspeed;
475 mmc-hs200-1_8v;
476 mmc-hs400-1_8v;
477 max-frequency = <200000000>;
478 vmmc-supply = <&ldo18_reg>;
479 vqmmc-supply = <&ldo3_reg>;
480};
481
482&pinctrl_0 {
483 power_key: power-key-pins {
484 samsung,pins = "gpx0-3";
485 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
486 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
487 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
488 };
489
490 hdmi_hpd_irq: hdmi-hpd-irq-pins {
491 samsung,pins = "gpx3-7";
492 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
493 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
494 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
495 };
496};
497
498&pinctrl_1 {
499 emmc_nrst_pin: emmc-nrst-pins {
500 samsung,pins = "gpd1-0";
501 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
502 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
503 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
504 };
505};
1/*
2 * Hardkernel Odroid XU3 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2014 Collabora Ltd.
7 * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
8 * Anand Moon <linux.amoon@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <dt-bindings/clock/samsung,s2mps11.h>
16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/sound/samsung-i2s.h>
19#include "exynos5800.dtsi"
20#include "exynos5422-cpus.dtsi"
21#include "exynos-mfc-reserved-memory.dtsi"
22
23/ {
24 memory@40000000 {
25 device_type = "memory";
26 reg = <0x40000000 0x7EA00000>;
27 };
28
29 chosen {
30 stdout-path = "serial2:115200n8";
31 };
32
33 firmware@02073000 {
34 compatible = "samsung,secure-firmware";
35 reg = <0x02073000 0x1000>;
36 };
37
38 fixed-rate-clocks {
39 oscclk {
40 compatible = "samsung,exynos5420-oscclk";
41 clock-frequency = <24000000>;
42 };
43 };
44
45 emmc_pwrseq: pwrseq {
46 pinctrl-0 = <&emmc_nrst_pin>;
47 pinctrl-names = "default";
48 compatible = "mmc-pwrseq-emmc";
49 reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
50 };
51
52 fan0: pwm-fan {
53 compatible = "pwm-fan";
54 pwms = <&pwm 0 20972 0>;
55 cooling-min-state = <0>;
56 cooling-max-state = <3>;
57 #cooling-cells = <2>;
58 cooling-levels = <0 130 170 230>;
59 };
60
61 thermal-zones {
62 cpu0_thermal: cpu0-thermal {
63 thermal-sensors = <&tmu_cpu0 0>;
64 polling-delay-passive = <250>;
65 polling-delay = <0>;
66 trips {
67 cpu_alert0: cpu-alert-0 {
68 temperature = <50000>; /* millicelsius */
69 hysteresis = <5000>; /* millicelsius */
70 type = "active";
71 };
72 cpu_alert1: cpu-alert-1 {
73 temperature = <60000>; /* millicelsius */
74 hysteresis = <5000>; /* millicelsius */
75 type = "active";
76 };
77 cpu_alert2: cpu-alert-2 {
78 temperature = <70000>; /* millicelsius */
79 hysteresis = <5000>; /* millicelsius */
80 type = "active";
81 };
82 cpu_crit0: cpu-crit-0 {
83 temperature = <120000>; /* millicelsius */
84 hysteresis = <0>; /* millicelsius */
85 type = "critical";
86 };
87 /*
88 * Exynos542x supports only 4 trip-points
89 * so for these polling mode is required.
90 * Start polling at temperature level of last
91 * interrupt-driven trip: cpu_alert2
92 */
93 cpu_alert3: cpu-alert-3 {
94 temperature = <70000>; /* millicelsius */
95 hysteresis = <10000>; /* millicelsius */
96 type = "passive";
97 };
98 cpu_alert4: cpu-alert-4 {
99 temperature = <85000>; /* millicelsius */
100 hysteresis = <10000>; /* millicelsius */
101 type = "passive";
102 };
103
104 };
105 cooling-maps {
106 map0 {
107 trip = <&cpu_alert0>;
108 cooling-device = <&fan0 0 1>;
109 };
110 map1 {
111 trip = <&cpu_alert1>;
112 cooling-device = <&fan0 1 2>;
113 };
114 map2 {
115 trip = <&cpu_alert2>;
116 cooling-device = <&fan0 2 3>;
117 };
118 /*
119 * When reaching cpu_alert3, reduce CPU
120 * by 2 steps. On Exynos5422/5800 that would
121 * be: 1600 MHz and 1100 MHz.
122 */
123 map3 {
124 trip = <&cpu_alert3>;
125 cooling-device = <&cpu0 0 2>;
126 };
127 map4 {
128 trip = <&cpu_alert3>;
129 cooling-device = <&cpu4 0 2>;
130 };
131
132 /*
133 * When reaching cpu_alert4, reduce CPU
134 * further, down to 600 MHz (11 steps for big,
135 * 7 steps for LITTLE).
136 */
137 map5 {
138 trip = <&cpu_alert4>;
139 cooling-device = <&cpu0 3 7>;
140 };
141 map6 {
142 trip = <&cpu_alert4>;
143 cooling-device = <&cpu4 3 11>;
144 };
145 };
146 };
147 };
148};
149
150&adc {
151 vdd-supply = <&ldo4_reg>;
152 status = "okay";
153};
154
155&bus_wcore {
156 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
157 <&nocp_mem1_0>, <&nocp_mem1_1>;
158 vdd-supply = <&buck3_reg>;
159 exynos,saturation-ratio = <100>;
160 status = "okay";
161};
162
163&bus_noc {
164 devfreq = <&bus_wcore>;
165 status = "okay";
166};
167
168&bus_fsys_apb {
169 devfreq = <&bus_wcore>;
170 status = "okay";
171};
172
173&bus_fsys {
174 devfreq = <&bus_wcore>;
175 status = "okay";
176};
177
178&bus_fsys2 {
179 devfreq = <&bus_wcore>;
180 status = "okay";
181};
182
183&bus_mfc {
184 devfreq = <&bus_wcore>;
185 status = "okay";
186};
187
188&bus_gen {
189 devfreq = <&bus_wcore>;
190 status = "okay";
191};
192
193&bus_peri {
194 devfreq = <&bus_wcore>;
195 status = "okay";
196};
197
198&bus_g2d {
199 devfreq = <&bus_wcore>;
200 status = "okay";
201};
202
203&bus_g2d_acp {
204 devfreq = <&bus_wcore>;
205 status = "okay";
206};
207
208&bus_jpeg {
209 devfreq = <&bus_wcore>;
210 status = "okay";
211};
212
213&bus_jpeg_apb {
214 devfreq = <&bus_wcore>;
215 status = "okay";
216};
217
218&bus_disp1_fimd {
219 devfreq = <&bus_wcore>;
220 status = "okay";
221};
222
223&bus_disp1 {
224 devfreq = <&bus_wcore>;
225 status = "okay";
226};
227
228&bus_gscl_scaler {
229 devfreq = <&bus_wcore>;
230 status = "okay";
231};
232
233&bus_mscl {
234 devfreq = <&bus_wcore>;
235 status = "okay";
236};
237
238&clock_audss {
239 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
240 <&clock_audss EXYNOS_MOUT_I2S>,
241 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
242 assigned-clock-parents = <&clock CLK_FIN_PLL>,
243 <&clock_audss EXYNOS_MOUT_AUDSS>;
244 assigned-clock-rates = <0>,
245 <0>,
246 <19200000>;
247};
248
249&cpu0 {
250 cpu-supply = <&buck6_reg>;
251};
252
253&cpu4 {
254 cpu-supply = <&buck2_reg>;
255};
256
257&hdmi {
258 status = "okay";
259 hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&hdmi_hpd_irq>;
262
263 vdd_osc-supply = <&ldo7_reg>;
264 vdd_pll-supply = <&ldo6_reg>;
265 vdd-supply = <&ldo6_reg>;
266};
267
268&hsi2c_4 {
269 status = "okay";
270
271 s2mps11_pmic@66 {
272 compatible = "samsung,s2mps11-pmic";
273 reg = <0x66>;
274 samsung,s2mps11-acokb-ground;
275
276 interrupt-parent = <&gpx0>;
277 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
278 pinctrl-names = "default";
279 pinctrl-0 = <&s2mps11_irq>;
280
281 s2mps11_osc: clocks {
282 #clock-cells = <1>;
283 clock-output-names = "s2mps11_ap",
284 "s2mps11_cp", "s2mps11_bt";
285 };
286
287 regulators {
288 ldo1_reg: LDO1 {
289 regulator-name = "vdd_ldo1";
290 regulator-min-microvolt = <1000000>;
291 regulator-max-microvolt = <1000000>;
292 regulator-always-on;
293 };
294
295 ldo3_reg: LDO3 {
296 regulator-name = "vddq_mmc0";
297 regulator-min-microvolt = <1800000>;
298 regulator-max-microvolt = <1800000>;
299 };
300
301 ldo4_reg: LDO4 {
302 regulator-name = "vdd_adc";
303 regulator-min-microvolt = <1800000>;
304 regulator-max-microvolt = <1800000>;
305 };
306
307 ldo5_reg: LDO5 {
308 regulator-name = "vdd_ldo5";
309 regulator-min-microvolt = <1800000>;
310 regulator-max-microvolt = <1800000>;
311 regulator-always-on;
312 };
313
314 ldo6_reg: LDO6 {
315 regulator-name = "vdd_ldo6";
316 regulator-min-microvolt = <1000000>;
317 regulator-max-microvolt = <1000000>;
318 regulator-always-on;
319 };
320
321 ldo7_reg: LDO7 {
322 regulator-name = "vdd_ldo7";
323 regulator-min-microvolt = <1800000>;
324 regulator-max-microvolt = <1800000>;
325 regulator-always-on;
326 };
327
328 ldo8_reg: LDO8 {
329 regulator-name = "vdd_ldo8";
330 regulator-min-microvolt = <1800000>;
331 regulator-max-microvolt = <1800000>;
332 regulator-always-on;
333 };
334
335 ldo9_reg: LDO9 {
336 regulator-name = "vdd_ldo9";
337 regulator-min-microvolt = <3000000>;
338 regulator-max-microvolt = <3000000>;
339 regulator-always-on;
340 };
341
342 ldo10_reg: LDO10 {
343 regulator-name = "vdd_ldo10";
344 regulator-min-microvolt = <1800000>;
345 regulator-max-microvolt = <1800000>;
346 regulator-always-on;
347 };
348
349 ldo11_reg: LDO11 {
350 regulator-name = "vdd_ldo11";
351 regulator-min-microvolt = <1000000>;
352 regulator-max-microvolt = <1000000>;
353 regulator-always-on;
354 };
355
356 ldo12_reg: LDO12 {
357 regulator-name = "vdd_ldo12";
358 regulator-min-microvolt = <1800000>;
359 regulator-max-microvolt = <1800000>;
360 regulator-always-on;
361 };
362
363 ldo13_reg: LDO13 {
364 regulator-name = "vddq_mmc2";
365 regulator-min-microvolt = <2800000>;
366 regulator-max-microvolt = <2800000>;
367 };
368
369 ldo15_reg: LDO15 {
370 regulator-name = "vdd_ldo15";
371 regulator-min-microvolt = <3100000>;
372 regulator-max-microvolt = <3100000>;
373 regulator-always-on;
374 };
375
376 ldo16_reg: LDO16 {
377 regulator-name = "vdd_ldo16";
378 regulator-min-microvolt = <2200000>;
379 regulator-max-microvolt = <2200000>;
380 regulator-always-on;
381 };
382
383 ldo17_reg: LDO17 {
384 regulator-name = "tsp_avdd";
385 regulator-min-microvolt = <3300000>;
386 regulator-max-microvolt = <3300000>;
387 regulator-always-on;
388 };
389
390 ldo18_reg: LDO18 {
391 regulator-name = "vdd_emmc_1V8";
392 regulator-min-microvolt = <1800000>;
393 regulator-max-microvolt = <1800000>;
394 };
395
396 ldo19_reg: LDO19 {
397 regulator-name = "vdd_sd";
398 regulator-min-microvolt = <2800000>;
399 regulator-max-microvolt = <2800000>;
400 };
401
402 ldo24_reg: LDO24 {
403 regulator-name = "tsp_io";
404 regulator-min-microvolt = <2800000>;
405 regulator-max-microvolt = <2800000>;
406 regulator-always-on;
407 };
408
409 ldo26_reg: LDO26 {
410 regulator-name = "vdd_ldo26";
411 regulator-min-microvolt = <3000000>;
412 regulator-max-microvolt = <3000000>;
413 regulator-always-on;
414 };
415
416 buck1_reg: BUCK1 {
417 regulator-name = "vdd_mif";
418 regulator-min-microvolt = <800000>;
419 regulator-max-microvolt = <1300000>;
420 regulator-always-on;
421 regulator-boot-on;
422 };
423
424 buck2_reg: BUCK2 {
425 regulator-name = "vdd_arm";
426 regulator-min-microvolt = <800000>;
427 regulator-max-microvolt = <1500000>;
428 regulator-always-on;
429 regulator-boot-on;
430 };
431
432 buck3_reg: BUCK3 {
433 regulator-name = "vdd_int";
434 regulator-min-microvolt = <800000>;
435 regulator-max-microvolt = <1400000>;
436 regulator-always-on;
437 regulator-boot-on;
438 };
439
440 buck4_reg: BUCK4 {
441 regulator-name = "vdd_g3d";
442 regulator-min-microvolt = <800000>;
443 regulator-max-microvolt = <1400000>;
444 regulator-always-on;
445 regulator-boot-on;
446 };
447
448 buck5_reg: BUCK5 {
449 regulator-name = "vdd_mem";
450 regulator-min-microvolt = <800000>;
451 regulator-max-microvolt = <1400000>;
452 regulator-always-on;
453 regulator-boot-on;
454 };
455
456 buck6_reg: BUCK6 {
457 regulator-name = "vdd_kfc";
458 regulator-min-microvolt = <800000>;
459 regulator-max-microvolt = <1500000>;
460 regulator-always-on;
461 regulator-boot-on;
462 };
463
464 buck7_reg: BUCK7 {
465 regulator-name = "vdd_1.0v_ldo";
466 regulator-min-microvolt = <800000>;
467 regulator-max-microvolt = <1500000>;
468 regulator-always-on;
469 regulator-boot-on;
470 };
471
472 buck8_reg: BUCK8 {
473 regulator-name = "vdd_1.8v_ldo";
474 regulator-min-microvolt = <800000>;
475 regulator-max-microvolt = <1500000>;
476 regulator-always-on;
477 regulator-boot-on;
478 };
479
480 buck9_reg: BUCK9 {
481 regulator-name = "vdd_2.8v_ldo";
482 regulator-min-microvolt = <3000000>;
483 regulator-max-microvolt = <3750000>;
484 regulator-always-on;
485 regulator-boot-on;
486 };
487
488 buck10_reg: BUCK10 {
489 regulator-name = "vdd_vmem";
490 regulator-min-microvolt = <2850000>;
491 regulator-max-microvolt = <2850000>;
492 regulator-always-on;
493 regulator-boot-on;
494 };
495 };
496 };
497};
498
499&i2c_2 {
500 samsung,i2c-sda-delay = <100>;
501 samsung,i2c-max-bus-freq = <66000>;
502 status = "okay";
503
504 hdmiddc@50 {
505 compatible = "samsung,exynos4210-hdmiddc";
506 reg = <0x50>;
507 };
508};
509
510&mmc_0 {
511 status = "okay";
512 mmc-pwrseq = <&emmc_pwrseq>;
513 card-detect-delay = <200>;
514 samsung,dw-mshc-ciu-div = <3>;
515 samsung,dw-mshc-sdr-timing = <0 4>;
516 samsung,dw-mshc-ddr-timing = <0 2>;
517 samsung,dw-mshc-hs400-timing = <0 2>;
518 samsung,read-strobe-delay = <90>;
519 pinctrl-names = "default";
520 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>;
521 bus-width = <8>;
522 cap-mmc-highspeed;
523 mmc-hs200-1_8v;
524 mmc-hs400-1_8v;
525 vmmc-supply = <&ldo18_reg>;
526 vqmmc-supply = <&ldo3_reg>;
527};
528
529&mmc_2 {
530 status = "okay";
531 card-detect-delay = <200>;
532 samsung,dw-mshc-ciu-div = <3>;
533 samsung,dw-mshc-sdr-timing = <0 4>;
534 samsung,dw-mshc-ddr-timing = <0 2>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
537 bus-width = <4>;
538 cap-sd-highspeed;
539 vmmc-supply = <&ldo19_reg>;
540 vqmmc-supply = <&ldo13_reg>;
541};
542
543&nocp_mem0_0 {
544 status = "okay";
545};
546
547&nocp_mem0_1 {
548 status = "okay";
549};
550
551&nocp_mem1_0 {
552 status = "okay";
553};
554
555&nocp_mem1_1 {
556 status = "okay";
557};
558
559&pinctrl_0 {
560 hdmi_hpd_irq: hdmi-hpd-irq {
561 samsung,pins = "gpx3-7";
562 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
563 samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
564 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
565 };
566
567 s2mps11_irq: s2mps11-irq {
568 samsung,pins = "gpx0-4";
569 samsung,pin-function = <EXYNOS_PIN_FUNC_F>;
570 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
571 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
572 };
573};
574
575&pinctrl_1 {
576 emmc_nrst_pin: emmc-nrst {
577 samsung,pins = "gpd1-0";
578 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
579 samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
580 samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
581 };
582};
583
584&tmu_cpu0 {
585 vtmu-supply = <&ldo7_reg>;
586};
587
588&tmu_cpu1 {
589 vtmu-supply = <&ldo7_reg>;
590};
591
592&tmu_cpu2 {
593 vtmu-supply = <&ldo7_reg>;
594};
595
596&tmu_cpu3 {
597 vtmu-supply = <&ldo7_reg>;
598};
599
600&tmu_gpu {
601 vtmu-supply = <&ldo7_reg>;
602};
603
604&rtc {
605 status = "okay";
606 clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
607 clock-names = "rtc", "rtc_src";
608};
609
610&usbdrd_dwc3_0 {
611 dr_mode = "host";
612};
613
614/* usbdrd_dwc3_1 mode customized in each board */
615
616&usbdrd3_0 {
617 vdd33-supply = <&ldo9_reg>;
618 vdd10-supply = <&ldo11_reg>;
619};
620
621&usbdrd3_1 {
622 vdd33-supply = <&ldo9_reg>;
623 vdd10-supply = <&ldo11_reg>;
624};