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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright(c) 2020 Intel Corporation. All rights reserved.
4//
5// Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
6//
7
8/*
9 * Hardware interface for audio DSP on Tigerlake.
10 */
11
12#include <sound/sof/ext_manifest4.h>
13#include "../ipc4-priv.h"
14#include "../ops.h"
15#include "hda.h"
16#include "hda-ipc.h"
17#include "../sof-audio.h"
18
19static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
20 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
21 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
22 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
23};
24
25static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
26{
27 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
28
29 /* power up primary core if not already powered up and return */
30 if (core == SOF_DSP_PRIMARY_CORE)
31 return hda_dsp_enable_core(sdev, BIT(core));
32
33 if (pm_ops->set_core_state)
34 return pm_ops->set_core_state(sdev, core, true);
35
36 return 0;
37}
38
39static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
40{
41 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
42
43 /* power down primary core and return */
44 if (core == SOF_DSP_PRIMARY_CORE)
45 return hda_dsp_core_reset_power_down(sdev, BIT(core));
46
47 if (pm_ops->set_core_state)
48 return pm_ops->set_core_state(sdev, core, false);
49
50 return 0;
51}
52
53/* Tigerlake ops */
54struct snd_sof_dsp_ops sof_tgl_ops;
55EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
56
57int sof_tgl_ops_init(struct snd_sof_dev *sdev)
58{
59 /* common defaults */
60 memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
61
62 /* probe/remove/shutdown */
63 sof_tgl_ops.shutdown = hda_dsp_shutdown_dma_flush;
64
65 if (sdev->pdata->ipc_type == SOF_IPC) {
66 /* doorbell */
67 sof_tgl_ops.irq_thread = cnl_ipc_irq_thread;
68
69 /* ipc */
70 sof_tgl_ops.send_msg = cnl_ipc_send_msg;
71
72 /* debug */
73 sof_tgl_ops.ipc_dump = cnl_ipc_dump;
74 }
75
76 if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
77 struct sof_ipc4_fw_data *ipc4_data;
78
79 sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
80 if (!sdev->private)
81 return -ENOMEM;
82
83 ipc4_data = sdev->private;
84 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
85
86 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
87
88 /* External library loading support */
89 ipc4_data->load_library = hda_dsp_ipc4_load_library;
90
91 /* doorbell */
92 sof_tgl_ops.irq_thread = cnl_ipc4_irq_thread;
93
94 /* ipc */
95 sof_tgl_ops.send_msg = cnl_ipc4_send_msg;
96
97 /* debug */
98 sof_tgl_ops.ipc_dump = cnl_ipc4_dump;
99 }
100
101 /* set DAI driver ops */
102 hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
103
104 /* debug */
105 sof_tgl_ops.debug_map = tgl_dsp_debugfs;
106 sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);
107
108 /* pre/post fw run */
109 sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
110
111 /* firmware run */
112 sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
113
114 /* dsp core get/put */
115 sof_tgl_ops.core_get = tgl_dsp_core_get;
116 sof_tgl_ops.core_put = tgl_dsp_core_put;
117
118 return 0;
119};
120EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
121
122const struct sof_intel_dsp_desc tgl_chip_info = {
123 /* Tigerlake , Alderlake */
124 .cores_num = 4,
125 .init_core_mask = 1,
126 .host_managed_cores_mask = BIT(0),
127 .ipc_req = CNL_DSP_REG_HIPCIDR,
128 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
129 .ipc_ack = CNL_DSP_REG_HIPCIDA,
130 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
131 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
132 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
133 .rom_init_timeout = 300,
134 .ssp_count = TGL_SSP_COUNT,
135 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
136 .sdw_shim_base = SDW_SHIM_BASE,
137 .sdw_alh_base = SDW_ALH_BASE,
138 .d0i3_offset = SOF_HDA_VS_D0I3C,
139 .read_sdw_lcount = hda_sdw_check_lcount_common,
140 .enable_sdw_irq = hda_common_enable_sdw_irq,
141 .check_sdw_irq = hda_common_check_sdw_irq,
142 .check_ipc_irq = hda_dsp_check_ipc_irq,
143 .cl_init = cl_dsp_init,
144 .power_down_dsp = hda_power_down_dsp,
145 .disable_interrupts = hda_dsp_disable_interrupts,
146 .hw_ip_version = SOF_INTEL_CAVS_2_5,
147};
148EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
149
150const struct sof_intel_dsp_desc tglh_chip_info = {
151 /* Tigerlake-H */
152 .cores_num = 2,
153 .init_core_mask = 1,
154 .host_managed_cores_mask = BIT(0),
155 .ipc_req = CNL_DSP_REG_HIPCIDR,
156 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
157 .ipc_ack = CNL_DSP_REG_HIPCIDA,
158 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
159 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
160 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
161 .rom_init_timeout = 300,
162 .ssp_count = TGL_SSP_COUNT,
163 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
164 .sdw_shim_base = SDW_SHIM_BASE,
165 .sdw_alh_base = SDW_ALH_BASE,
166 .d0i3_offset = SOF_HDA_VS_D0I3C,
167 .read_sdw_lcount = hda_sdw_check_lcount_common,
168 .enable_sdw_irq = hda_common_enable_sdw_irq,
169 .check_sdw_irq = hda_common_check_sdw_irq,
170 .check_ipc_irq = hda_dsp_check_ipc_irq,
171 .cl_init = cl_dsp_init,
172 .power_down_dsp = hda_power_down_dsp,
173 .disable_interrupts = hda_dsp_disable_interrupts,
174 .hw_ip_version = SOF_INTEL_CAVS_2_5,
175};
176EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
177
178const struct sof_intel_dsp_desc ehl_chip_info = {
179 /* Elkhartlake */
180 .cores_num = 4,
181 .init_core_mask = 1,
182 .host_managed_cores_mask = BIT(0),
183 .ipc_req = CNL_DSP_REG_HIPCIDR,
184 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
185 .ipc_ack = CNL_DSP_REG_HIPCIDA,
186 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
187 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
188 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
189 .rom_init_timeout = 300,
190 .ssp_count = TGL_SSP_COUNT,
191 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
192 .sdw_shim_base = SDW_SHIM_BASE,
193 .sdw_alh_base = SDW_ALH_BASE,
194 .d0i3_offset = SOF_HDA_VS_D0I3C,
195 .read_sdw_lcount = hda_sdw_check_lcount_common,
196 .enable_sdw_irq = hda_common_enable_sdw_irq,
197 .check_sdw_irq = hda_common_check_sdw_irq,
198 .check_ipc_irq = hda_dsp_check_ipc_irq,
199 .cl_init = cl_dsp_init,
200 .power_down_dsp = hda_power_down_dsp,
201 .disable_interrupts = hda_dsp_disable_interrupts,
202 .hw_ip_version = SOF_INTEL_CAVS_2_5,
203};
204EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
205
206const struct sof_intel_dsp_desc adls_chip_info = {
207 /* Alderlake-S */
208 .cores_num = 2,
209 .init_core_mask = BIT(0),
210 .host_managed_cores_mask = BIT(0),
211 .ipc_req = CNL_DSP_REG_HIPCIDR,
212 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
213 .ipc_ack = CNL_DSP_REG_HIPCIDA,
214 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
215 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
216 .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
217 .rom_init_timeout = 300,
218 .ssp_count = TGL_SSP_COUNT,
219 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
220 .sdw_shim_base = SDW_SHIM_BASE,
221 .sdw_alh_base = SDW_ALH_BASE,
222 .d0i3_offset = SOF_HDA_VS_D0I3C,
223 .read_sdw_lcount = hda_sdw_check_lcount_common,
224 .enable_sdw_irq = hda_common_enable_sdw_irq,
225 .check_sdw_irq = hda_common_check_sdw_irq,
226 .check_ipc_irq = hda_dsp_check_ipc_irq,
227 .cl_init = cl_dsp_init,
228 .power_down_dsp = hda_power_down_dsp,
229 .disable_interrupts = hda_dsp_disable_interrupts,
230 .hw_ip_version = SOF_INTEL_CAVS_2_5,
231};
232EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);