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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2018 Intel Corporation. All rights reserved.
7//
8// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10// Rander Wang <rander.wang@intel.com>
11// Keyon Jie <yang.jie@linux.intel.com>
12//
13
14/*
15 * Hardware interface for HDA DSP code loader
16 */
17
18#include <linux/firmware.h>
19#include <sound/hdaudio_ext.h>
20#include <sound/hda_register.h>
21#include <sound/sof.h>
22#include <sound/sof/ipc4/header.h>
23#include "ext_manifest.h"
24#include "../ipc4-priv.h"
25#include "../ops.h"
26#include "../sof-priv.h"
27#include "hda.h"
28
29static void hda_ssp_set_cbp_cfp(struct snd_sof_dev *sdev)
30{
31 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
32 const struct sof_intel_dsp_desc *chip = hda->desc;
33 int i;
34
35 /* DSP is powered up, set all SSPs to clock consumer/codec provider mode */
36 for (i = 0; i < chip->ssp_count; i++) {
37 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
38 chip->ssp_base_offset
39 + i * SSP_DEV_MEM_SIZE
40 + SSP_SSC1_OFFSET,
41 SSP_SET_CBP_CFP,
42 SSP_SET_CBP_CFP);
43 }
44}
45
46struct hdac_ext_stream *hda_cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
47 unsigned int size, struct snd_dma_buffer *dmab,
48 int direction)
49{
50 struct hdac_ext_stream *hext_stream;
51 struct hdac_stream *hstream;
52 struct pci_dev *pci = to_pci_dev(sdev->dev);
53 int ret;
54
55 hext_stream = hda_dsp_stream_get(sdev, direction, 0);
56
57 if (!hext_stream) {
58 dev_err(sdev->dev, "error: no stream available\n");
59 return ERR_PTR(-ENODEV);
60 }
61 hstream = &hext_stream->hstream;
62 hstream->substream = NULL;
63
64 /* allocate DMA buffer */
65 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
66 if (ret < 0) {
67 dev_err(sdev->dev, "error: memory alloc failed: %d\n", ret);
68 goto out_put;
69 }
70
71 hstream->period_bytes = 0;/* initialize period_bytes */
72 hstream->format_val = format;
73 hstream->bufsize = size;
74
75 if (direction == SNDRV_PCM_STREAM_CAPTURE) {
76 ret = hda_dsp_iccmax_stream_hw_params(sdev, hext_stream, dmab, NULL);
77 if (ret < 0) {
78 dev_err(sdev->dev, "error: iccmax stream prepare failed: %d\n", ret);
79 goto out_free;
80 }
81 } else {
82 ret = hda_dsp_stream_hw_params(sdev, hext_stream, dmab, NULL);
83 if (ret < 0) {
84 dev_err(sdev->dev, "error: hdac prepare failed: %d\n", ret);
85 goto out_free;
86 }
87 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_ENABLE, size);
88 }
89
90 return hext_stream;
91
92out_free:
93 snd_dma_free_pages(dmab);
94out_put:
95 hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
96 return ERR_PTR(ret);
97}
98
99/*
100 * first boot sequence has some extra steps.
101 * power on all host managed cores and only unstall/run the boot core to boot the
102 * DSP then turn off all non boot cores (if any) is powered on.
103 */
104int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot)
105{
106 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
107 const struct sof_intel_dsp_desc *chip = hda->desc;
108 unsigned int status, target_status;
109 u32 flags, ipc_hdr, j;
110 unsigned long mask;
111 char *dump_msg;
112 int ret;
113
114 /* step 1: power up corex */
115 ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
116 if (ret < 0) {
117 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
118 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
119 goto err;
120 }
121
122 hda_ssp_set_cbp_cfp(sdev);
123
124 /* step 2: Send ROM_CONTROL command (stream_tag is ignored for IMR boot) */
125 ipc_hdr = chip->ipc_req_mask | HDA_DSP_ROM_IPC_CONTROL;
126 if (!imr_boot)
127 ipc_hdr |= HDA_DSP_ROM_IPC_PURGE_FW | ((stream_tag - 1) << 9);
128
129 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req, ipc_hdr);
130
131 /* step 3: unset core 0 reset state & unstall/run core 0 */
132 ret = hda_dsp_core_run(sdev, chip->init_core_mask);
133 if (ret < 0) {
134 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
135 dev_err(sdev->dev,
136 "error: dsp core start failed %d\n", ret);
137 ret = -EIO;
138 goto err;
139 }
140
141 /* step 4: wait for IPC DONE bit from ROM */
142 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
143 chip->ipc_ack, status,
144 ((status & chip->ipc_ack_mask)
145 == chip->ipc_ack_mask),
146 HDA_DSP_REG_POLL_INTERVAL_US,
147 HDA_DSP_INIT_TIMEOUT_US);
148
149 if (ret < 0) {
150 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
151 dev_err(sdev->dev,
152 "error: %s: timeout for HIPCIE done\n",
153 __func__);
154 goto err;
155 }
156
157 /* set DONE bit to clear the reply IPC message */
158 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
159 chip->ipc_ack,
160 chip->ipc_ack_mask,
161 chip->ipc_ack_mask);
162
163 /* step 5: power down cores that are no longer needed */
164 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask &
165 ~(chip->init_core_mask));
166 if (ret < 0) {
167 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
168 dev_err(sdev->dev,
169 "error: dsp core x power down failed\n");
170 goto err;
171 }
172
173 /* step 6: enable IPC interrupts */
174 hda_dsp_ipc_int_enable(sdev);
175
176 /*
177 * step 7:
178 * - Cold/Full boot: wait for ROM init to proceed to download the firmware
179 * - IMR boot: wait for ROM firmware entered (firmware booted up from IMR)
180 */
181 if (imr_boot)
182 target_status = FSR_STATE_FW_ENTERED;
183 else
184 target_status = FSR_STATE_INIT_DONE;
185
186 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
187 chip->rom_status_reg, status,
188 (FSR_TO_STATE_CODE(status) == target_status),
189 HDA_DSP_REG_POLL_INTERVAL_US,
190 chip->rom_init_timeout *
191 USEC_PER_MSEC);
192 if (!ret) {
193 /* set enabled cores mask and increment ref count for cores in init_core_mask */
194 sdev->enabled_cores_mask |= chip->init_core_mask;
195 mask = sdev->enabled_cores_mask;
196 for_each_set_bit(j, &mask, SOF_MAX_DSP_NUM_CORES)
197 sdev->dsp_core_ref_count[j]++;
198 return 0;
199 }
200
201 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
202 dev_err(sdev->dev,
203 "%s: timeout with rom_status_reg (%#x) read\n",
204 __func__, chip->rom_status_reg);
205
206err:
207 flags = SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX | SOF_DBG_DUMP_OPTIONAL;
208
209 /* after max boot attempts make sure that the dump is printed */
210 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
211 flags &= ~SOF_DBG_DUMP_OPTIONAL;
212
213 dump_msg = kasprintf(GFP_KERNEL, "Boot iteration failed: %d/%d",
214 hda->boot_iteration, HDA_FW_BOOT_ATTEMPTS);
215 snd_sof_dsp_dbg_dump(sdev, dump_msg, flags);
216 hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
217
218 kfree(dump_msg);
219 return ret;
220}
221
222static int cl_trigger(struct snd_sof_dev *sdev,
223 struct hdac_ext_stream *hext_stream, int cmd)
224{
225 struct hdac_stream *hstream = &hext_stream->hstream;
226 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
227
228 /* code loader is special case that reuses stream ops */
229 switch (cmd) {
230 case SNDRV_PCM_TRIGGER_START:
231 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
232 1 << hstream->index,
233 1 << hstream->index);
234
235 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
236 sd_offset,
237 SOF_HDA_SD_CTL_DMA_START |
238 SOF_HDA_CL_DMA_SD_INT_MASK,
239 SOF_HDA_SD_CTL_DMA_START |
240 SOF_HDA_CL_DMA_SD_INT_MASK);
241
242 hstream->running = true;
243 return 0;
244 default:
245 return hda_dsp_stream_trigger(sdev, hext_stream, cmd);
246 }
247}
248
249int hda_cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
250 struct hdac_ext_stream *hext_stream)
251{
252 struct hdac_stream *hstream = &hext_stream->hstream;
253 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
254 int ret = 0;
255
256 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
257 ret = hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
258 else
259 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
260 SOF_HDA_SD_CTL_DMA_START, 0);
261
262 hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag);
263 hstream->running = 0;
264 hstream->substream = NULL;
265
266 /* reset BDL address */
267 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
268 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL, 0);
269 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
270 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU, 0);
271
272 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
273 snd_dma_free_pages(dmab);
274 dmab->area = NULL;
275 hstream->bufsize = 0;
276 hstream->format_val = 0;
277
278 return ret;
279}
280
281int hda_cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream)
282{
283 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
284 const struct sof_intel_dsp_desc *chip = hda->desc;
285 unsigned int reg;
286 int ret, status;
287
288 ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_START);
289 if (ret < 0) {
290 dev_err(sdev->dev, "error: DMA trigger start failed\n");
291 return ret;
292 }
293
294 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
295 chip->rom_status_reg, reg,
296 (FSR_TO_STATE_CODE(reg) == FSR_STATE_FW_ENTERED),
297 HDA_DSP_REG_POLL_INTERVAL_US,
298 HDA_DSP_BASEFW_TIMEOUT_US);
299
300 /*
301 * even in case of errors we still need to stop the DMAs,
302 * but we return the initial error should the DMA stop also fail
303 */
304
305 if (status < 0) {
306 dev_err(sdev->dev,
307 "%s: timeout with rom_status_reg (%#x) read\n",
308 __func__, chip->rom_status_reg);
309 }
310
311 ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_STOP);
312 if (ret < 0) {
313 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
314 if (!status)
315 status = ret;
316 }
317
318 return status;
319}
320
321int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
322{
323 struct hdac_ext_stream *iccmax_stream;
324 struct hdac_bus *bus = sof_to_bus(sdev);
325 struct snd_dma_buffer dmab_bdl;
326 int ret, ret1;
327 u8 original_gb;
328
329 /* save the original LTRP guardband value */
330 original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK;
331
332 /*
333 * Prepare capture stream for ICCMAX. We do not need to store
334 * the data, so use a buffer of PAGE_SIZE for receiving.
335 */
336 iccmax_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, PAGE_SIZE,
337 &dmab_bdl, SNDRV_PCM_STREAM_CAPTURE);
338 if (IS_ERR(iccmax_stream)) {
339 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
340 return PTR_ERR(iccmax_stream);
341 }
342
343 ret = hda_dsp_cl_boot_firmware(sdev);
344
345 /*
346 * Perform iccmax stream cleanup. This should be done even if firmware loading fails.
347 * If the cleanup also fails, we return the initial error
348 */
349 ret1 = hda_cl_cleanup(sdev, &dmab_bdl, iccmax_stream);
350 if (ret1 < 0) {
351 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
352
353 /* set return value to indicate cleanup failure */
354 if (!ret)
355 ret = ret1;
356 }
357
358 /* restore the original guardband value after FW boot */
359 snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb);
360
361 return ret;
362}
363
364static int hda_dsp_boot_imr(struct snd_sof_dev *sdev)
365{
366 const struct sof_intel_dsp_desc *chip_info;
367 int ret;
368
369 chip_info = get_chip_info(sdev->pdata);
370 if (chip_info->cl_init)
371 ret = chip_info->cl_init(sdev, 0, true);
372 else
373 ret = -EINVAL;
374
375 if (!ret)
376 hda_sdw_process_wakeen(sdev);
377
378 return ret;
379}
380
381int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
382{
383 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
384 struct snd_sof_pdata *plat_data = sdev->pdata;
385 const struct sof_dev_desc *desc = plat_data->desc;
386 const struct sof_intel_dsp_desc *chip_info;
387 struct hdac_ext_stream *hext_stream;
388 struct firmware stripped_firmware;
389 struct snd_dma_buffer dmab;
390 int ret, ret1, i;
391
392 if (hda->imrboot_supported && !sdev->first_boot && !hda->skip_imr_boot) {
393 dev_dbg(sdev->dev, "IMR restore supported, booting from IMR directly\n");
394 hda->boot_iteration = 0;
395 ret = hda_dsp_boot_imr(sdev);
396 if (!ret) {
397 hda->booted_from_imr = true;
398 return 0;
399 }
400
401 dev_warn(sdev->dev, "IMR restore failed, trying to cold boot\n");
402 }
403
404 hda->booted_from_imr = false;
405
406 chip_info = desc->chip_info;
407
408 if (sdev->basefw.fw->size <= sdev->basefw.payload_offset) {
409 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
410 return -EINVAL;
411 }
412
413 stripped_firmware.data = sdev->basefw.fw->data + sdev->basefw.payload_offset;
414 stripped_firmware.size = sdev->basefw.fw->size - sdev->basefw.payload_offset;
415
416 /* init for booting wait */
417 init_waitqueue_head(&sdev->boot_wait);
418
419 /* prepare DMA for code loader stream */
420 hext_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT,
421 stripped_firmware.size,
422 &dmab, SNDRV_PCM_STREAM_PLAYBACK);
423 if (IS_ERR(hext_stream)) {
424 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
425 return PTR_ERR(hext_stream);
426 }
427
428 memcpy(dmab.area, stripped_firmware.data,
429 stripped_firmware.size);
430
431 /* try ROM init a few times before giving up */
432 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
433 dev_dbg(sdev->dev,
434 "Attempting iteration %d of Core En/ROM load...\n", i);
435
436 hda->boot_iteration = i + 1;
437 if (chip_info->cl_init)
438 ret = chip_info->cl_init(sdev, hext_stream->hstream.stream_tag, false);
439 else
440 ret = -EINVAL;
441
442 /* don't retry anymore if successful */
443 if (!ret)
444 break;
445 }
446
447 if (i == HDA_FW_BOOT_ATTEMPTS) {
448 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
449 i, ret);
450 goto cleanup;
451 }
452
453 /*
454 * When a SoundWire link is in clock stop state, a Slave
455 * device may trigger in-band wakes for events such as jack
456 * insertion or acoustic event detection. This event will lead
457 * to a WAKEEN interrupt, handled by the PCI device and routed
458 * to PME if the PCI device is in D3. The resume function in
459 * audio PCI driver will be invoked by ACPI for PME event and
460 * initialize the device and process WAKEEN interrupt.
461 *
462 * The WAKEEN interrupt should be processed ASAP to prevent an
463 * interrupt flood, otherwise other interrupts, such IPC,
464 * cannot work normally. The WAKEEN is handled after the ROM
465 * is initialized successfully, which ensures power rails are
466 * enabled before accessing the SoundWire SHIM registers
467 */
468 if (!sdev->first_boot)
469 hda_sdw_process_wakeen(sdev);
470
471 /*
472 * Set the boot_iteration to the last attempt, indicating that the
473 * DSP ROM has been initialized and from this point there will be no
474 * retry done to boot.
475 *
476 * Continue with code loading and firmware boot
477 */
478 hda->boot_iteration = HDA_FW_BOOT_ATTEMPTS;
479 ret = hda_cl_copy_fw(sdev, hext_stream);
480 if (!ret) {
481 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
482 hda->skip_imr_boot = false;
483 } else {
484 snd_sof_dsp_dbg_dump(sdev, "Firmware download failed",
485 SOF_DBG_DUMP_PCI | SOF_DBG_DUMP_MBOX);
486 hda->skip_imr_boot = true;
487 }
488
489cleanup:
490 /*
491 * Perform codeloader stream cleanup.
492 * This should be done even if firmware loading fails.
493 * If the cleanup also fails, we return the initial error
494 */
495 ret1 = hda_cl_cleanup(sdev, &dmab, hext_stream);
496 if (ret1 < 0) {
497 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
498
499 /* set return value to indicate cleanup failure */
500 if (!ret)
501 ret = ret1;
502 }
503
504 /*
505 * return primary core id if both fw copy
506 * and stream clean up are successful
507 */
508 if (!ret)
509 return chip_info->init_core_mask;
510
511 /* disable DSP */
512 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
513 SOF_HDA_REG_PP_PPCTL,
514 SOF_HDA_PPCTL_GPROCEN, 0);
515 return ret;
516}
517
518int hda_dsp_ipc4_load_library(struct snd_sof_dev *sdev,
519 struct sof_ipc4_fw_library *fw_lib, bool reload)
520{
521 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
522 struct hdac_ext_stream *hext_stream;
523 struct firmware stripped_firmware;
524 struct sof_ipc4_msg msg = {};
525 struct snd_dma_buffer dmab;
526 int ret, ret1;
527
528 /* IMR booting will restore the libraries as well, skip the loading */
529 if (reload && hda->booted_from_imr)
530 return 0;
531
532 /* the fw_lib has been verified during loading, we can trust the validity here */
533 stripped_firmware.data = fw_lib->sof_fw.fw->data + fw_lib->sof_fw.payload_offset;
534 stripped_firmware.size = fw_lib->sof_fw.fw->size - fw_lib->sof_fw.payload_offset;
535
536 /* prepare DMA for code loader stream */
537 hext_stream = hda_cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT,
538 stripped_firmware.size,
539 &dmab, SNDRV_PCM_STREAM_PLAYBACK);
540 if (IS_ERR(hext_stream)) {
541 dev_err(sdev->dev, "%s: DMA prepare failed\n", __func__);
542 return PTR_ERR(hext_stream);
543 }
544
545 memcpy(dmab.area, stripped_firmware.data, stripped_firmware.size);
546
547 msg.primary = hext_stream->hstream.stream_tag - 1;
548 msg.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_LOAD_LIBRARY);
549 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
550 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
551 msg.primary |= SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(fw_lib->id);
552
553 ret = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_START);
554 if (ret < 0) {
555 dev_err(sdev->dev, "%s: DMA trigger start failed\n", __func__);
556 goto cleanup;
557 }
558
559 ret = sof_ipc_tx_message(sdev->ipc, &msg, 0, NULL, 0);
560
561 ret1 = cl_trigger(sdev, hext_stream, SNDRV_PCM_TRIGGER_STOP);
562 if (ret1 < 0) {
563 dev_err(sdev->dev, "%s: DMA trigger stop failed\n", __func__);
564 if (!ret)
565 ret = ret1;
566 }
567
568cleanup:
569 /* clean up even in case of error and return the first error */
570 ret1 = hda_cl_cleanup(sdev, &dmab, hext_stream);
571 if (ret1 < 0) {
572 dev_err(sdev->dev, "%s: Code loader DSP cleanup failed\n", __func__);
573
574 /* set return value to indicate cleanup failure */
575 if (!ret)
576 ret = ret1;
577 }
578
579 return ret;
580}
581
582/* pre fw run operations */
583int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
584{
585 /* disable clock gating and power gating */
586 return hda_dsp_ctrl_clock_power_gating(sdev, false);
587}
588
589/* post fw run operations */
590int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
591{
592 int ret;
593
594 if (sdev->first_boot) {
595 struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
596
597 ret = hda_sdw_startup(sdev);
598 if (ret < 0) {
599 dev_err(sdev->dev,
600 "error: could not startup SoundWire links\n");
601 return ret;
602 }
603
604 /* Check if IMR boot is usable */
605 if (!sof_debug_check_flag(SOF_DBG_IGNORE_D3_PERSISTENT) &&
606 (sdev->fw_ready.flags & SOF_IPC_INFO_D3_PERSISTENT ||
607 sdev->pdata->ipc_type == SOF_INTEL_IPC4))
608 hdev->imrboot_supported = true;
609 }
610
611 hda_sdw_int_enable(sdev, true);
612
613 /* re-enable clock gating and power gating */
614 return hda_dsp_ctrl_clock_power_gating(sdev, true);
615}
616
617int hda_dsp_ext_man_get_cavs_config_data(struct snd_sof_dev *sdev,
618 const struct sof_ext_man_elem_header *hdr)
619{
620 const struct sof_ext_man_cavs_config_data *config_data =
621 container_of(hdr, struct sof_ext_man_cavs_config_data, hdr);
622 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
623 int i, elem_num;
624
625 /* calculate total number of config data elements */
626 elem_num = (hdr->size - sizeof(struct sof_ext_man_elem_header))
627 / sizeof(struct sof_config_elem);
628 if (elem_num <= 0) {
629 dev_err(sdev->dev, "cavs config data is inconsistent: %d\n", elem_num);
630 return -EINVAL;
631 }
632
633 for (i = 0; i < elem_num; i++)
634 switch (config_data->elems[i].token) {
635 case SOF_EXT_MAN_CAVS_CONFIG_EMPTY:
636 /* skip empty token */
637 break;
638 case SOF_EXT_MAN_CAVS_CONFIG_CAVS_LPRO:
639 hda->clk_config_lpro = config_data->elems[i].value;
640 dev_dbg(sdev->dev, "FW clock config: %s\n",
641 hda->clk_config_lpro ? "LPRO" : "HPRO");
642 break;
643 case SOF_EXT_MAN_CAVS_CONFIG_OUTBOX_SIZE:
644 case SOF_EXT_MAN_CAVS_CONFIG_INBOX_SIZE:
645 /* These elements are defined but not being used yet. No warn is required */
646 break;
647 default:
648 dev_info(sdev->dev, "unsupported token type: %d\n",
649 config_data->elems[i].token);
650 }
651
652 return 0;
653}