Loading...
Note: File does not exist in v3.5.6.
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Author: Andrzej Hajda <a.hajda@samsung.com>
5 *
6 * Device Tree binding constants for Exynos5420 clock controller.
7 */
8
9#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
10#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
11
12/* core clocks */
13#define CLK_FIN_PLL 1
14#define CLK_FOUT_APLL 2
15#define CLK_FOUT_CPLL 3
16#define CLK_FOUT_DPLL 4
17#define CLK_FOUT_EPLL 5
18#define CLK_FOUT_RPLL 6
19#define CLK_FOUT_IPLL 7
20#define CLK_FOUT_SPLL 8
21#define CLK_FOUT_VPLL 9
22#define CLK_FOUT_MPLL 10
23#define CLK_FOUT_BPLL 11
24#define CLK_FOUT_KPLL 12
25#define CLK_ARM_CLK 13
26#define CLK_KFC_CLK 14
27
28/* gate for special clocks (sclk) */
29#define CLK_SCLK_UART0 128
30#define CLK_SCLK_UART1 129
31#define CLK_SCLK_UART2 130
32#define CLK_SCLK_UART3 131
33#define CLK_SCLK_MMC0 132
34#define CLK_SCLK_MMC1 133
35#define CLK_SCLK_MMC2 134
36#define CLK_SCLK_SPI0 135
37#define CLK_SCLK_SPI1 136
38#define CLK_SCLK_SPI2 137
39#define CLK_SCLK_I2S1 138
40#define CLK_SCLK_I2S2 139
41#define CLK_SCLK_PCM1 140
42#define CLK_SCLK_PCM2 141
43#define CLK_SCLK_SPDIF 142
44#define CLK_SCLK_HDMI 143
45#define CLK_SCLK_PIXEL 144
46#define CLK_SCLK_DP1 145
47#define CLK_SCLK_MIPI1 146
48#define CLK_SCLK_FIMD1 147
49#define CLK_SCLK_MAUDIO0 148
50#define CLK_SCLK_MAUPCM0 149
51#define CLK_SCLK_USBD300 150
52#define CLK_SCLK_USBD301 151
53#define CLK_SCLK_USBPHY300 152
54#define CLK_SCLK_USBPHY301 153
55#define CLK_SCLK_UNIPRO 154
56#define CLK_SCLK_PWM 155
57#define CLK_SCLK_GSCL_WA 156
58#define CLK_SCLK_GSCL_WB 157
59#define CLK_SCLK_HDMIPHY 158
60#define CLK_MAU_EPLL 159
61#define CLK_SCLK_HSIC_12M 160
62#define CLK_SCLK_MPHY_IXTAL24 161
63#define CLK_SCLK_BPLL 162
64
65/* gate clocks */
66#define CLK_UART0 257
67#define CLK_UART1 258
68#define CLK_UART2 259
69#define CLK_UART3 260
70#define CLK_I2C0 261
71#define CLK_I2C1 262
72#define CLK_I2C2 263
73#define CLK_I2C3 264
74#define CLK_USI0 265
75#define CLK_USI1 266
76#define CLK_USI2 267
77#define CLK_USI3 268
78#define CLK_I2C_HDMI 269
79#define CLK_TSADC 270
80#define CLK_SPI0 271
81#define CLK_SPI1 272
82#define CLK_SPI2 273
83#define CLK_KEYIF 274
84#define CLK_I2S1 275
85#define CLK_I2S2 276
86#define CLK_PCM1 277
87#define CLK_PCM2 278
88#define CLK_PWM 279
89#define CLK_SPDIF 280
90#define CLK_USI4 281
91#define CLK_USI5 282
92#define CLK_USI6 283
93#define CLK_ACLK66_PSGEN 300
94#define CLK_CHIPID 301
95#define CLK_SYSREG 302
96#define CLK_TZPC0 303
97#define CLK_TZPC1 304
98#define CLK_TZPC2 305
99#define CLK_TZPC3 306
100#define CLK_TZPC4 307
101#define CLK_TZPC5 308
102#define CLK_TZPC6 309
103#define CLK_TZPC7 310
104#define CLK_TZPC8 311
105#define CLK_TZPC9 312
106#define CLK_HDMI_CEC 313
107#define CLK_SECKEY 314
108#define CLK_MCT 315
109#define CLK_WDT 316
110#define CLK_RTC 317
111#define CLK_TMU 318
112#define CLK_TMU_GPU 319
113#define CLK_PCLK66_GPIO 330
114#define CLK_ACLK200_FSYS2 350
115#define CLK_MMC0 351
116#define CLK_MMC1 352
117#define CLK_MMC2 353
118#define CLK_SROMC 354
119#define CLK_UFS 355
120#define CLK_ACLK200_FSYS 360
121#define CLK_TSI 361
122#define CLK_PDMA0 362
123#define CLK_PDMA1 363
124#define CLK_RTIC 364
125#define CLK_USBH20 365
126#define CLK_USBD300 366
127#define CLK_USBD301 367
128#define CLK_ACLK400_MSCL 380
129#define CLK_MSCL0 381
130#define CLK_MSCL1 382
131#define CLK_MSCL2 383
132#define CLK_SMMU_MSCL0 384
133#define CLK_SMMU_MSCL1 385
134#define CLK_SMMU_MSCL2 386
135#define CLK_ACLK333 400
136#define CLK_MFC 401
137#define CLK_SMMU_MFCL 402
138#define CLK_SMMU_MFCR 403
139#define CLK_ACLK200_DISP1 410
140#define CLK_DSIM1 411
141#define CLK_DP1 412
142#define CLK_HDMI 413
143#define CLK_ACLK300_DISP1 420
144#define CLK_FIMD1 421
145#define CLK_SMMU_FIMD1M0 422
146#define CLK_SMMU_FIMD1M1 423
147#define CLK_ACLK166 430
148#define CLK_MIXER 431
149#define CLK_ACLK266 440
150#define CLK_ROTATOR 441
151#define CLK_MDMA1 442
152#define CLK_SMMU_ROTATOR 443
153#define CLK_SMMU_MDMA1 444
154#define CLK_ACLK300_JPEG 450
155#define CLK_JPEG 451
156#define CLK_JPEG2 452
157#define CLK_SMMU_JPEG 453
158#define CLK_SMMU_JPEG2 454
159#define CLK_ACLK300_GSCL 460
160#define CLK_SMMU_GSCL0 461
161#define CLK_SMMU_GSCL1 462
162#define CLK_GSCL_WA 463
163#define CLK_GSCL_WB 464
164#define CLK_GSCL0 465
165#define CLK_GSCL1 466
166#define CLK_FIMC_3AA 467
167#define CLK_ACLK266_G2D 470
168#define CLK_SSS 471
169#define CLK_SLIM_SSS 472
170#define CLK_MDMA0 473
171#define CLK_ACLK333_G2D 480
172#define CLK_G2D 481
173#define CLK_ACLK333_432_GSCL 490
174#define CLK_SMMU_3AA 491
175#define CLK_SMMU_FIMCL0 492
176#define CLK_SMMU_FIMCL1 493
177#define CLK_SMMU_FIMCL3 494
178#define CLK_FIMC_LITE3 495
179#define CLK_FIMC_LITE0 496
180#define CLK_FIMC_LITE1 497
181#define CLK_ACLK_G3D 500
182#define CLK_G3D 501
183#define CLK_SMMU_MIXER 502
184#define CLK_SMMU_G2D 503
185#define CLK_SMMU_MDMA0 504
186#define CLK_MC 505
187#define CLK_TOP_RTC 506
188#define CLK_SCLK_UART_ISP 510
189#define CLK_SCLK_SPI0_ISP 511
190#define CLK_SCLK_SPI1_ISP 512
191#define CLK_SCLK_PWM_ISP 513
192#define CLK_SCLK_ISP_SENSOR0 514
193#define CLK_SCLK_ISP_SENSOR1 515
194#define CLK_SCLK_ISP_SENSOR2 516
195#define CLK_ACLK432_SCALER 517
196#define CLK_ACLK432_CAM 518
197#define CLK_ACLK_FL1550_CAM 519
198#define CLK_ACLK550_CAM 520
199#define CLK_CLKM_PHY0 521
200#define CLK_CLKM_PHY1 522
201#define CLK_ACLK_PPMU_DREX0_0 523
202#define CLK_ACLK_PPMU_DREX0_1 524
203#define CLK_ACLK_PPMU_DREX1_0 525
204#define CLK_ACLK_PPMU_DREX1_1 526
205#define CLK_PCLK_PPMU_DREX0_0 527
206#define CLK_PCLK_PPMU_DREX0_1 528
207#define CLK_PCLK_PPMU_DREX1_0 529
208#define CLK_PCLK_PPMU_DREX1_1 530
209
210/* mux clocks */
211#define CLK_MOUT_HDMI 640
212#define CLK_MOUT_G3D 641
213#define CLK_MOUT_VPLL 642
214#define CLK_MOUT_MAUDIO0 643
215#define CLK_MOUT_USER_ACLK333 644
216#define CLK_MOUT_SW_ACLK333 645
217#define CLK_MOUT_USER_ACLK200_DISP1 646
218#define CLK_MOUT_SW_ACLK200 647
219#define CLK_MOUT_USER_ACLK300_DISP1 648
220#define CLK_MOUT_SW_ACLK300 649
221#define CLK_MOUT_USER_ACLK400_DISP1 650
222#define CLK_MOUT_SW_ACLK400 651
223#define CLK_MOUT_USER_ACLK300_GSCL 652
224#define CLK_MOUT_SW_ACLK300_GSCL 653
225#define CLK_MOUT_MCLK_CDREX 654
226#define CLK_MOUT_BPLL 655
227#define CLK_MOUT_MX_MSPLL_CCORE 656
228#define CLK_MOUT_EPLL 657
229#define CLK_MOUT_MAU_EPLL 658
230#define CLK_MOUT_USER_MAU_EPLL 659
231#define CLK_MOUT_SCLK_SPLL 660
232#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
233#define CLK_MOUT_SW_ACLK_G3D 662
234#define CLK_MOUT_APLL 663
235#define CLK_MOUT_MSPLL_CPU 664
236#define CLK_MOUT_KPLL 665
237#define CLK_MOUT_MSPLL_KFC 666
238
239
240/* divider clocks */
241#define CLK_DOUT_PIXEL 768
242#define CLK_DOUT_ACLK400_WCORE 769
243#define CLK_DOUT_ACLK400_ISP 770
244#define CLK_DOUT_ACLK400_MSCL 771
245#define CLK_DOUT_ACLK200 772
246#define CLK_DOUT_ACLK200_FSYS2 773
247#define CLK_DOUT_ACLK100_NOC 774
248#define CLK_DOUT_PCLK200_FSYS 775
249#define CLK_DOUT_ACLK200_FSYS 776
250#define CLK_DOUT_ACLK333_432_GSCL 777
251#define CLK_DOUT_ACLK333_432_ISP 778
252#define CLK_DOUT_ACLK66 779
253#define CLK_DOUT_ACLK333_432_ISP0 780
254#define CLK_DOUT_ACLK266 781
255#define CLK_DOUT_ACLK166 782
256#define CLK_DOUT_ACLK333 783
257#define CLK_DOUT_ACLK333_G2D 784
258#define CLK_DOUT_ACLK266_G2D 785
259#define CLK_DOUT_ACLK_G3D 786
260#define CLK_DOUT_ACLK300_JPEG 787
261#define CLK_DOUT_ACLK300_DISP1 788
262#define CLK_DOUT_ACLK300_GSCL 789
263#define CLK_DOUT_ACLK400_DISP1 790
264#define CLK_DOUT_PCLK_CDREX 791
265#define CLK_DOUT_SCLK_CDREX 792
266#define CLK_DOUT_ACLK_CDREX1 793
267#define CLK_DOUT_CCLK_DREX0 794
268#define CLK_DOUT_CLK2X_PHY0 795
269#define CLK_DOUT_PCLK_CORE_MEM 796
270#define CLK_FF_DOUT_SPLL2 797
271#define CLK_DOUT_PCLK_DREX0 798
272#define CLK_DOUT_PCLK_DREX1 799
273
274/* must be greater than maximal clock id */
275#define CLK_NR_CLKS 800
276
277#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */