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1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26#ifndef _I915_DRM_H_
27#define _I915_DRM_H_
28
29#include <linux/types.h>
30
31/* For use by IPS driver */
32unsigned long i915_read_mch_val(void);
33bool i915_gpu_raise(void);
34bool i915_gpu_lower(void);
35bool i915_gpu_busy(void);
36bool i915_gpu_turbo_disable(void);
37
38/* Exported from arch/x86/kernel/early-quirks.c */
39extern struct resource intel_graphics_stolen_res;
40
41/*
42 * The Bridge device's PCI config space has information about the
43 * fb aperture size and the amount of pre-reserved memory.
44 * This is all handled in the intel-gtt.ko module. i915.ko only
45 * cares about the vga bit for the vga rbiter.
46 */
47#define INTEL_GMCH_CTRL 0x52
48#define INTEL_GMCH_VGA_DISABLE (1 << 1)
49#define SNB_GMCH_CTRL 0x50
50#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */
51#define SNB_GMCH_GGMS_MASK 0x3
52#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
53#define SNB_GMCH_GMS_MASK 0x1f
54#define BDW_GMCH_GGMS_SHIFT 6
55#define BDW_GMCH_GGMS_MASK 0x3
56#define BDW_GMCH_GMS_SHIFT 8
57#define BDW_GMCH_GMS_MASK 0xff
58
59#define I830_GMCH_CTRL 0x52
60
61#define I830_GMCH_GMS_MASK 0x70
62#define I830_GMCH_GMS_LOCAL 0x10
63#define I830_GMCH_GMS_STOLEN_512 0x20
64#define I830_GMCH_GMS_STOLEN_1024 0x30
65#define I830_GMCH_GMS_STOLEN_8192 0x40
66
67#define I855_GMCH_GMS_MASK 0xF0
68#define I855_GMCH_GMS_STOLEN_0M 0x0
69#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
70#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
71#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
72#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
73#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
74#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
75#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
76#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
77#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
78#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
79#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
80#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
81#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
82
83#define I830_DRB3 0x63
84#define I85X_DRB3 0x43
85#define I865_TOUD 0xc4
86
87#define I830_ESMRAMC 0x91
88#define I845_ESMRAMC 0x9e
89#define I85X_ESMRAMC 0x61
90#define TSEG_ENABLE (1 << 0)
91#define I830_TSEG_SIZE_512K (0 << 1)
92#define I830_TSEG_SIZE_1M (1 << 1)
93#define I845_TSEG_SIZE_MASK (3 << 1)
94#define I845_TSEG_SIZE_512K (2 << 1)
95#define I845_TSEG_SIZE_1M (3 << 1)
96
97#define INTEL_BSM 0x5c
98#define INTEL_GEN11_BSM_DW0 0xc0
99#define INTEL_GEN11_BSM_DW1 0xc4
100#define INTEL_BSM_MASK (-(1u << 20))
101
102#endif /* _I915_DRM_H_ */
1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30#include "drm.h"
31
32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
35
36#ifdef __KERNEL__
37/* For use by IPS driver */
38extern unsigned long i915_read_mch_val(void);
39extern bool i915_gpu_raise(void);
40extern bool i915_gpu_lower(void);
41extern bool i915_gpu_busy(void);
42extern bool i915_gpu_turbo_disable(void);
43#endif
44
45/* Each region is a minimum of 16k, and there are at most 255 of them.
46 */
47#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
48 * of chars for next/prev indices */
49#define I915_LOG_MIN_TEX_REGION_SIZE 14
50
51typedef struct _drm_i915_init {
52 enum {
53 I915_INIT_DMA = 0x01,
54 I915_CLEANUP_DMA = 0x02,
55 I915_RESUME_DMA = 0x03
56 } func;
57 unsigned int mmio_offset;
58 int sarea_priv_offset;
59 unsigned int ring_start;
60 unsigned int ring_end;
61 unsigned int ring_size;
62 unsigned int front_offset;
63 unsigned int back_offset;
64 unsigned int depth_offset;
65 unsigned int w;
66 unsigned int h;
67 unsigned int pitch;
68 unsigned int pitch_bits;
69 unsigned int back_pitch;
70 unsigned int depth_pitch;
71 unsigned int cpp;
72 unsigned int chipset;
73} drm_i915_init_t;
74
75typedef struct _drm_i915_sarea {
76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
77 int last_upload; /* last time texture was uploaded */
78 int last_enqueue; /* last time a buffer was enqueued */
79 int last_dispatch; /* age of the most recently dispatched buffer */
80 int ctxOwner; /* last context to upload state */
81 int texAge;
82 int pf_enabled; /* is pageflipping allowed? */
83 int pf_active;
84 int pf_current_page; /* which buffer is being displayed? */
85 int perf_boxes; /* performance boxes to be displayed */
86 int width, height; /* screen size in pixels */
87
88 drm_handle_t front_handle;
89 int front_offset;
90 int front_size;
91
92 drm_handle_t back_handle;
93 int back_offset;
94 int back_size;
95
96 drm_handle_t depth_handle;
97 int depth_offset;
98 int depth_size;
99
100 drm_handle_t tex_handle;
101 int tex_offset;
102 int tex_size;
103 int log_tex_granularity;
104 int pitch;
105 int rotation; /* 0, 90, 180 or 270 */
106 int rotated_offset;
107 int rotated_size;
108 int rotated_pitch;
109 int virtualX, virtualY;
110
111 unsigned int front_tiled;
112 unsigned int back_tiled;
113 unsigned int depth_tiled;
114 unsigned int rotated_tiled;
115 unsigned int rotated2_tiled;
116
117 int pipeA_x;
118 int pipeA_y;
119 int pipeA_w;
120 int pipeA_h;
121 int pipeB_x;
122 int pipeB_y;
123 int pipeB_w;
124 int pipeB_h;
125
126 /* fill out some space for old userspace triple buffer */
127 drm_handle_t unused_handle;
128 __u32 unused1, unused2, unused3;
129
130 /* buffer object handles for static buffers. May change
131 * over the lifetime of the client.
132 */
133 __u32 front_bo_handle;
134 __u32 back_bo_handle;
135 __u32 unused_bo_handle;
136 __u32 depth_bo_handle;
137
138} drm_i915_sarea_t;
139
140/* due to userspace building against these headers we need some compat here */
141#define planeA_x pipeA_x
142#define planeA_y pipeA_y
143#define planeA_w pipeA_w
144#define planeA_h pipeA_h
145#define planeB_x pipeB_x
146#define planeB_y pipeB_y
147#define planeB_w pipeB_w
148#define planeB_h pipeB_h
149
150/* Flags for perf_boxes
151 */
152#define I915_BOX_RING_EMPTY 0x1
153#define I915_BOX_FLIP 0x2
154#define I915_BOX_WAIT 0x4
155#define I915_BOX_TEXTURE_LOAD 0x8
156#define I915_BOX_LOST_CONTEXT 0x10
157
158/* I915 specific ioctls
159 * The device specific ioctl range is 0x40 to 0x79.
160 */
161#define DRM_I915_INIT 0x00
162#define DRM_I915_FLUSH 0x01
163#define DRM_I915_FLIP 0x02
164#define DRM_I915_BATCHBUFFER 0x03
165#define DRM_I915_IRQ_EMIT 0x04
166#define DRM_I915_IRQ_WAIT 0x05
167#define DRM_I915_GETPARAM 0x06
168#define DRM_I915_SETPARAM 0x07
169#define DRM_I915_ALLOC 0x08
170#define DRM_I915_FREE 0x09
171#define DRM_I915_INIT_HEAP 0x0a
172#define DRM_I915_CMDBUFFER 0x0b
173#define DRM_I915_DESTROY_HEAP 0x0c
174#define DRM_I915_SET_VBLANK_PIPE 0x0d
175#define DRM_I915_GET_VBLANK_PIPE 0x0e
176#define DRM_I915_VBLANK_SWAP 0x0f
177#define DRM_I915_HWS_ADDR 0x11
178#define DRM_I915_GEM_INIT 0x13
179#define DRM_I915_GEM_EXECBUFFER 0x14
180#define DRM_I915_GEM_PIN 0x15
181#define DRM_I915_GEM_UNPIN 0x16
182#define DRM_I915_GEM_BUSY 0x17
183#define DRM_I915_GEM_THROTTLE 0x18
184#define DRM_I915_GEM_ENTERVT 0x19
185#define DRM_I915_GEM_LEAVEVT 0x1a
186#define DRM_I915_GEM_CREATE 0x1b
187#define DRM_I915_GEM_PREAD 0x1c
188#define DRM_I915_GEM_PWRITE 0x1d
189#define DRM_I915_GEM_MMAP 0x1e
190#define DRM_I915_GEM_SET_DOMAIN 0x1f
191#define DRM_I915_GEM_SW_FINISH 0x20
192#define DRM_I915_GEM_SET_TILING 0x21
193#define DRM_I915_GEM_GET_TILING 0x22
194#define DRM_I915_GEM_GET_APERTURE 0x23
195#define DRM_I915_GEM_MMAP_GTT 0x24
196#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
197#define DRM_I915_GEM_MADVISE 0x26
198#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
199#define DRM_I915_OVERLAY_ATTRS 0x28
200#define DRM_I915_GEM_EXECBUFFER2 0x29
201#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
202#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
203
204#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
205#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
206#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
207#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
208#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
209#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
210#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
211#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
212#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
213#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
214#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
215#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
216#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
217#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
218#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
219#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
220#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
221#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
222#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
223#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
224#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
225#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
226#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
227#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
228#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
229#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
230#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
231#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
232#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
233#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
234#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
235#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
236#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
237#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
238#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
239#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
240#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
241#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
242#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
243#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
244#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
245#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
246
247/* Allow drivers to submit batchbuffers directly to hardware, relying
248 * on the security mechanisms provided by hardware.
249 */
250typedef struct drm_i915_batchbuffer {
251 int start; /* agp offset */
252 int used; /* nr bytes in use */
253 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
254 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
255 int num_cliprects; /* mulitpass with multiple cliprects? */
256 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
257} drm_i915_batchbuffer_t;
258
259/* As above, but pass a pointer to userspace buffer which can be
260 * validated by the kernel prior to sending to hardware.
261 */
262typedef struct _drm_i915_cmdbuffer {
263 char __user *buf; /* pointer to userspace command buffer */
264 int sz; /* nr bytes in buf */
265 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
266 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
267 int num_cliprects; /* mulitpass with multiple cliprects? */
268 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
269} drm_i915_cmdbuffer_t;
270
271/* Userspace can request & wait on irq's:
272 */
273typedef struct drm_i915_irq_emit {
274 int __user *irq_seq;
275} drm_i915_irq_emit_t;
276
277typedef struct drm_i915_irq_wait {
278 int irq_seq;
279} drm_i915_irq_wait_t;
280
281/* Ioctl to query kernel params:
282 */
283#define I915_PARAM_IRQ_ACTIVE 1
284#define I915_PARAM_ALLOW_BATCHBUFFER 2
285#define I915_PARAM_LAST_DISPATCH 3
286#define I915_PARAM_CHIPSET_ID 4
287#define I915_PARAM_HAS_GEM 5
288#define I915_PARAM_NUM_FENCES_AVAIL 6
289#define I915_PARAM_HAS_OVERLAY 7
290#define I915_PARAM_HAS_PAGEFLIPPING 8
291#define I915_PARAM_HAS_EXECBUF2 9
292#define I915_PARAM_HAS_BSD 10
293#define I915_PARAM_HAS_BLT 11
294#define I915_PARAM_HAS_RELAXED_FENCING 12
295#define I915_PARAM_HAS_COHERENT_RINGS 13
296#define I915_PARAM_HAS_EXEC_CONSTANTS 14
297#define I915_PARAM_HAS_RELAXED_DELTA 15
298#define I915_PARAM_HAS_GEN7_SOL_RESET 16
299#define I915_PARAM_HAS_LLC 17
300#define I915_PARAM_HAS_ALIASING_PPGTT 18
301
302typedef struct drm_i915_getparam {
303 int param;
304 int __user *value;
305} drm_i915_getparam_t;
306
307/* Ioctl to set kernel params:
308 */
309#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
310#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
311#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
312#define I915_SETPARAM_NUM_USED_FENCES 4
313
314typedef struct drm_i915_setparam {
315 int param;
316 int value;
317} drm_i915_setparam_t;
318
319/* A memory manager for regions of shared memory:
320 */
321#define I915_MEM_REGION_AGP 1
322
323typedef struct drm_i915_mem_alloc {
324 int region;
325 int alignment;
326 int size;
327 int __user *region_offset; /* offset from start of fb or agp */
328} drm_i915_mem_alloc_t;
329
330typedef struct drm_i915_mem_free {
331 int region;
332 int region_offset;
333} drm_i915_mem_free_t;
334
335typedef struct drm_i915_mem_init_heap {
336 int region;
337 int size;
338 int start;
339} drm_i915_mem_init_heap_t;
340
341/* Allow memory manager to be torn down and re-initialized (eg on
342 * rotate):
343 */
344typedef struct drm_i915_mem_destroy_heap {
345 int region;
346} drm_i915_mem_destroy_heap_t;
347
348/* Allow X server to configure which pipes to monitor for vblank signals
349 */
350#define DRM_I915_VBLANK_PIPE_A 1
351#define DRM_I915_VBLANK_PIPE_B 2
352
353typedef struct drm_i915_vblank_pipe {
354 int pipe;
355} drm_i915_vblank_pipe_t;
356
357/* Schedule buffer swap at given vertical blank:
358 */
359typedef struct drm_i915_vblank_swap {
360 drm_drawable_t drawable;
361 enum drm_vblank_seq_type seqtype;
362 unsigned int sequence;
363} drm_i915_vblank_swap_t;
364
365typedef struct drm_i915_hws_addr {
366 __u64 addr;
367} drm_i915_hws_addr_t;
368
369struct drm_i915_gem_init {
370 /**
371 * Beginning offset in the GTT to be managed by the DRM memory
372 * manager.
373 */
374 __u64 gtt_start;
375 /**
376 * Ending offset in the GTT to be managed by the DRM memory
377 * manager.
378 */
379 __u64 gtt_end;
380};
381
382struct drm_i915_gem_create {
383 /**
384 * Requested size for the object.
385 *
386 * The (page-aligned) allocated size for the object will be returned.
387 */
388 __u64 size;
389 /**
390 * Returned handle for the object.
391 *
392 * Object handles are nonzero.
393 */
394 __u32 handle;
395 __u32 pad;
396};
397
398struct drm_i915_gem_pread {
399 /** Handle for the object being read. */
400 __u32 handle;
401 __u32 pad;
402 /** Offset into the object to read from */
403 __u64 offset;
404 /** Length of data to read */
405 __u64 size;
406 /**
407 * Pointer to write the data into.
408 *
409 * This is a fixed-size type for 32/64 compatibility.
410 */
411 __u64 data_ptr;
412};
413
414struct drm_i915_gem_pwrite {
415 /** Handle for the object being written to. */
416 __u32 handle;
417 __u32 pad;
418 /** Offset into the object to write to */
419 __u64 offset;
420 /** Length of data to write */
421 __u64 size;
422 /**
423 * Pointer to read the data from.
424 *
425 * This is a fixed-size type for 32/64 compatibility.
426 */
427 __u64 data_ptr;
428};
429
430struct drm_i915_gem_mmap {
431 /** Handle for the object being mapped. */
432 __u32 handle;
433 __u32 pad;
434 /** Offset in the object to map. */
435 __u64 offset;
436 /**
437 * Length of data to map.
438 *
439 * The value will be page-aligned.
440 */
441 __u64 size;
442 /**
443 * Returned pointer the data was mapped at.
444 *
445 * This is a fixed-size type for 32/64 compatibility.
446 */
447 __u64 addr_ptr;
448};
449
450struct drm_i915_gem_mmap_gtt {
451 /** Handle for the object being mapped. */
452 __u32 handle;
453 __u32 pad;
454 /**
455 * Fake offset to use for subsequent mmap call
456 *
457 * This is a fixed-size type for 32/64 compatibility.
458 */
459 __u64 offset;
460};
461
462struct drm_i915_gem_set_domain {
463 /** Handle for the object */
464 __u32 handle;
465
466 /** New read domains */
467 __u32 read_domains;
468
469 /** New write domain */
470 __u32 write_domain;
471};
472
473struct drm_i915_gem_sw_finish {
474 /** Handle for the object */
475 __u32 handle;
476};
477
478struct drm_i915_gem_relocation_entry {
479 /**
480 * Handle of the buffer being pointed to by this relocation entry.
481 *
482 * It's appealing to make this be an index into the mm_validate_entry
483 * list to refer to the buffer, but this allows the driver to create
484 * a relocation list for state buffers and not re-write it per
485 * exec using the buffer.
486 */
487 __u32 target_handle;
488
489 /**
490 * Value to be added to the offset of the target buffer to make up
491 * the relocation entry.
492 */
493 __u32 delta;
494
495 /** Offset in the buffer the relocation entry will be written into */
496 __u64 offset;
497
498 /**
499 * Offset value of the target buffer that the relocation entry was last
500 * written as.
501 *
502 * If the buffer has the same offset as last time, we can skip syncing
503 * and writing the relocation. This value is written back out by
504 * the execbuffer ioctl when the relocation is written.
505 */
506 __u64 presumed_offset;
507
508 /**
509 * Target memory domains read by this operation.
510 */
511 __u32 read_domains;
512
513 /**
514 * Target memory domains written by this operation.
515 *
516 * Note that only one domain may be written by the whole
517 * execbuffer operation, so that where there are conflicts,
518 * the application will get -EINVAL back.
519 */
520 __u32 write_domain;
521};
522
523/** @{
524 * Intel memory domains
525 *
526 * Most of these just align with the various caches in
527 * the system and are used to flush and invalidate as
528 * objects end up cached in different domains.
529 */
530/** CPU cache */
531#define I915_GEM_DOMAIN_CPU 0x00000001
532/** Render cache, used by 2D and 3D drawing */
533#define I915_GEM_DOMAIN_RENDER 0x00000002
534/** Sampler cache, used by texture engine */
535#define I915_GEM_DOMAIN_SAMPLER 0x00000004
536/** Command queue, used to load batch buffers */
537#define I915_GEM_DOMAIN_COMMAND 0x00000008
538/** Instruction cache, used by shader programs */
539#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
540/** Vertex address cache */
541#define I915_GEM_DOMAIN_VERTEX 0x00000020
542/** GTT domain - aperture and scanout */
543#define I915_GEM_DOMAIN_GTT 0x00000040
544/** @} */
545
546struct drm_i915_gem_exec_object {
547 /**
548 * User's handle for a buffer to be bound into the GTT for this
549 * operation.
550 */
551 __u32 handle;
552
553 /** Number of relocations to be performed on this buffer */
554 __u32 relocation_count;
555 /**
556 * Pointer to array of struct drm_i915_gem_relocation_entry containing
557 * the relocations to be performed in this buffer.
558 */
559 __u64 relocs_ptr;
560
561 /** Required alignment in graphics aperture */
562 __u64 alignment;
563
564 /**
565 * Returned value of the updated offset of the object, for future
566 * presumed_offset writes.
567 */
568 __u64 offset;
569};
570
571struct drm_i915_gem_execbuffer {
572 /**
573 * List of buffers to be validated with their relocations to be
574 * performend on them.
575 *
576 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
577 *
578 * These buffers must be listed in an order such that all relocations
579 * a buffer is performing refer to buffers that have already appeared
580 * in the validate list.
581 */
582 __u64 buffers_ptr;
583 __u32 buffer_count;
584
585 /** Offset in the batchbuffer to start execution from. */
586 __u32 batch_start_offset;
587 /** Bytes used in batchbuffer from batch_start_offset */
588 __u32 batch_len;
589 __u32 DR1;
590 __u32 DR4;
591 __u32 num_cliprects;
592 /** This is a struct drm_clip_rect *cliprects */
593 __u64 cliprects_ptr;
594};
595
596struct drm_i915_gem_exec_object2 {
597 /**
598 * User's handle for a buffer to be bound into the GTT for this
599 * operation.
600 */
601 __u32 handle;
602
603 /** Number of relocations to be performed on this buffer */
604 __u32 relocation_count;
605 /**
606 * Pointer to array of struct drm_i915_gem_relocation_entry containing
607 * the relocations to be performed in this buffer.
608 */
609 __u64 relocs_ptr;
610
611 /** Required alignment in graphics aperture */
612 __u64 alignment;
613
614 /**
615 * Returned value of the updated offset of the object, for future
616 * presumed_offset writes.
617 */
618 __u64 offset;
619
620#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
621 __u64 flags;
622 __u64 rsvd1;
623 __u64 rsvd2;
624};
625
626struct drm_i915_gem_execbuffer2 {
627 /**
628 * List of gem_exec_object2 structs
629 */
630 __u64 buffers_ptr;
631 __u32 buffer_count;
632
633 /** Offset in the batchbuffer to start execution from. */
634 __u32 batch_start_offset;
635 /** Bytes used in batchbuffer from batch_start_offset */
636 __u32 batch_len;
637 __u32 DR1;
638 __u32 DR4;
639 __u32 num_cliprects;
640 /** This is a struct drm_clip_rect *cliprects */
641 __u64 cliprects_ptr;
642#define I915_EXEC_RING_MASK (7<<0)
643#define I915_EXEC_DEFAULT (0<<0)
644#define I915_EXEC_RENDER (1<<0)
645#define I915_EXEC_BSD (2<<0)
646#define I915_EXEC_BLT (3<<0)
647
648/* Used for switching the constants addressing mode on gen4+ RENDER ring.
649 * Gen6+ only supports relative addressing to dynamic state (default) and
650 * absolute addressing.
651 *
652 * These flags are ignored for the BSD and BLT rings.
653 */
654#define I915_EXEC_CONSTANTS_MASK (3<<6)
655#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
656#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
657#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
658 __u64 flags;
659 __u64 rsvd1;
660 __u64 rsvd2;
661};
662
663/** Resets the SO write offset registers for transform feedback on gen7. */
664#define I915_EXEC_GEN7_SOL_RESET (1<<8)
665
666struct drm_i915_gem_pin {
667 /** Handle of the buffer to be pinned. */
668 __u32 handle;
669 __u32 pad;
670
671 /** alignment required within the aperture */
672 __u64 alignment;
673
674 /** Returned GTT offset of the buffer. */
675 __u64 offset;
676};
677
678struct drm_i915_gem_unpin {
679 /** Handle of the buffer to be unpinned. */
680 __u32 handle;
681 __u32 pad;
682};
683
684struct drm_i915_gem_busy {
685 /** Handle of the buffer to check for busy */
686 __u32 handle;
687
688 /** Return busy status (1 if busy, 0 if idle) */
689 __u32 busy;
690};
691
692#define I915_TILING_NONE 0
693#define I915_TILING_X 1
694#define I915_TILING_Y 2
695
696#define I915_BIT_6_SWIZZLE_NONE 0
697#define I915_BIT_6_SWIZZLE_9 1
698#define I915_BIT_6_SWIZZLE_9_10 2
699#define I915_BIT_6_SWIZZLE_9_11 3
700#define I915_BIT_6_SWIZZLE_9_10_11 4
701/* Not seen by userland */
702#define I915_BIT_6_SWIZZLE_UNKNOWN 5
703/* Seen by userland. */
704#define I915_BIT_6_SWIZZLE_9_17 6
705#define I915_BIT_6_SWIZZLE_9_10_17 7
706
707struct drm_i915_gem_set_tiling {
708 /** Handle of the buffer to have its tiling state updated */
709 __u32 handle;
710
711 /**
712 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
713 * I915_TILING_Y).
714 *
715 * This value is to be set on request, and will be updated by the
716 * kernel on successful return with the actual chosen tiling layout.
717 *
718 * The tiling mode may be demoted to I915_TILING_NONE when the system
719 * has bit 6 swizzling that can't be managed correctly by GEM.
720 *
721 * Buffer contents become undefined when changing tiling_mode.
722 */
723 __u32 tiling_mode;
724
725 /**
726 * Stride in bytes for the object when in I915_TILING_X or
727 * I915_TILING_Y.
728 */
729 __u32 stride;
730
731 /**
732 * Returned address bit 6 swizzling required for CPU access through
733 * mmap mapping.
734 */
735 __u32 swizzle_mode;
736};
737
738struct drm_i915_gem_get_tiling {
739 /** Handle of the buffer to get tiling state for. */
740 __u32 handle;
741
742 /**
743 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
744 * I915_TILING_Y).
745 */
746 __u32 tiling_mode;
747
748 /**
749 * Returned address bit 6 swizzling required for CPU access through
750 * mmap mapping.
751 */
752 __u32 swizzle_mode;
753};
754
755struct drm_i915_gem_get_aperture {
756 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
757 __u64 aper_size;
758
759 /**
760 * Available space in the aperture used by i915_gem_execbuffer, in
761 * bytes
762 */
763 __u64 aper_available_size;
764};
765
766struct drm_i915_get_pipe_from_crtc_id {
767 /** ID of CRTC being requested **/
768 __u32 crtc_id;
769
770 /** pipe of requested CRTC **/
771 __u32 pipe;
772};
773
774#define I915_MADV_WILLNEED 0
775#define I915_MADV_DONTNEED 1
776#define __I915_MADV_PURGED 2 /* internal state */
777
778struct drm_i915_gem_madvise {
779 /** Handle of the buffer to change the backing store advice */
780 __u32 handle;
781
782 /* Advice: either the buffer will be needed again in the near future,
783 * or wont be and could be discarded under memory pressure.
784 */
785 __u32 madv;
786
787 /** Whether the backing store still exists. */
788 __u32 retained;
789};
790
791/* flags */
792#define I915_OVERLAY_TYPE_MASK 0xff
793#define I915_OVERLAY_YUV_PLANAR 0x01
794#define I915_OVERLAY_YUV_PACKED 0x02
795#define I915_OVERLAY_RGB 0x03
796
797#define I915_OVERLAY_DEPTH_MASK 0xff00
798#define I915_OVERLAY_RGB24 0x1000
799#define I915_OVERLAY_RGB16 0x2000
800#define I915_OVERLAY_RGB15 0x3000
801#define I915_OVERLAY_YUV422 0x0100
802#define I915_OVERLAY_YUV411 0x0200
803#define I915_OVERLAY_YUV420 0x0300
804#define I915_OVERLAY_YUV410 0x0400
805
806#define I915_OVERLAY_SWAP_MASK 0xff0000
807#define I915_OVERLAY_NO_SWAP 0x000000
808#define I915_OVERLAY_UV_SWAP 0x010000
809#define I915_OVERLAY_Y_SWAP 0x020000
810#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
811
812#define I915_OVERLAY_FLAGS_MASK 0xff000000
813#define I915_OVERLAY_ENABLE 0x01000000
814
815struct drm_intel_overlay_put_image {
816 /* various flags and src format description */
817 __u32 flags;
818 /* source picture description */
819 __u32 bo_handle;
820 /* stride values and offsets are in bytes, buffer relative */
821 __u16 stride_Y; /* stride for packed formats */
822 __u16 stride_UV;
823 __u32 offset_Y; /* offset for packet formats */
824 __u32 offset_U;
825 __u32 offset_V;
826 /* in pixels */
827 __u16 src_width;
828 __u16 src_height;
829 /* to compensate the scaling factors for partially covered surfaces */
830 __u16 src_scan_width;
831 __u16 src_scan_height;
832 /* output crtc description */
833 __u32 crtc_id;
834 __u16 dst_x;
835 __u16 dst_y;
836 __u16 dst_width;
837 __u16 dst_height;
838};
839
840/* flags */
841#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
842#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
843struct drm_intel_overlay_attrs {
844 __u32 flags;
845 __u32 color_key;
846 __s32 brightness;
847 __u32 contrast;
848 __u32 saturation;
849 __u32 gamma0;
850 __u32 gamma1;
851 __u32 gamma2;
852 __u32 gamma3;
853 __u32 gamma4;
854 __u32 gamma5;
855};
856
857/*
858 * Intel sprite handling
859 *
860 * Color keying works with a min/mask/max tuple. Both source and destination
861 * color keying is allowed.
862 *
863 * Source keying:
864 * Sprite pixels within the min & max values, masked against the color channels
865 * specified in the mask field, will be transparent. All other pixels will
866 * be displayed on top of the primary plane. For RGB surfaces, only the min
867 * and mask fields will be used; ranged compares are not allowed.
868 *
869 * Destination keying:
870 * Primary plane pixels that match the min value, masked against the color
871 * channels specified in the mask field, will be replaced by corresponding
872 * pixels from the sprite plane.
873 *
874 * Note that source & destination keying are exclusive; only one can be
875 * active on a given plane.
876 */
877
878#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
879#define I915_SET_COLORKEY_DESTINATION (1<<1)
880#define I915_SET_COLORKEY_SOURCE (1<<2)
881struct drm_intel_sprite_colorkey {
882 __u32 plane_id;
883 __u32 min_value;
884 __u32 channel_mask;
885 __u32 max_value;
886 __u32 flags;
887};
888
889#endif /* _I915_DRM_H_ */