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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for CLPS711x serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 */
10
11#include <linux/module.h>
12#include <linux/device.h>
13#include <linux/console.h>
14#include <linux/serial_core.h>
15#include <linux/serial.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/ioport.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/regmap.h>
24
25#include <linux/mfd/syscon.h>
26#include <linux/mfd/syscon/clps711x.h>
27
28#include "serial_mctrl_gpio.h"
29
30#define UART_CLPS711X_DEVNAME "ttyCL"
31#define UART_CLPS711X_NR 2
32#define UART_CLPS711X_MAJOR 204
33#define UART_CLPS711X_MINOR 40
34
35#define UARTDR_OFFSET (0x00)
36#define UBRLCR_OFFSET (0x40)
37
38#define UARTDR_FRMERR (1 << 8)
39#define UARTDR_PARERR (1 << 9)
40#define UARTDR_OVERR (1 << 10)
41
42#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
43#define UBRLCR_BREAK (1 << 12)
44#define UBRLCR_PRTEN (1 << 13)
45#define UBRLCR_EVENPRT (1 << 14)
46#define UBRLCR_XSTOP (1 << 15)
47#define UBRLCR_FIFOEN (1 << 16)
48#define UBRLCR_WRDLEN5 (0 << 17)
49#define UBRLCR_WRDLEN6 (1 << 17)
50#define UBRLCR_WRDLEN7 (2 << 17)
51#define UBRLCR_WRDLEN8 (3 << 17)
52#define UBRLCR_WRDLEN_MASK (3 << 17)
53
54struct clps711x_port {
55 struct uart_port port;
56 unsigned int tx_enabled;
57 int rx_irq;
58 struct regmap *syscon;
59 struct mctrl_gpios *gpios;
60};
61
62static struct uart_driver clps711x_uart = {
63 .owner = THIS_MODULE,
64 .driver_name = UART_CLPS711X_DEVNAME,
65 .dev_name = UART_CLPS711X_DEVNAME,
66 .major = UART_CLPS711X_MAJOR,
67 .minor = UART_CLPS711X_MINOR,
68 .nr = UART_CLPS711X_NR,
69};
70
71static void uart_clps711x_stop_tx(struct uart_port *port)
72{
73 struct clps711x_port *s = dev_get_drvdata(port->dev);
74
75 if (s->tx_enabled) {
76 disable_irq(port->irq);
77 s->tx_enabled = 0;
78 }
79}
80
81static void uart_clps711x_start_tx(struct uart_port *port)
82{
83 struct clps711x_port *s = dev_get_drvdata(port->dev);
84
85 if (!s->tx_enabled) {
86 s->tx_enabled = 1;
87 enable_irq(port->irq);
88 }
89}
90
91static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
92{
93 struct uart_port *port = dev_id;
94 struct clps711x_port *s = dev_get_drvdata(port->dev);
95 unsigned int status, flg;
96 u16 ch;
97
98 for (;;) {
99 u32 sysflg = 0;
100
101 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
102 if (sysflg & SYSFLG_URXFE)
103 break;
104
105 ch = readw(port->membase + UARTDR_OFFSET);
106 status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
107 ch &= 0xff;
108
109 port->icount.rx++;
110 flg = TTY_NORMAL;
111
112 if (unlikely(status)) {
113 if (status & UARTDR_PARERR)
114 port->icount.parity++;
115 else if (status & UARTDR_FRMERR)
116 port->icount.frame++;
117 else if (status & UARTDR_OVERR)
118 port->icount.overrun++;
119
120 status &= port->read_status_mask;
121
122 if (status & UARTDR_PARERR)
123 flg = TTY_PARITY;
124 else if (status & UARTDR_FRMERR)
125 flg = TTY_FRAME;
126 else if (status & UARTDR_OVERR)
127 flg = TTY_OVERRUN;
128 }
129
130 if (uart_handle_sysrq_char(port, ch))
131 continue;
132
133 if (status & port->ignore_status_mask)
134 continue;
135
136 uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
137 }
138
139 tty_flip_buffer_push(&port->state->port);
140
141 return IRQ_HANDLED;
142}
143
144static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id)
145{
146 struct uart_port *port = dev_id;
147 struct clps711x_port *s = dev_get_drvdata(port->dev);
148 struct circ_buf *xmit = &port->state->xmit;
149
150 if (port->x_char) {
151 writew(port->x_char, port->membase + UARTDR_OFFSET);
152 port->icount.tx++;
153 port->x_char = 0;
154 return IRQ_HANDLED;
155 }
156
157 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
158 if (s->tx_enabled) {
159 disable_irq_nosync(port->irq);
160 s->tx_enabled = 0;
161 }
162 return IRQ_HANDLED;
163 }
164
165 while (!uart_circ_empty(xmit)) {
166 u32 sysflg = 0;
167
168 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET);
169 uart_xmit_advance(port, 1);
170
171 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
172 if (sysflg & SYSFLG_UTXFF)
173 break;
174 }
175
176 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
177 uart_write_wakeup(port);
178
179 return IRQ_HANDLED;
180}
181
182static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
183{
184 struct clps711x_port *s = dev_get_drvdata(port->dev);
185 u32 sysflg = 0;
186
187 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
188
189 return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT;
190}
191
192static unsigned int uart_clps711x_get_mctrl(struct uart_port *port)
193{
194 unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
195 struct clps711x_port *s = dev_get_drvdata(port->dev);
196
197 return mctrl_gpio_get(s->gpios, &result);
198}
199
200static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl)
201{
202 struct clps711x_port *s = dev_get_drvdata(port->dev);
203
204 mctrl_gpio_set(s->gpios, mctrl);
205}
206
207static void uart_clps711x_break_ctl(struct uart_port *port, int break_state)
208{
209 unsigned int ubrlcr;
210
211 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
212 if (break_state)
213 ubrlcr |= UBRLCR_BREAK;
214 else
215 ubrlcr &= ~UBRLCR_BREAK;
216 writel(ubrlcr, port->membase + UBRLCR_OFFSET);
217}
218
219static void uart_clps711x_set_ldisc(struct uart_port *port,
220 struct ktermios *termios)
221{
222 if (!port->line) {
223 struct clps711x_port *s = dev_get_drvdata(port->dev);
224
225 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN,
226 (termios->c_line == N_IRDA) ? SYSCON1_SIREN : 0);
227 }
228}
229
230static int uart_clps711x_startup(struct uart_port *port)
231{
232 struct clps711x_port *s = dev_get_drvdata(port->dev);
233
234 /* Disable break */
235 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
236 port->membase + UBRLCR_OFFSET);
237
238 /* Enable the port */
239 return regmap_update_bits(s->syscon, SYSCON_OFFSET,
240 SYSCON_UARTEN, SYSCON_UARTEN);
241}
242
243static void uart_clps711x_shutdown(struct uart_port *port)
244{
245 struct clps711x_port *s = dev_get_drvdata(port->dev);
246
247 /* Disable the port */
248 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
249}
250
251static void uart_clps711x_set_termios(struct uart_port *port,
252 struct ktermios *termios,
253 const struct ktermios *old)
254{
255 u32 ubrlcr;
256 unsigned int baud, quot;
257
258 /* Mask termios capabilities we don't support */
259 termios->c_cflag &= ~CMSPAR;
260 termios->c_iflag &= ~(BRKINT | IGNBRK);
261
262 /* Ask the core to calculate the divisor for us */
263 baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096,
264 port->uartclk / 16);
265 quot = uart_get_divisor(port, baud);
266
267 switch (termios->c_cflag & CSIZE) {
268 case CS5:
269 ubrlcr = UBRLCR_WRDLEN5;
270 break;
271 case CS6:
272 ubrlcr = UBRLCR_WRDLEN6;
273 break;
274 case CS7:
275 ubrlcr = UBRLCR_WRDLEN7;
276 break;
277 case CS8:
278 default:
279 ubrlcr = UBRLCR_WRDLEN8;
280 break;
281 }
282
283 if (termios->c_cflag & CSTOPB)
284 ubrlcr |= UBRLCR_XSTOP;
285
286 if (termios->c_cflag & PARENB) {
287 ubrlcr |= UBRLCR_PRTEN;
288 if (!(termios->c_cflag & PARODD))
289 ubrlcr |= UBRLCR_EVENPRT;
290 }
291
292 /* Enable FIFO */
293 ubrlcr |= UBRLCR_FIFOEN;
294
295 /* Set read status mask */
296 port->read_status_mask = UARTDR_OVERR;
297 if (termios->c_iflag & INPCK)
298 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
299
300 /* Set status ignore mask */
301 port->ignore_status_mask = 0;
302 if (!(termios->c_cflag & CREAD))
303 port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR |
304 UARTDR_FRMERR;
305
306 uart_update_timeout(port, termios->c_cflag, baud);
307
308 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
309}
310
311static const char *uart_clps711x_type(struct uart_port *port)
312{
313 return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL;
314}
315
316static void uart_clps711x_config_port(struct uart_port *port, int flags)
317{
318 if (flags & UART_CONFIG_TYPE)
319 port->type = PORT_CLPS711X;
320}
321
322static void uart_clps711x_nop_void(struct uart_port *port)
323{
324}
325
326static int uart_clps711x_nop_int(struct uart_port *port)
327{
328 return 0;
329}
330
331static const struct uart_ops uart_clps711x_ops = {
332 .tx_empty = uart_clps711x_tx_empty,
333 .set_mctrl = uart_clps711x_set_mctrl,
334 .get_mctrl = uart_clps711x_get_mctrl,
335 .stop_tx = uart_clps711x_stop_tx,
336 .start_tx = uart_clps711x_start_tx,
337 .stop_rx = uart_clps711x_nop_void,
338 .break_ctl = uart_clps711x_break_ctl,
339 .set_ldisc = uart_clps711x_set_ldisc,
340 .startup = uart_clps711x_startup,
341 .shutdown = uart_clps711x_shutdown,
342 .set_termios = uart_clps711x_set_termios,
343 .type = uart_clps711x_type,
344 .config_port = uart_clps711x_config_port,
345 .release_port = uart_clps711x_nop_void,
346 .request_port = uart_clps711x_nop_int,
347};
348
349#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
350static void uart_clps711x_console_putchar(struct uart_port *port, unsigned char ch)
351{
352 struct clps711x_port *s = dev_get_drvdata(port->dev);
353 u32 sysflg = 0;
354
355 /* Wait for FIFO is not full */
356 do {
357 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
358 } while (sysflg & SYSFLG_UTXFF);
359
360 writew(ch, port->membase + UARTDR_OFFSET);
361}
362
363static void uart_clps711x_console_write(struct console *co, const char *c,
364 unsigned n)
365{
366 struct uart_port *port = clps711x_uart.state[co->index].uart_port;
367 struct clps711x_port *s = dev_get_drvdata(port->dev);
368 u32 sysflg = 0;
369
370 uart_console_write(port, c, n, uart_clps711x_console_putchar);
371
372 /* Wait for transmitter to become empty */
373 do {
374 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
375 } while (sysflg & SYSFLG_UBUSY);
376}
377
378static int uart_clps711x_console_setup(struct console *co, char *options)
379{
380 int baud = 38400, bits = 8, parity = 'n', flow = 'n';
381 int ret, index = co->index;
382 struct clps711x_port *s;
383 struct uart_port *port;
384 unsigned int quot;
385 u32 ubrlcr;
386
387 if (index < 0 || index >= UART_CLPS711X_NR)
388 return -EINVAL;
389
390 port = clps711x_uart.state[index].uart_port;
391 if (!port)
392 return -ENODEV;
393
394 s = dev_get_drvdata(port->dev);
395
396 if (!options) {
397 u32 syscon = 0;
398
399 regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
400 if (syscon & SYSCON_UARTEN) {
401 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
402
403 if (ubrlcr & UBRLCR_PRTEN) {
404 if (ubrlcr & UBRLCR_EVENPRT)
405 parity = 'e';
406 else
407 parity = 'o';
408 }
409
410 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
411 bits = 7;
412
413 quot = ubrlcr & UBRLCR_BAUD_MASK;
414 baud = port->uartclk / (16 * (quot + 1));
415 }
416 } else
417 uart_parse_options(options, &baud, &parity, &bits, &flow);
418
419 ret = uart_set_options(port, co, baud, parity, bits, flow);
420 if (ret)
421 return ret;
422
423 return regmap_update_bits(s->syscon, SYSCON_OFFSET,
424 SYSCON_UARTEN, SYSCON_UARTEN);
425}
426
427static struct console clps711x_console = {
428 .name = UART_CLPS711X_DEVNAME,
429 .device = uart_console_device,
430 .write = uart_clps711x_console_write,
431 .setup = uart_clps711x_console_setup,
432 .flags = CON_PRINTBUFFER,
433 .index = -1,
434};
435#endif
436
437static int uart_clps711x_probe(struct platform_device *pdev)
438{
439 struct device_node *np = pdev->dev.of_node;
440 struct clps711x_port *s;
441 struct resource *res;
442 struct clk *uart_clk;
443 int irq, ret;
444
445 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
446 if (!s)
447 return -ENOMEM;
448
449 uart_clk = devm_clk_get(&pdev->dev, NULL);
450 if (IS_ERR(uart_clk))
451 return PTR_ERR(uart_clk);
452
453 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
454 s->port.membase = devm_ioremap_resource(&pdev->dev, res);
455 if (IS_ERR(s->port.membase))
456 return PTR_ERR(s->port.membase);
457
458 irq = platform_get_irq(pdev, 0);
459 if (irq < 0)
460 return irq;
461 s->port.irq = irq;
462
463 s->rx_irq = platform_get_irq(pdev, 1);
464 if (s->rx_irq < 0)
465 return s->rx_irq;
466
467 s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
468 if (IS_ERR(s->syscon))
469 return PTR_ERR(s->syscon);
470
471 s->port.line = of_alias_get_id(np, "serial");
472 s->port.dev = &pdev->dev;
473 s->port.iotype = UPIO_MEM32;
474 s->port.mapbase = res->start;
475 s->port.type = PORT_CLPS711X;
476 s->port.fifosize = 16;
477 s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CLPS711X_CONSOLE);
478 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
479 s->port.uartclk = clk_get_rate(uart_clk);
480 s->port.ops = &uart_clps711x_ops;
481
482 platform_set_drvdata(pdev, s);
483
484 s->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0);
485 if (IS_ERR(s->gpios))
486 return PTR_ERR(s->gpios);
487
488 ret = uart_add_one_port(&clps711x_uart, &s->port);
489 if (ret)
490 return ret;
491
492 /* Disable port */
493 if (!uart_console(&s->port))
494 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
495
496 s->tx_enabled = 1;
497
498 ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0,
499 dev_name(&pdev->dev), &s->port);
500 if (ret) {
501 uart_remove_one_port(&clps711x_uart, &s->port);
502 return ret;
503 }
504
505 ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0,
506 dev_name(&pdev->dev), &s->port);
507 if (ret)
508 uart_remove_one_port(&clps711x_uart, &s->port);
509
510 return ret;
511}
512
513static int uart_clps711x_remove(struct platform_device *pdev)
514{
515 struct clps711x_port *s = platform_get_drvdata(pdev);
516
517 return uart_remove_one_port(&clps711x_uart, &s->port);
518}
519
520static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {
521 { .compatible = "cirrus,ep7209-uart", },
522 { }
523};
524MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids);
525
526static struct platform_driver clps711x_uart_platform = {
527 .driver = {
528 .name = "clps711x-uart",
529 .of_match_table = of_match_ptr(clps711x_uart_dt_ids),
530 },
531 .probe = uart_clps711x_probe,
532 .remove = uart_clps711x_remove,
533};
534
535static int __init uart_clps711x_init(void)
536{
537 int ret;
538
539#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
540 clps711x_uart.cons = &clps711x_console;
541 clps711x_console.data = &clps711x_uart;
542#endif
543
544 ret = uart_register_driver(&clps711x_uart);
545 if (ret)
546 return ret;
547
548 return platform_driver_register(&clps711x_uart_platform);
549}
550module_init(uart_clps711x_init);
551
552static void __exit uart_clps711x_exit(void)
553{
554 platform_driver_unregister(&clps711x_uart_platform);
555 uart_unregister_driver(&clps711x_uart);
556}
557module_exit(uart_clps711x_exit);
558
559MODULE_AUTHOR("Deep Blue Solutions Ltd");
560MODULE_DESCRIPTION("CLPS711X serial driver");
561MODULE_LICENSE("GPL");
1/*
2 * Driver for CLPS711x serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
33#include <linux/spinlock.h>
34#include <linux/device.h>
35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_core.h>
38#include <linux/serial.h>
39#include <linux/io.h>
40
41#include <mach/hardware.h>
42#include <asm/irq.h>
43
44#define UART_NR 2
45
46#define SERIAL_CLPS711X_MAJOR 204
47#define SERIAL_CLPS711X_MINOR 40
48#define SERIAL_CLPS711X_NR UART_NR
49
50/*
51 * We use the relevant SYSCON register as a base address for these ports.
52 */
53#define UBRLCR(port) ((port)->iobase + UBRLCR1 - SYSCON1)
54#define UARTDR(port) ((port)->iobase + UARTDR1 - SYSCON1)
55#define SYSFLG(port) ((port)->iobase + SYSFLG1 - SYSCON1)
56#define SYSCON(port) ((port)->iobase + SYSCON1 - SYSCON1)
57
58#define TX_IRQ(port) ((port)->irq)
59#define RX_IRQ(port) ((port)->irq + 1)
60
61#define UART_ANY_ERR (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR)
62
63#define tx_enabled(port) ((port)->unused[0])
64
65static void clps711xuart_stop_tx(struct uart_port *port)
66{
67 if (tx_enabled(port)) {
68 disable_irq(TX_IRQ(port));
69 tx_enabled(port) = 0;
70 }
71}
72
73static void clps711xuart_start_tx(struct uart_port *port)
74{
75 if (!tx_enabled(port)) {
76 enable_irq(TX_IRQ(port));
77 tx_enabled(port) = 1;
78 }
79}
80
81static void clps711xuart_stop_rx(struct uart_port *port)
82{
83 disable_irq(RX_IRQ(port));
84}
85
86static void clps711xuart_enable_ms(struct uart_port *port)
87{
88}
89
90static irqreturn_t clps711xuart_int_rx(int irq, void *dev_id)
91{
92 struct uart_port *port = dev_id;
93 struct tty_struct *tty = port->state->port.tty;
94 unsigned int status, ch, flg;
95
96 status = clps_readl(SYSFLG(port));
97 while (!(status & SYSFLG_URXFE)) {
98 ch = clps_readl(UARTDR(port));
99
100 port->icount.rx++;
101
102 flg = TTY_NORMAL;
103
104 /*
105 * Note that the error handling code is
106 * out of the main execution path
107 */
108 if (unlikely(ch & UART_ANY_ERR)) {
109 if (ch & UARTDR_PARERR)
110 port->icount.parity++;
111 else if (ch & UARTDR_FRMERR)
112 port->icount.frame++;
113 if (ch & UARTDR_OVERR)
114 port->icount.overrun++;
115
116 ch &= port->read_status_mask;
117
118 if (ch & UARTDR_PARERR)
119 flg = TTY_PARITY;
120 else if (ch & UARTDR_FRMERR)
121 flg = TTY_FRAME;
122
123#ifdef SUPPORT_SYSRQ
124 port->sysrq = 0;
125#endif
126 }
127
128 if (uart_handle_sysrq_char(port, ch))
129 goto ignore_char;
130
131 /*
132 * CHECK: does overrun affect the current character?
133 * ASSUMPTION: it does not.
134 */
135 uart_insert_char(port, ch, UARTDR_OVERR, ch, flg);
136
137 ignore_char:
138 status = clps_readl(SYSFLG(port));
139 }
140 tty_flip_buffer_push(tty);
141 return IRQ_HANDLED;
142}
143
144static irqreturn_t clps711xuart_int_tx(int irq, void *dev_id)
145{
146 struct uart_port *port = dev_id;
147 struct circ_buf *xmit = &port->state->xmit;
148 int count;
149
150 if (port->x_char) {
151 clps_writel(port->x_char, UARTDR(port));
152 port->icount.tx++;
153 port->x_char = 0;
154 return IRQ_HANDLED;
155 }
156
157 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
158 goto disable_tx_irq;
159
160 count = port->fifosize >> 1;
161 do {
162 clps_writel(xmit->buf[xmit->tail], UARTDR(port));
163 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
164 port->icount.tx++;
165 if (uart_circ_empty(xmit))
166 break;
167 } while (--count > 0);
168
169 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
170 uart_write_wakeup(port);
171
172 if (uart_circ_empty(xmit)) {
173 disable_tx_irq:
174 disable_irq_nosync(TX_IRQ(port));
175 tx_enabled(port) = 0;
176 }
177
178 return IRQ_HANDLED;
179}
180
181static unsigned int clps711xuart_tx_empty(struct uart_port *port)
182{
183 unsigned int status = clps_readl(SYSFLG(port));
184 return status & SYSFLG_UBUSY ? 0 : TIOCSER_TEMT;
185}
186
187static unsigned int clps711xuart_get_mctrl(struct uart_port *port)
188{
189 unsigned int port_addr;
190 unsigned int result = 0;
191 unsigned int status;
192
193 port_addr = SYSFLG(port);
194 if (port_addr == SYSFLG1) {
195 status = clps_readl(SYSFLG1);
196 if (status & SYSFLG1_DCD)
197 result |= TIOCM_CAR;
198 if (status & SYSFLG1_DSR)
199 result |= TIOCM_DSR;
200 if (status & SYSFLG1_CTS)
201 result |= TIOCM_CTS;
202 }
203
204 return result;
205}
206
207static void
208clps711xuart_set_mctrl_null(struct uart_port *port, unsigned int mctrl)
209{
210}
211
212static void clps711xuart_break_ctl(struct uart_port *port, int break_state)
213{
214 unsigned long flags;
215 unsigned int ubrlcr;
216
217 spin_lock_irqsave(&port->lock, flags);
218 ubrlcr = clps_readl(UBRLCR(port));
219 if (break_state == -1)
220 ubrlcr |= UBRLCR_BREAK;
221 else
222 ubrlcr &= ~UBRLCR_BREAK;
223 clps_writel(ubrlcr, UBRLCR(port));
224 spin_unlock_irqrestore(&port->lock, flags);
225}
226
227static int clps711xuart_startup(struct uart_port *port)
228{
229 unsigned int syscon;
230 int retval;
231
232 tx_enabled(port) = 1;
233
234 /*
235 * Allocate the IRQs
236 */
237 retval = request_irq(TX_IRQ(port), clps711xuart_int_tx, 0,
238 "clps711xuart_tx", port);
239 if (retval)
240 return retval;
241
242 retval = request_irq(RX_IRQ(port), clps711xuart_int_rx, 0,
243 "clps711xuart_rx", port);
244 if (retval) {
245 free_irq(TX_IRQ(port), port);
246 return retval;
247 }
248
249 /*
250 * enable the port
251 */
252 syscon = clps_readl(SYSCON(port));
253 syscon |= SYSCON_UARTEN;
254 clps_writel(syscon, SYSCON(port));
255
256 return 0;
257}
258
259static void clps711xuart_shutdown(struct uart_port *port)
260{
261 unsigned int ubrlcr, syscon;
262
263 /*
264 * Free the interrupt
265 */
266 free_irq(TX_IRQ(port), port); /* TX interrupt */
267 free_irq(RX_IRQ(port), port); /* RX interrupt */
268
269 /*
270 * disable the port
271 */
272 syscon = clps_readl(SYSCON(port));
273 syscon &= ~SYSCON_UARTEN;
274 clps_writel(syscon, SYSCON(port));
275
276 /*
277 * disable break condition and fifos
278 */
279 ubrlcr = clps_readl(UBRLCR(port));
280 ubrlcr &= ~(UBRLCR_FIFOEN | UBRLCR_BREAK);
281 clps_writel(ubrlcr, UBRLCR(port));
282}
283
284static void
285clps711xuart_set_termios(struct uart_port *port, struct ktermios *termios,
286 struct ktermios *old)
287{
288 unsigned int ubrlcr, baud, quot;
289 unsigned long flags;
290
291 /*
292 * We don't implement CREAD.
293 */
294 termios->c_cflag |= CREAD;
295
296 /*
297 * Ask the core to calculate the divisor for us.
298 */
299 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
300 quot = uart_get_divisor(port, baud);
301
302 switch (termios->c_cflag & CSIZE) {
303 case CS5:
304 ubrlcr = UBRLCR_WRDLEN5;
305 break;
306 case CS6:
307 ubrlcr = UBRLCR_WRDLEN6;
308 break;
309 case CS7:
310 ubrlcr = UBRLCR_WRDLEN7;
311 break;
312 default: // CS8
313 ubrlcr = UBRLCR_WRDLEN8;
314 break;
315 }
316 if (termios->c_cflag & CSTOPB)
317 ubrlcr |= UBRLCR_XSTOP;
318 if (termios->c_cflag & PARENB) {
319 ubrlcr |= UBRLCR_PRTEN;
320 if (!(termios->c_cflag & PARODD))
321 ubrlcr |= UBRLCR_EVENPRT;
322 }
323 if (port->fifosize > 1)
324 ubrlcr |= UBRLCR_FIFOEN;
325
326 spin_lock_irqsave(&port->lock, flags);
327
328 /*
329 * Update the per-port timeout.
330 */
331 uart_update_timeout(port, termios->c_cflag, baud);
332
333 port->read_status_mask = UARTDR_OVERR;
334 if (termios->c_iflag & INPCK)
335 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
336
337 /*
338 * Characters to ignore
339 */
340 port->ignore_status_mask = 0;
341 if (termios->c_iflag & IGNPAR)
342 port->ignore_status_mask |= UARTDR_FRMERR | UARTDR_PARERR;
343 if (termios->c_iflag & IGNBRK) {
344 /*
345 * If we're ignoring parity and break indicators,
346 * ignore overruns to (for real raw support).
347 */
348 if (termios->c_iflag & IGNPAR)
349 port->ignore_status_mask |= UARTDR_OVERR;
350 }
351
352 quot -= 1;
353
354 clps_writel(ubrlcr | quot, UBRLCR(port));
355
356 spin_unlock_irqrestore(&port->lock, flags);
357}
358
359static const char *clps711xuart_type(struct uart_port *port)
360{
361 return port->type == PORT_CLPS711X ? "CLPS711x" : NULL;
362}
363
364/*
365 * Configure/autoconfigure the port.
366 */
367static void clps711xuart_config_port(struct uart_port *port, int flags)
368{
369 if (flags & UART_CONFIG_TYPE)
370 port->type = PORT_CLPS711X;
371}
372
373static void clps711xuart_release_port(struct uart_port *port)
374{
375}
376
377static int clps711xuart_request_port(struct uart_port *port)
378{
379 return 0;
380}
381
382static struct uart_ops clps711x_pops = {
383 .tx_empty = clps711xuart_tx_empty,
384 .set_mctrl = clps711xuart_set_mctrl_null,
385 .get_mctrl = clps711xuart_get_mctrl,
386 .stop_tx = clps711xuart_stop_tx,
387 .start_tx = clps711xuart_start_tx,
388 .stop_rx = clps711xuart_stop_rx,
389 .enable_ms = clps711xuart_enable_ms,
390 .break_ctl = clps711xuart_break_ctl,
391 .startup = clps711xuart_startup,
392 .shutdown = clps711xuart_shutdown,
393 .set_termios = clps711xuart_set_termios,
394 .type = clps711xuart_type,
395 .config_port = clps711xuart_config_port,
396 .release_port = clps711xuart_release_port,
397 .request_port = clps711xuart_request_port,
398};
399
400static struct uart_port clps711x_ports[UART_NR] = {
401 {
402 .iobase = SYSCON1,
403 .irq = IRQ_UTXINT1, /* IRQ_URXINT1, IRQ_UMSINT */
404 .uartclk = 3686400,
405 .fifosize = 16,
406 .ops = &clps711x_pops,
407 .line = 0,
408 .flags = UPF_BOOT_AUTOCONF,
409 },
410 {
411 .iobase = SYSCON2,
412 .irq = IRQ_UTXINT2, /* IRQ_URXINT2 */
413 .uartclk = 3686400,
414 .fifosize = 16,
415 .ops = &clps711x_pops,
416 .line = 1,
417 .flags = UPF_BOOT_AUTOCONF,
418 }
419};
420
421#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
422static void clps711xuart_console_putchar(struct uart_port *port, int ch)
423{
424 while (clps_readl(SYSFLG(port)) & SYSFLG_UTXFF)
425 barrier();
426 clps_writel(ch, UARTDR(port));
427}
428
429/*
430 * Print a string to the serial port trying not to disturb
431 * any possible real use of the port...
432 *
433 * The console_lock must be held when we get here.
434 *
435 * Note that this is called with interrupts already disabled
436 */
437static void
438clps711xuart_console_write(struct console *co, const char *s,
439 unsigned int count)
440{
441 struct uart_port *port = clps711x_ports + co->index;
442 unsigned int status, syscon;
443
444 /*
445 * Ensure that the port is enabled.
446 */
447 syscon = clps_readl(SYSCON(port));
448 clps_writel(syscon | SYSCON_UARTEN, SYSCON(port));
449
450 uart_console_write(port, s, count, clps711xuart_console_putchar);
451
452 /*
453 * Finally, wait for transmitter to become empty
454 * and restore the uart state.
455 */
456 do {
457 status = clps_readl(SYSFLG(port));
458 } while (status & SYSFLG_UBUSY);
459
460 clps_writel(syscon, SYSCON(port));
461}
462
463static void __init
464clps711xuart_console_get_options(struct uart_port *port, int *baud,
465 int *parity, int *bits)
466{
467 if (clps_readl(SYSCON(port)) & SYSCON_UARTEN) {
468 unsigned int ubrlcr, quot;
469
470 ubrlcr = clps_readl(UBRLCR(port));
471
472 *parity = 'n';
473 if (ubrlcr & UBRLCR_PRTEN) {
474 if (ubrlcr & UBRLCR_EVENPRT)
475 *parity = 'e';
476 else
477 *parity = 'o';
478 }
479
480 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
481 *bits = 7;
482 else
483 *bits = 8;
484
485 quot = ubrlcr & UBRLCR_BAUD_MASK;
486 *baud = port->uartclk / (16 * (quot + 1));
487 }
488}
489
490static int __init clps711xuart_console_setup(struct console *co, char *options)
491{
492 struct uart_port *port;
493 int baud = 38400;
494 int bits = 8;
495 int parity = 'n';
496 int flow = 'n';
497
498 /*
499 * Check whether an invalid uart number has been specified, and
500 * if so, search for the first available port that does have
501 * console support.
502 */
503 port = uart_get_console(clps711x_ports, UART_NR, co);
504
505 if (options)
506 uart_parse_options(options, &baud, &parity, &bits, &flow);
507 else
508 clps711xuart_console_get_options(port, &baud, &parity, &bits);
509
510 return uart_set_options(port, co, baud, parity, bits, flow);
511}
512
513static struct uart_driver clps711x_reg;
514static struct console clps711x_console = {
515 .name = "ttyCL",
516 .write = clps711xuart_console_write,
517 .device = uart_console_device,
518 .setup = clps711xuart_console_setup,
519 .flags = CON_PRINTBUFFER,
520 .index = -1,
521 .data = &clps711x_reg,
522};
523
524static int __init clps711xuart_console_init(void)
525{
526 register_console(&clps711x_console);
527 return 0;
528}
529console_initcall(clps711xuart_console_init);
530
531#define CLPS711X_CONSOLE &clps711x_console
532#else
533#define CLPS711X_CONSOLE NULL
534#endif
535
536static struct uart_driver clps711x_reg = {
537 .driver_name = "ttyCL",
538 .dev_name = "ttyCL",
539 .major = SERIAL_CLPS711X_MAJOR,
540 .minor = SERIAL_CLPS711X_MINOR,
541 .nr = UART_NR,
542
543 .cons = CLPS711X_CONSOLE,
544};
545
546static int __init clps711xuart_init(void)
547{
548 int ret, i;
549
550 printk(KERN_INFO "Serial: CLPS711x driver\n");
551
552 ret = uart_register_driver(&clps711x_reg);
553 if (ret)
554 return ret;
555
556 for (i = 0; i < UART_NR; i++)
557 uart_add_one_port(&clps711x_reg, &clps711x_ports[i]);
558
559 return 0;
560}
561
562static void __exit clps711xuart_exit(void)
563{
564 int i;
565
566 for (i = 0; i < UART_NR; i++)
567 uart_remove_one_port(&clps711x_reg, &clps711x_ports[i]);
568
569 uart_unregister_driver(&clps711x_reg);
570}
571
572module_init(clps711xuart_init);
573module_exit(clps711xuart_exit);
574
575MODULE_AUTHOR("Deep Blue Solutions Ltd");
576MODULE_DESCRIPTION("CLPS-711x generic serial driver");
577MODULE_LICENSE("GPL");
578MODULE_ALIAS_CHARDEV(SERIAL_CLPS711X_MAJOR, SERIAL_CLPS711X_MINOR);