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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for AMBA serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
10 *
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
17 */
18
19#include <linux/module.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/sysrq.h>
24#include <linux/device.h>
25#include <linux/tty.h>
26#include <linux/tty_flip.h>
27#include <linux/serial_core.h>
28#include <linux/serial.h>
29#include <linux/amba/bus.h>
30#include <linux/amba/serial.h>
31#include <linux/clk.h>
32#include <linux/slab.h>
33#include <linux/dmaengine.h>
34#include <linux/dma-mapping.h>
35#include <linux/scatterlist.h>
36#include <linux/delay.h>
37#include <linux/types.h>
38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/pinctrl/consumer.h>
41#include <linux/sizes.h>
42#include <linux/io.h>
43#include <linux/acpi.h>
44
45#define UART_NR 14
46
47#define SERIAL_AMBA_MAJOR 204
48#define SERIAL_AMBA_MINOR 64
49#define SERIAL_AMBA_NR UART_NR
50
51#define AMBA_ISR_PASS_LIMIT 256
52
53#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
54#define UART_DUMMY_DR_RX (1 << 16)
55
56enum {
57 REG_DR,
58 REG_ST_DMAWM,
59 REG_ST_TIMEOUT,
60 REG_FR,
61 REG_LCRH_RX,
62 REG_LCRH_TX,
63 REG_IBRD,
64 REG_FBRD,
65 REG_CR,
66 REG_IFLS,
67 REG_IMSC,
68 REG_RIS,
69 REG_MIS,
70 REG_ICR,
71 REG_DMACR,
72 REG_ST_XFCR,
73 REG_ST_XON1,
74 REG_ST_XON2,
75 REG_ST_XOFF1,
76 REG_ST_XOFF2,
77 REG_ST_ITCR,
78 REG_ST_ITIP,
79 REG_ST_ABCR,
80 REG_ST_ABIMSC,
81
82 /* The size of the array - must be last */
83 REG_ARRAY_SIZE,
84};
85
86static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
87 [REG_DR] = UART01x_DR,
88 [REG_FR] = UART01x_FR,
89 [REG_LCRH_RX] = UART011_LCRH,
90 [REG_LCRH_TX] = UART011_LCRH,
91 [REG_IBRD] = UART011_IBRD,
92 [REG_FBRD] = UART011_FBRD,
93 [REG_CR] = UART011_CR,
94 [REG_IFLS] = UART011_IFLS,
95 [REG_IMSC] = UART011_IMSC,
96 [REG_RIS] = UART011_RIS,
97 [REG_MIS] = UART011_MIS,
98 [REG_ICR] = UART011_ICR,
99 [REG_DMACR] = UART011_DMACR,
100};
101
102/* There is by now at least one vendor with differing details, so handle it */
103struct vendor_data {
104 const u16 *reg_offset;
105 unsigned int ifls;
106 unsigned int fr_busy;
107 unsigned int fr_dsr;
108 unsigned int fr_cts;
109 unsigned int fr_ri;
110 unsigned int inv_fr;
111 bool access_32b;
112 bool oversampling;
113 bool dma_threshold;
114 bool cts_event_workaround;
115 bool always_enabled;
116 bool fixed_options;
117
118 unsigned int (*get_fifosize)(struct amba_device *dev);
119};
120
121static unsigned int get_fifosize_arm(struct amba_device *dev)
122{
123 return amba_rev(dev) < 3 ? 16 : 32;
124}
125
126static struct vendor_data vendor_arm = {
127 .reg_offset = pl011_std_offsets,
128 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
129 .fr_busy = UART01x_FR_BUSY,
130 .fr_dsr = UART01x_FR_DSR,
131 .fr_cts = UART01x_FR_CTS,
132 .fr_ri = UART011_FR_RI,
133 .oversampling = false,
134 .dma_threshold = false,
135 .cts_event_workaround = false,
136 .always_enabled = false,
137 .fixed_options = false,
138 .get_fifosize = get_fifosize_arm,
139};
140
141static const struct vendor_data vendor_sbsa = {
142 .reg_offset = pl011_std_offsets,
143 .fr_busy = UART01x_FR_BUSY,
144 .fr_dsr = UART01x_FR_DSR,
145 .fr_cts = UART01x_FR_CTS,
146 .fr_ri = UART011_FR_RI,
147 .access_32b = true,
148 .oversampling = false,
149 .dma_threshold = false,
150 .cts_event_workaround = false,
151 .always_enabled = true,
152 .fixed_options = true,
153};
154
155#ifdef CONFIG_ACPI_SPCR_TABLE
156static const struct vendor_data vendor_qdt_qdf2400_e44 = {
157 .reg_offset = pl011_std_offsets,
158 .fr_busy = UART011_FR_TXFE,
159 .fr_dsr = UART01x_FR_DSR,
160 .fr_cts = UART01x_FR_CTS,
161 .fr_ri = UART011_FR_RI,
162 .inv_fr = UART011_FR_TXFE,
163 .access_32b = true,
164 .oversampling = false,
165 .dma_threshold = false,
166 .cts_event_workaround = false,
167 .always_enabled = true,
168 .fixed_options = true,
169};
170#endif
171
172static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
173 [REG_DR] = UART01x_DR,
174 [REG_ST_DMAWM] = ST_UART011_DMAWM,
175 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
176 [REG_FR] = UART01x_FR,
177 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
178 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
179 [REG_IBRD] = UART011_IBRD,
180 [REG_FBRD] = UART011_FBRD,
181 [REG_CR] = UART011_CR,
182 [REG_IFLS] = UART011_IFLS,
183 [REG_IMSC] = UART011_IMSC,
184 [REG_RIS] = UART011_RIS,
185 [REG_MIS] = UART011_MIS,
186 [REG_ICR] = UART011_ICR,
187 [REG_DMACR] = UART011_DMACR,
188 [REG_ST_XFCR] = ST_UART011_XFCR,
189 [REG_ST_XON1] = ST_UART011_XON1,
190 [REG_ST_XON2] = ST_UART011_XON2,
191 [REG_ST_XOFF1] = ST_UART011_XOFF1,
192 [REG_ST_XOFF2] = ST_UART011_XOFF2,
193 [REG_ST_ITCR] = ST_UART011_ITCR,
194 [REG_ST_ITIP] = ST_UART011_ITIP,
195 [REG_ST_ABCR] = ST_UART011_ABCR,
196 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
197};
198
199static unsigned int get_fifosize_st(struct amba_device *dev)
200{
201 return 64;
202}
203
204static struct vendor_data vendor_st = {
205 .reg_offset = pl011_st_offsets,
206 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
207 .fr_busy = UART01x_FR_BUSY,
208 .fr_dsr = UART01x_FR_DSR,
209 .fr_cts = UART01x_FR_CTS,
210 .fr_ri = UART011_FR_RI,
211 .oversampling = true,
212 .dma_threshold = true,
213 .cts_event_workaround = true,
214 .always_enabled = false,
215 .fixed_options = false,
216 .get_fifosize = get_fifosize_st,
217};
218
219/* Deals with DMA transactions */
220
221struct pl011_sgbuf {
222 struct scatterlist sg;
223 char *buf;
224};
225
226struct pl011_dmarx_data {
227 struct dma_chan *chan;
228 struct completion complete;
229 bool use_buf_b;
230 struct pl011_sgbuf sgbuf_a;
231 struct pl011_sgbuf sgbuf_b;
232 dma_cookie_t cookie;
233 bool running;
234 struct timer_list timer;
235 unsigned int last_residue;
236 unsigned long last_jiffies;
237 bool auto_poll_rate;
238 unsigned int poll_rate;
239 unsigned int poll_timeout;
240};
241
242struct pl011_dmatx_data {
243 struct dma_chan *chan;
244 struct scatterlist sg;
245 char *buf;
246 bool queued;
247};
248
249/*
250 * We wrap our port structure around the generic uart_port.
251 */
252struct uart_amba_port {
253 struct uart_port port;
254 const u16 *reg_offset;
255 struct clk *clk;
256 const struct vendor_data *vendor;
257 unsigned int dmacr; /* dma control reg */
258 unsigned int im; /* interrupt mask */
259 unsigned int old_status;
260 unsigned int fifosize; /* vendor-specific */
261 unsigned int fixed_baud; /* vendor-set fixed baud rate */
262 char type[12];
263 bool rs485_tx_started;
264 unsigned int rs485_tx_drain_interval; /* usecs */
265#ifdef CONFIG_DMA_ENGINE
266 /* DMA stuff */
267 bool using_tx_dma;
268 bool using_rx_dma;
269 struct pl011_dmarx_data dmarx;
270 struct pl011_dmatx_data dmatx;
271 bool dma_probed;
272#endif
273};
274
275static unsigned int pl011_tx_empty(struct uart_port *port);
276
277static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
278 unsigned int reg)
279{
280 return uap->reg_offset[reg];
281}
282
283static unsigned int pl011_read(const struct uart_amba_port *uap,
284 unsigned int reg)
285{
286 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
287
288 return (uap->port.iotype == UPIO_MEM32) ?
289 readl_relaxed(addr) : readw_relaxed(addr);
290}
291
292static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
293 unsigned int reg)
294{
295 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
296
297 if (uap->port.iotype == UPIO_MEM32)
298 writel_relaxed(val, addr);
299 else
300 writew_relaxed(val, addr);
301}
302
303/*
304 * Reads up to 256 characters from the FIFO or until it's empty and
305 * inserts them into the TTY layer. Returns the number of characters
306 * read from the FIFO.
307 */
308static int pl011_fifo_to_tty(struct uart_amba_port *uap)
309{
310 unsigned int ch, flag, fifotaken;
311 int sysrq;
312 u16 status;
313
314 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
315 status = pl011_read(uap, REG_FR);
316 if (status & UART01x_FR_RXFE)
317 break;
318
319 /* Take chars from the FIFO and update status */
320 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
321 flag = TTY_NORMAL;
322 uap->port.icount.rx++;
323
324 if (unlikely(ch & UART_DR_ERROR)) {
325 if (ch & UART011_DR_BE) {
326 ch &= ~(UART011_DR_FE | UART011_DR_PE);
327 uap->port.icount.brk++;
328 if (uart_handle_break(&uap->port))
329 continue;
330 } else if (ch & UART011_DR_PE)
331 uap->port.icount.parity++;
332 else if (ch & UART011_DR_FE)
333 uap->port.icount.frame++;
334 if (ch & UART011_DR_OE)
335 uap->port.icount.overrun++;
336
337 ch &= uap->port.read_status_mask;
338
339 if (ch & UART011_DR_BE)
340 flag = TTY_BREAK;
341 else if (ch & UART011_DR_PE)
342 flag = TTY_PARITY;
343 else if (ch & UART011_DR_FE)
344 flag = TTY_FRAME;
345 }
346
347 spin_unlock(&uap->port.lock);
348 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
349 spin_lock(&uap->port.lock);
350
351 if (!sysrq)
352 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
353 }
354
355 return fifotaken;
356}
357
358
359/*
360 * All the DMA operation mode stuff goes inside this ifdef.
361 * This assumes that you have a generic DMA device interface,
362 * no custom DMA interfaces are supported.
363 */
364#ifdef CONFIG_DMA_ENGINE
365
366#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
367
368static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
369 enum dma_data_direction dir)
370{
371 dma_addr_t dma_addr;
372
373 sg->buf = dma_alloc_coherent(chan->device->dev,
374 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
375 if (!sg->buf)
376 return -ENOMEM;
377
378 sg_init_table(&sg->sg, 1);
379 sg_set_page(&sg->sg, phys_to_page(dma_addr),
380 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
381 sg_dma_address(&sg->sg) = dma_addr;
382 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
383
384 return 0;
385}
386
387static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
388 enum dma_data_direction dir)
389{
390 if (sg->buf) {
391 dma_free_coherent(chan->device->dev,
392 PL011_DMA_BUFFER_SIZE, sg->buf,
393 sg_dma_address(&sg->sg));
394 }
395}
396
397static void pl011_dma_probe(struct uart_amba_port *uap)
398{
399 /* DMA is the sole user of the platform data right now */
400 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
401 struct device *dev = uap->port.dev;
402 struct dma_slave_config tx_conf = {
403 .dst_addr = uap->port.mapbase +
404 pl011_reg_to_offset(uap, REG_DR),
405 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
406 .direction = DMA_MEM_TO_DEV,
407 .dst_maxburst = uap->fifosize >> 1,
408 .device_fc = false,
409 };
410 struct dma_chan *chan;
411 dma_cap_mask_t mask;
412
413 uap->dma_probed = true;
414 chan = dma_request_chan(dev, "tx");
415 if (IS_ERR(chan)) {
416 if (PTR_ERR(chan) == -EPROBE_DEFER) {
417 uap->dma_probed = false;
418 return;
419 }
420
421 /* We need platform data */
422 if (!plat || !plat->dma_filter) {
423 dev_info(uap->port.dev, "no DMA platform data\n");
424 return;
425 }
426
427 /* Try to acquire a generic DMA engine slave TX channel */
428 dma_cap_zero(mask);
429 dma_cap_set(DMA_SLAVE, mask);
430
431 chan = dma_request_channel(mask, plat->dma_filter,
432 plat->dma_tx_param);
433 if (!chan) {
434 dev_err(uap->port.dev, "no TX DMA channel!\n");
435 return;
436 }
437 }
438
439 dmaengine_slave_config(chan, &tx_conf);
440 uap->dmatx.chan = chan;
441
442 dev_info(uap->port.dev, "DMA channel TX %s\n",
443 dma_chan_name(uap->dmatx.chan));
444
445 /* Optionally make use of an RX channel as well */
446 chan = dma_request_slave_channel(dev, "rx");
447
448 if (!chan && plat && plat->dma_rx_param) {
449 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
450
451 if (!chan) {
452 dev_err(uap->port.dev, "no RX DMA channel!\n");
453 return;
454 }
455 }
456
457 if (chan) {
458 struct dma_slave_config rx_conf = {
459 .src_addr = uap->port.mapbase +
460 pl011_reg_to_offset(uap, REG_DR),
461 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
462 .direction = DMA_DEV_TO_MEM,
463 .src_maxburst = uap->fifosize >> 2,
464 .device_fc = false,
465 };
466 struct dma_slave_caps caps;
467
468 /*
469 * Some DMA controllers provide information on their capabilities.
470 * If the controller does, check for suitable residue processing
471 * otherwise assime all is well.
472 */
473 if (0 == dma_get_slave_caps(chan, &caps)) {
474 if (caps.residue_granularity ==
475 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
476 dma_release_channel(chan);
477 dev_info(uap->port.dev,
478 "RX DMA disabled - no residue processing\n");
479 return;
480 }
481 }
482 dmaengine_slave_config(chan, &rx_conf);
483 uap->dmarx.chan = chan;
484
485 uap->dmarx.auto_poll_rate = false;
486 if (plat && plat->dma_rx_poll_enable) {
487 /* Set poll rate if specified. */
488 if (plat->dma_rx_poll_rate) {
489 uap->dmarx.auto_poll_rate = false;
490 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
491 } else {
492 /*
493 * 100 ms defaults to poll rate if not
494 * specified. This will be adjusted with
495 * the baud rate at set_termios.
496 */
497 uap->dmarx.auto_poll_rate = true;
498 uap->dmarx.poll_rate = 100;
499 }
500 /* 3 secs defaults poll_timeout if not specified. */
501 if (plat->dma_rx_poll_timeout)
502 uap->dmarx.poll_timeout =
503 plat->dma_rx_poll_timeout;
504 else
505 uap->dmarx.poll_timeout = 3000;
506 } else if (!plat && dev->of_node) {
507 uap->dmarx.auto_poll_rate = of_property_read_bool(
508 dev->of_node, "auto-poll");
509 if (uap->dmarx.auto_poll_rate) {
510 u32 x;
511
512 if (0 == of_property_read_u32(dev->of_node,
513 "poll-rate-ms", &x))
514 uap->dmarx.poll_rate = x;
515 else
516 uap->dmarx.poll_rate = 100;
517 if (0 == of_property_read_u32(dev->of_node,
518 "poll-timeout-ms", &x))
519 uap->dmarx.poll_timeout = x;
520 else
521 uap->dmarx.poll_timeout = 3000;
522 }
523 }
524 dev_info(uap->port.dev, "DMA channel RX %s\n",
525 dma_chan_name(uap->dmarx.chan));
526 }
527}
528
529static void pl011_dma_remove(struct uart_amba_port *uap)
530{
531 if (uap->dmatx.chan)
532 dma_release_channel(uap->dmatx.chan);
533 if (uap->dmarx.chan)
534 dma_release_channel(uap->dmarx.chan);
535}
536
537/* Forward declare these for the refill routine */
538static int pl011_dma_tx_refill(struct uart_amba_port *uap);
539static void pl011_start_tx_pio(struct uart_amba_port *uap);
540
541/*
542 * The current DMA TX buffer has been sent.
543 * Try to queue up another DMA buffer.
544 */
545static void pl011_dma_tx_callback(void *data)
546{
547 struct uart_amba_port *uap = data;
548 struct pl011_dmatx_data *dmatx = &uap->dmatx;
549 unsigned long flags;
550 u16 dmacr;
551
552 spin_lock_irqsave(&uap->port.lock, flags);
553 if (uap->dmatx.queued)
554 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
555 DMA_TO_DEVICE);
556
557 dmacr = uap->dmacr;
558 uap->dmacr = dmacr & ~UART011_TXDMAE;
559 pl011_write(uap->dmacr, uap, REG_DMACR);
560
561 /*
562 * If TX DMA was disabled, it means that we've stopped the DMA for
563 * some reason (eg, XOFF received, or we want to send an X-char.)
564 *
565 * Note: we need to be careful here of a potential race between DMA
566 * and the rest of the driver - if the driver disables TX DMA while
567 * a TX buffer completing, we must update the tx queued status to
568 * get further refills (hence we check dmacr).
569 */
570 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
571 uart_circ_empty(&uap->port.state->xmit)) {
572 uap->dmatx.queued = false;
573 spin_unlock_irqrestore(&uap->port.lock, flags);
574 return;
575 }
576
577 if (pl011_dma_tx_refill(uap) <= 0)
578 /*
579 * We didn't queue a DMA buffer for some reason, but we
580 * have data pending to be sent. Re-enable the TX IRQ.
581 */
582 pl011_start_tx_pio(uap);
583
584 spin_unlock_irqrestore(&uap->port.lock, flags);
585}
586
587/*
588 * Try to refill the TX DMA buffer.
589 * Locking: called with port lock held and IRQs disabled.
590 * Returns:
591 * 1 if we queued up a TX DMA buffer.
592 * 0 if we didn't want to handle this by DMA
593 * <0 on error
594 */
595static int pl011_dma_tx_refill(struct uart_amba_port *uap)
596{
597 struct pl011_dmatx_data *dmatx = &uap->dmatx;
598 struct dma_chan *chan = dmatx->chan;
599 struct dma_device *dma_dev = chan->device;
600 struct dma_async_tx_descriptor *desc;
601 struct circ_buf *xmit = &uap->port.state->xmit;
602 unsigned int count;
603
604 /*
605 * Try to avoid the overhead involved in using DMA if the
606 * transaction fits in the first half of the FIFO, by using
607 * the standard interrupt handling. This ensures that we
608 * issue a uart_write_wakeup() at the appropriate time.
609 */
610 count = uart_circ_chars_pending(xmit);
611 if (count < (uap->fifosize >> 1)) {
612 uap->dmatx.queued = false;
613 return 0;
614 }
615
616 /*
617 * Bodge: don't send the last character by DMA, as this
618 * will prevent XON from notifying us to restart DMA.
619 */
620 count -= 1;
621
622 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
623 if (count > PL011_DMA_BUFFER_SIZE)
624 count = PL011_DMA_BUFFER_SIZE;
625
626 if (xmit->tail < xmit->head)
627 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
628 else {
629 size_t first = UART_XMIT_SIZE - xmit->tail;
630 size_t second;
631
632 if (first > count)
633 first = count;
634 second = count - first;
635
636 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
637 if (second)
638 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
639 }
640
641 dmatx->sg.length = count;
642
643 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
644 uap->dmatx.queued = false;
645 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
646 return -EBUSY;
647 }
648
649 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
650 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
651 if (!desc) {
652 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
653 uap->dmatx.queued = false;
654 /*
655 * If DMA cannot be used right now, we complete this
656 * transaction via IRQ and let the TTY layer retry.
657 */
658 dev_dbg(uap->port.dev, "TX DMA busy\n");
659 return -EBUSY;
660 }
661
662 /* Some data to go along to the callback */
663 desc->callback = pl011_dma_tx_callback;
664 desc->callback_param = uap;
665
666 /* All errors should happen at prepare time */
667 dmaengine_submit(desc);
668
669 /* Fire the DMA transaction */
670 dma_dev->device_issue_pending(chan);
671
672 uap->dmacr |= UART011_TXDMAE;
673 pl011_write(uap->dmacr, uap, REG_DMACR);
674 uap->dmatx.queued = true;
675
676 /*
677 * Now we know that DMA will fire, so advance the ring buffer
678 * with the stuff we just dispatched.
679 */
680 uart_xmit_advance(&uap->port, count);
681
682 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
683 uart_write_wakeup(&uap->port);
684
685 return 1;
686}
687
688/*
689 * We received a transmit interrupt without a pending X-char but with
690 * pending characters.
691 * Locking: called with port lock held and IRQs disabled.
692 * Returns:
693 * false if we want to use PIO to transmit
694 * true if we queued a DMA buffer
695 */
696static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
697{
698 if (!uap->using_tx_dma)
699 return false;
700
701 /*
702 * If we already have a TX buffer queued, but received a
703 * TX interrupt, it will be because we've just sent an X-char.
704 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
705 */
706 if (uap->dmatx.queued) {
707 uap->dmacr |= UART011_TXDMAE;
708 pl011_write(uap->dmacr, uap, REG_DMACR);
709 uap->im &= ~UART011_TXIM;
710 pl011_write(uap->im, uap, REG_IMSC);
711 return true;
712 }
713
714 /*
715 * We don't have a TX buffer queued, so try to queue one.
716 * If we successfully queued a buffer, mask the TX IRQ.
717 */
718 if (pl011_dma_tx_refill(uap) > 0) {
719 uap->im &= ~UART011_TXIM;
720 pl011_write(uap->im, uap, REG_IMSC);
721 return true;
722 }
723 return false;
724}
725
726/*
727 * Stop the DMA transmit (eg, due to received XOFF).
728 * Locking: called with port lock held and IRQs disabled.
729 */
730static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
731{
732 if (uap->dmatx.queued) {
733 uap->dmacr &= ~UART011_TXDMAE;
734 pl011_write(uap->dmacr, uap, REG_DMACR);
735 }
736}
737
738/*
739 * Try to start a DMA transmit, or in the case of an XON/OFF
740 * character queued for send, try to get that character out ASAP.
741 * Locking: called with port lock held and IRQs disabled.
742 * Returns:
743 * false if we want the TX IRQ to be enabled
744 * true if we have a buffer queued
745 */
746static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
747{
748 u16 dmacr;
749
750 if (!uap->using_tx_dma)
751 return false;
752
753 if (!uap->port.x_char) {
754 /* no X-char, try to push chars out in DMA mode */
755 bool ret = true;
756
757 if (!uap->dmatx.queued) {
758 if (pl011_dma_tx_refill(uap) > 0) {
759 uap->im &= ~UART011_TXIM;
760 pl011_write(uap->im, uap, REG_IMSC);
761 } else
762 ret = false;
763 } else if (!(uap->dmacr & UART011_TXDMAE)) {
764 uap->dmacr |= UART011_TXDMAE;
765 pl011_write(uap->dmacr, uap, REG_DMACR);
766 }
767 return ret;
768 }
769
770 /*
771 * We have an X-char to send. Disable DMA to prevent it loading
772 * the TX fifo, and then see if we can stuff it into the FIFO.
773 */
774 dmacr = uap->dmacr;
775 uap->dmacr &= ~UART011_TXDMAE;
776 pl011_write(uap->dmacr, uap, REG_DMACR);
777
778 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
779 /*
780 * No space in the FIFO, so enable the transmit interrupt
781 * so we know when there is space. Note that once we've
782 * loaded the character, we should just re-enable DMA.
783 */
784 return false;
785 }
786
787 pl011_write(uap->port.x_char, uap, REG_DR);
788 uap->port.icount.tx++;
789 uap->port.x_char = 0;
790
791 /* Success - restore the DMA state */
792 uap->dmacr = dmacr;
793 pl011_write(dmacr, uap, REG_DMACR);
794
795 return true;
796}
797
798/*
799 * Flush the transmit buffer.
800 * Locking: called with port lock held and IRQs disabled.
801 */
802static void pl011_dma_flush_buffer(struct uart_port *port)
803__releases(&uap->port.lock)
804__acquires(&uap->port.lock)
805{
806 struct uart_amba_port *uap =
807 container_of(port, struct uart_amba_port, port);
808
809 if (!uap->using_tx_dma)
810 return;
811
812 dmaengine_terminate_async(uap->dmatx.chan);
813
814 if (uap->dmatx.queued) {
815 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
816 DMA_TO_DEVICE);
817 uap->dmatx.queued = false;
818 uap->dmacr &= ~UART011_TXDMAE;
819 pl011_write(uap->dmacr, uap, REG_DMACR);
820 }
821}
822
823static void pl011_dma_rx_callback(void *data);
824
825static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
826{
827 struct dma_chan *rxchan = uap->dmarx.chan;
828 struct pl011_dmarx_data *dmarx = &uap->dmarx;
829 struct dma_async_tx_descriptor *desc;
830 struct pl011_sgbuf *sgbuf;
831
832 if (!rxchan)
833 return -EIO;
834
835 /* Start the RX DMA job */
836 sgbuf = uap->dmarx.use_buf_b ?
837 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
838 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
839 DMA_DEV_TO_MEM,
840 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
841 /*
842 * If the DMA engine is busy and cannot prepare a
843 * channel, no big deal, the driver will fall back
844 * to interrupt mode as a result of this error code.
845 */
846 if (!desc) {
847 uap->dmarx.running = false;
848 dmaengine_terminate_all(rxchan);
849 return -EBUSY;
850 }
851
852 /* Some data to go along to the callback */
853 desc->callback = pl011_dma_rx_callback;
854 desc->callback_param = uap;
855 dmarx->cookie = dmaengine_submit(desc);
856 dma_async_issue_pending(rxchan);
857
858 uap->dmacr |= UART011_RXDMAE;
859 pl011_write(uap->dmacr, uap, REG_DMACR);
860 uap->dmarx.running = true;
861
862 uap->im &= ~UART011_RXIM;
863 pl011_write(uap->im, uap, REG_IMSC);
864
865 return 0;
866}
867
868/*
869 * This is called when either the DMA job is complete, or
870 * the FIFO timeout interrupt occurred. This must be called
871 * with the port spinlock uap->port.lock held.
872 */
873static void pl011_dma_rx_chars(struct uart_amba_port *uap,
874 u32 pending, bool use_buf_b,
875 bool readfifo)
876{
877 struct tty_port *port = &uap->port.state->port;
878 struct pl011_sgbuf *sgbuf = use_buf_b ?
879 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
880 int dma_count = 0;
881 u32 fifotaken = 0; /* only used for vdbg() */
882
883 struct pl011_dmarx_data *dmarx = &uap->dmarx;
884 int dmataken = 0;
885
886 if (uap->dmarx.poll_rate) {
887 /* The data can be taken by polling */
888 dmataken = sgbuf->sg.length - dmarx->last_residue;
889 /* Recalculate the pending size */
890 if (pending >= dmataken)
891 pending -= dmataken;
892 }
893
894 /* Pick the remain data from the DMA */
895 if (pending) {
896
897 /*
898 * First take all chars in the DMA pipe, then look in the FIFO.
899 * Note that tty_insert_flip_buf() tries to take as many chars
900 * as it can.
901 */
902 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
903 pending);
904
905 uap->port.icount.rx += dma_count;
906 if (dma_count < pending)
907 dev_warn(uap->port.dev,
908 "couldn't insert all characters (TTY is full?)\n");
909 }
910
911 /* Reset the last_residue for Rx DMA poll */
912 if (uap->dmarx.poll_rate)
913 dmarx->last_residue = sgbuf->sg.length;
914
915 /*
916 * Only continue with trying to read the FIFO if all DMA chars have
917 * been taken first.
918 */
919 if (dma_count == pending && readfifo) {
920 /* Clear any error flags */
921 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
922 UART011_FEIS, uap, REG_ICR);
923
924 /*
925 * If we read all the DMA'd characters, and we had an
926 * incomplete buffer, that could be due to an rx error, or
927 * maybe we just timed out. Read any pending chars and check
928 * the error status.
929 *
930 * Error conditions will only occur in the FIFO, these will
931 * trigger an immediate interrupt and stop the DMA job, so we
932 * will always find the error in the FIFO, never in the DMA
933 * buffer.
934 */
935 fifotaken = pl011_fifo_to_tty(uap);
936 }
937
938 dev_vdbg(uap->port.dev,
939 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
940 dma_count, fifotaken);
941 tty_flip_buffer_push(port);
942}
943
944static void pl011_dma_rx_irq(struct uart_amba_port *uap)
945{
946 struct pl011_dmarx_data *dmarx = &uap->dmarx;
947 struct dma_chan *rxchan = dmarx->chan;
948 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
949 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
950 size_t pending;
951 struct dma_tx_state state;
952 enum dma_status dmastat;
953
954 /*
955 * Pause the transfer so we can trust the current counter,
956 * do this before we pause the PL011 block, else we may
957 * overflow the FIFO.
958 */
959 if (dmaengine_pause(rxchan))
960 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
961 dmastat = rxchan->device->device_tx_status(rxchan,
962 dmarx->cookie, &state);
963 if (dmastat != DMA_PAUSED)
964 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
965
966 /* Disable RX DMA - incoming data will wait in the FIFO */
967 uap->dmacr &= ~UART011_RXDMAE;
968 pl011_write(uap->dmacr, uap, REG_DMACR);
969 uap->dmarx.running = false;
970
971 pending = sgbuf->sg.length - state.residue;
972 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
973 /* Then we terminate the transfer - we now know our residue */
974 dmaengine_terminate_all(rxchan);
975
976 /*
977 * This will take the chars we have so far and insert
978 * into the framework.
979 */
980 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
981
982 /* Switch buffer & re-trigger DMA job */
983 dmarx->use_buf_b = !dmarx->use_buf_b;
984 if (pl011_dma_rx_trigger_dma(uap)) {
985 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
986 "fall back to interrupt mode\n");
987 uap->im |= UART011_RXIM;
988 pl011_write(uap->im, uap, REG_IMSC);
989 }
990}
991
992static void pl011_dma_rx_callback(void *data)
993{
994 struct uart_amba_port *uap = data;
995 struct pl011_dmarx_data *dmarx = &uap->dmarx;
996 struct dma_chan *rxchan = dmarx->chan;
997 bool lastbuf = dmarx->use_buf_b;
998 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
999 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1000 size_t pending;
1001 struct dma_tx_state state;
1002 int ret;
1003
1004 /*
1005 * This completion interrupt occurs typically when the
1006 * RX buffer is totally stuffed but no timeout has yet
1007 * occurred. When that happens, we just want the RX
1008 * routine to flush out the secondary DMA buffer while
1009 * we immediately trigger the next DMA job.
1010 */
1011 spin_lock_irq(&uap->port.lock);
1012 /*
1013 * Rx data can be taken by the UART interrupts during
1014 * the DMA irq handler. So we check the residue here.
1015 */
1016 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1017 pending = sgbuf->sg.length - state.residue;
1018 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1019 /* Then we terminate the transfer - we now know our residue */
1020 dmaengine_terminate_all(rxchan);
1021
1022 uap->dmarx.running = false;
1023 dmarx->use_buf_b = !lastbuf;
1024 ret = pl011_dma_rx_trigger_dma(uap);
1025
1026 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1027 spin_unlock_irq(&uap->port.lock);
1028 /*
1029 * Do this check after we picked the DMA chars so we don't
1030 * get some IRQ immediately from RX.
1031 */
1032 if (ret) {
1033 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1034 "fall back to interrupt mode\n");
1035 uap->im |= UART011_RXIM;
1036 pl011_write(uap->im, uap, REG_IMSC);
1037 }
1038}
1039
1040/*
1041 * Stop accepting received characters, when we're shutting down or
1042 * suspending this port.
1043 * Locking: called with port lock held and IRQs disabled.
1044 */
1045static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1046{
1047 if (!uap->using_rx_dma)
1048 return;
1049
1050 /* FIXME. Just disable the DMA enable */
1051 uap->dmacr &= ~UART011_RXDMAE;
1052 pl011_write(uap->dmacr, uap, REG_DMACR);
1053}
1054
1055/*
1056 * Timer handler for Rx DMA polling.
1057 * Every polling, It checks the residue in the dma buffer and transfer
1058 * data to the tty. Also, last_residue is updated for the next polling.
1059 */
1060static void pl011_dma_rx_poll(struct timer_list *t)
1061{
1062 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1063 struct tty_port *port = &uap->port.state->port;
1064 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1065 struct dma_chan *rxchan = uap->dmarx.chan;
1066 unsigned long flags;
1067 unsigned int dmataken = 0;
1068 unsigned int size = 0;
1069 struct pl011_sgbuf *sgbuf;
1070 int dma_count;
1071 struct dma_tx_state state;
1072
1073 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1074 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1075 if (likely(state.residue < dmarx->last_residue)) {
1076 dmataken = sgbuf->sg.length - dmarx->last_residue;
1077 size = dmarx->last_residue - state.residue;
1078 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1079 size);
1080 if (dma_count == size)
1081 dmarx->last_residue = state.residue;
1082 dmarx->last_jiffies = jiffies;
1083 }
1084 tty_flip_buffer_push(port);
1085
1086 /*
1087 * If no data is received in poll_timeout, the driver will fall back
1088 * to interrupt mode. We will retrigger DMA at the first interrupt.
1089 */
1090 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1091 > uap->dmarx.poll_timeout) {
1092
1093 spin_lock_irqsave(&uap->port.lock, flags);
1094 pl011_dma_rx_stop(uap);
1095 uap->im |= UART011_RXIM;
1096 pl011_write(uap->im, uap, REG_IMSC);
1097 spin_unlock_irqrestore(&uap->port.lock, flags);
1098
1099 uap->dmarx.running = false;
1100 dmaengine_terminate_all(rxchan);
1101 del_timer(&uap->dmarx.timer);
1102 } else {
1103 mod_timer(&uap->dmarx.timer,
1104 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1105 }
1106}
1107
1108static void pl011_dma_startup(struct uart_amba_port *uap)
1109{
1110 int ret;
1111
1112 if (!uap->dma_probed)
1113 pl011_dma_probe(uap);
1114
1115 if (!uap->dmatx.chan)
1116 return;
1117
1118 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1119 if (!uap->dmatx.buf) {
1120 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1121 uap->port.fifosize = uap->fifosize;
1122 return;
1123 }
1124
1125 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1126
1127 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1128 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1129 uap->using_tx_dma = true;
1130
1131 if (!uap->dmarx.chan)
1132 goto skip_rx;
1133
1134 /* Allocate and map DMA RX buffers */
1135 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1136 DMA_FROM_DEVICE);
1137 if (ret) {
1138 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1139 "RX buffer A", ret);
1140 goto skip_rx;
1141 }
1142
1143 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1144 DMA_FROM_DEVICE);
1145 if (ret) {
1146 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1147 "RX buffer B", ret);
1148 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1149 DMA_FROM_DEVICE);
1150 goto skip_rx;
1151 }
1152
1153 uap->using_rx_dma = true;
1154
1155skip_rx:
1156 /* Turn on DMA error (RX/TX will be enabled on demand) */
1157 uap->dmacr |= UART011_DMAONERR;
1158 pl011_write(uap->dmacr, uap, REG_DMACR);
1159
1160 /*
1161 * ST Micro variants has some specific dma burst threshold
1162 * compensation. Set this to 16 bytes, so burst will only
1163 * be issued above/below 16 bytes.
1164 */
1165 if (uap->vendor->dma_threshold)
1166 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1167 uap, REG_ST_DMAWM);
1168
1169 if (uap->using_rx_dma) {
1170 if (pl011_dma_rx_trigger_dma(uap))
1171 dev_dbg(uap->port.dev, "could not trigger initial "
1172 "RX DMA job, fall back to interrupt mode\n");
1173 if (uap->dmarx.poll_rate) {
1174 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1175 mod_timer(&uap->dmarx.timer,
1176 jiffies +
1177 msecs_to_jiffies(uap->dmarx.poll_rate));
1178 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1179 uap->dmarx.last_jiffies = jiffies;
1180 }
1181 }
1182}
1183
1184static void pl011_dma_shutdown(struct uart_amba_port *uap)
1185{
1186 if (!(uap->using_tx_dma || uap->using_rx_dma))
1187 return;
1188
1189 /* Disable RX and TX DMA */
1190 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1191 cpu_relax();
1192
1193 spin_lock_irq(&uap->port.lock);
1194 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1195 pl011_write(uap->dmacr, uap, REG_DMACR);
1196 spin_unlock_irq(&uap->port.lock);
1197
1198 if (uap->using_tx_dma) {
1199 /* In theory, this should already be done by pl011_dma_flush_buffer */
1200 dmaengine_terminate_all(uap->dmatx.chan);
1201 if (uap->dmatx.queued) {
1202 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1203 DMA_TO_DEVICE);
1204 uap->dmatx.queued = false;
1205 }
1206
1207 kfree(uap->dmatx.buf);
1208 uap->using_tx_dma = false;
1209 }
1210
1211 if (uap->using_rx_dma) {
1212 dmaengine_terminate_all(uap->dmarx.chan);
1213 /* Clean up the RX DMA */
1214 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1215 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1216 if (uap->dmarx.poll_rate)
1217 del_timer_sync(&uap->dmarx.timer);
1218 uap->using_rx_dma = false;
1219 }
1220}
1221
1222static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1223{
1224 return uap->using_rx_dma;
1225}
1226
1227static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1228{
1229 return uap->using_rx_dma && uap->dmarx.running;
1230}
1231
1232#else
1233/* Blank functions if the DMA engine is not available */
1234static inline void pl011_dma_remove(struct uart_amba_port *uap)
1235{
1236}
1237
1238static inline void pl011_dma_startup(struct uart_amba_port *uap)
1239{
1240}
1241
1242static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1243{
1244}
1245
1246static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1247{
1248 return false;
1249}
1250
1251static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1252{
1253}
1254
1255static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1256{
1257 return false;
1258}
1259
1260static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1261{
1262}
1263
1264static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1265{
1266}
1267
1268static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1269{
1270 return -EIO;
1271}
1272
1273static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1274{
1275 return false;
1276}
1277
1278static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1279{
1280 return false;
1281}
1282
1283#define pl011_dma_flush_buffer NULL
1284#endif
1285
1286static void pl011_rs485_tx_stop(struct uart_amba_port *uap)
1287{
1288 /*
1289 * To be on the safe side only time out after twice as many iterations
1290 * as fifo size.
1291 */
1292 const int MAX_TX_DRAIN_ITERS = uap->port.fifosize * 2;
1293 struct uart_port *port = &uap->port;
1294 int i = 0;
1295 u32 cr;
1296
1297 /* Wait until hardware tx queue is empty */
1298 while (!pl011_tx_empty(port)) {
1299 if (i > MAX_TX_DRAIN_ITERS) {
1300 dev_warn(port->dev,
1301 "timeout while draining hardware tx queue\n");
1302 break;
1303 }
1304
1305 udelay(uap->rs485_tx_drain_interval);
1306 i++;
1307 }
1308
1309 if (port->rs485.delay_rts_after_send)
1310 mdelay(port->rs485.delay_rts_after_send);
1311
1312 cr = pl011_read(uap, REG_CR);
1313
1314 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1315 cr &= ~UART011_CR_RTS;
1316 else
1317 cr |= UART011_CR_RTS;
1318
1319 /* Disable the transmitter and reenable the transceiver */
1320 cr &= ~UART011_CR_TXE;
1321 cr |= UART011_CR_RXE;
1322 pl011_write(cr, uap, REG_CR);
1323
1324 uap->rs485_tx_started = false;
1325}
1326
1327static void pl011_stop_tx(struct uart_port *port)
1328{
1329 struct uart_amba_port *uap =
1330 container_of(port, struct uart_amba_port, port);
1331
1332 uap->im &= ~UART011_TXIM;
1333 pl011_write(uap->im, uap, REG_IMSC);
1334 pl011_dma_tx_stop(uap);
1335
1336 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1337 pl011_rs485_tx_stop(uap);
1338}
1339
1340static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1341
1342/* Start TX with programmed I/O only (no DMA) */
1343static void pl011_start_tx_pio(struct uart_amba_port *uap)
1344{
1345 if (pl011_tx_chars(uap, false)) {
1346 uap->im |= UART011_TXIM;
1347 pl011_write(uap->im, uap, REG_IMSC);
1348 }
1349}
1350
1351static void pl011_start_tx(struct uart_port *port)
1352{
1353 struct uart_amba_port *uap =
1354 container_of(port, struct uart_amba_port, port);
1355
1356 if (!pl011_dma_tx_start(uap))
1357 pl011_start_tx_pio(uap);
1358}
1359
1360static void pl011_stop_rx(struct uart_port *port)
1361{
1362 struct uart_amba_port *uap =
1363 container_of(port, struct uart_amba_port, port);
1364
1365 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1366 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1367 pl011_write(uap->im, uap, REG_IMSC);
1368
1369 pl011_dma_rx_stop(uap);
1370}
1371
1372static void pl011_throttle_rx(struct uart_port *port)
1373{
1374 unsigned long flags;
1375
1376 spin_lock_irqsave(&port->lock, flags);
1377 pl011_stop_rx(port);
1378 spin_unlock_irqrestore(&port->lock, flags);
1379}
1380
1381static void pl011_enable_ms(struct uart_port *port)
1382{
1383 struct uart_amba_port *uap =
1384 container_of(port, struct uart_amba_port, port);
1385
1386 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1387 pl011_write(uap->im, uap, REG_IMSC);
1388}
1389
1390static void pl011_rx_chars(struct uart_amba_port *uap)
1391__releases(&uap->port.lock)
1392__acquires(&uap->port.lock)
1393{
1394 pl011_fifo_to_tty(uap);
1395
1396 spin_unlock(&uap->port.lock);
1397 tty_flip_buffer_push(&uap->port.state->port);
1398 /*
1399 * If we were temporarily out of DMA mode for a while,
1400 * attempt to switch back to DMA mode again.
1401 */
1402 if (pl011_dma_rx_available(uap)) {
1403 if (pl011_dma_rx_trigger_dma(uap)) {
1404 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1405 "fall back to interrupt mode again\n");
1406 uap->im |= UART011_RXIM;
1407 pl011_write(uap->im, uap, REG_IMSC);
1408 } else {
1409#ifdef CONFIG_DMA_ENGINE
1410 /* Start Rx DMA poll */
1411 if (uap->dmarx.poll_rate) {
1412 uap->dmarx.last_jiffies = jiffies;
1413 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1414 mod_timer(&uap->dmarx.timer,
1415 jiffies +
1416 msecs_to_jiffies(uap->dmarx.poll_rate));
1417 }
1418#endif
1419 }
1420 }
1421 spin_lock(&uap->port.lock);
1422}
1423
1424static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1425 bool from_irq)
1426{
1427 if (unlikely(!from_irq) &&
1428 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1429 return false; /* unable to transmit character */
1430
1431 pl011_write(c, uap, REG_DR);
1432 uap->port.icount.tx++;
1433
1434 return true;
1435}
1436
1437static void pl011_rs485_tx_start(struct uart_amba_port *uap)
1438{
1439 struct uart_port *port = &uap->port;
1440 u32 cr;
1441
1442 /* Enable transmitter */
1443 cr = pl011_read(uap, REG_CR);
1444 cr |= UART011_CR_TXE;
1445
1446 /* Disable receiver if half-duplex */
1447 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
1448 cr &= ~UART011_CR_RXE;
1449
1450 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
1451 cr &= ~UART011_CR_RTS;
1452 else
1453 cr |= UART011_CR_RTS;
1454
1455 pl011_write(cr, uap, REG_CR);
1456
1457 if (port->rs485.delay_rts_before_send)
1458 mdelay(port->rs485.delay_rts_before_send);
1459
1460 uap->rs485_tx_started = true;
1461}
1462
1463/* Returns true if tx interrupts have to be (kept) enabled */
1464static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1465{
1466 struct circ_buf *xmit = &uap->port.state->xmit;
1467 int count = uap->fifosize >> 1;
1468
1469 if ((uap->port.rs485.flags & SER_RS485_ENABLED) &&
1470 !uap->rs485_tx_started)
1471 pl011_rs485_tx_start(uap);
1472
1473 if (uap->port.x_char) {
1474 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1475 return true;
1476 uap->port.x_char = 0;
1477 --count;
1478 }
1479 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1480 pl011_stop_tx(&uap->port);
1481 return false;
1482 }
1483
1484 /* If we are using DMA mode, try to send some characters. */
1485 if (pl011_dma_tx_irq(uap))
1486 return true;
1487
1488 do {
1489 if (likely(from_irq) && count-- == 0)
1490 break;
1491
1492 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1493 break;
1494
1495 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1496 } while (!uart_circ_empty(xmit));
1497
1498 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1499 uart_write_wakeup(&uap->port);
1500
1501 if (uart_circ_empty(xmit)) {
1502 pl011_stop_tx(&uap->port);
1503 return false;
1504 }
1505 return true;
1506}
1507
1508static void pl011_modem_status(struct uart_amba_port *uap)
1509{
1510 unsigned int status, delta;
1511
1512 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1513
1514 delta = status ^ uap->old_status;
1515 uap->old_status = status;
1516
1517 if (!delta)
1518 return;
1519
1520 if (delta & UART01x_FR_DCD)
1521 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1522
1523 if (delta & uap->vendor->fr_dsr)
1524 uap->port.icount.dsr++;
1525
1526 if (delta & uap->vendor->fr_cts)
1527 uart_handle_cts_change(&uap->port,
1528 status & uap->vendor->fr_cts);
1529
1530 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1531}
1532
1533static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1534{
1535 if (!uap->vendor->cts_event_workaround)
1536 return;
1537
1538 /* workaround to make sure that all bits are unlocked.. */
1539 pl011_write(0x00, uap, REG_ICR);
1540
1541 /*
1542 * WA: introduce 26ns(1 uart clk) delay before W1C;
1543 * single apb access will incur 2 pclk(133.12Mhz) delay,
1544 * so add 2 dummy reads
1545 */
1546 pl011_read(uap, REG_ICR);
1547 pl011_read(uap, REG_ICR);
1548}
1549
1550static irqreturn_t pl011_int(int irq, void *dev_id)
1551{
1552 struct uart_amba_port *uap = dev_id;
1553 unsigned long flags;
1554 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1555 int handled = 0;
1556
1557 spin_lock_irqsave(&uap->port.lock, flags);
1558 status = pl011_read(uap, REG_RIS) & uap->im;
1559 if (status) {
1560 do {
1561 check_apply_cts_event_workaround(uap);
1562
1563 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1564 UART011_RXIS),
1565 uap, REG_ICR);
1566
1567 if (status & (UART011_RTIS|UART011_RXIS)) {
1568 if (pl011_dma_rx_running(uap))
1569 pl011_dma_rx_irq(uap);
1570 else
1571 pl011_rx_chars(uap);
1572 }
1573 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1574 UART011_CTSMIS|UART011_RIMIS))
1575 pl011_modem_status(uap);
1576 if (status & UART011_TXIS)
1577 pl011_tx_chars(uap, true);
1578
1579 if (pass_counter-- == 0)
1580 break;
1581
1582 status = pl011_read(uap, REG_RIS) & uap->im;
1583 } while (status != 0);
1584 handled = 1;
1585 }
1586
1587 spin_unlock_irqrestore(&uap->port.lock, flags);
1588
1589 return IRQ_RETVAL(handled);
1590}
1591
1592static unsigned int pl011_tx_empty(struct uart_port *port)
1593{
1594 struct uart_amba_port *uap =
1595 container_of(port, struct uart_amba_port, port);
1596
1597 /* Allow feature register bits to be inverted to work around errata */
1598 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1599
1600 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1601 0 : TIOCSER_TEMT;
1602}
1603
1604static unsigned int pl011_get_mctrl(struct uart_port *port)
1605{
1606 struct uart_amba_port *uap =
1607 container_of(port, struct uart_amba_port, port);
1608 unsigned int result = 0;
1609 unsigned int status = pl011_read(uap, REG_FR);
1610
1611#define TIOCMBIT(uartbit, tiocmbit) \
1612 if (status & uartbit) \
1613 result |= tiocmbit
1614
1615 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1616 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1617 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1618 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1619#undef TIOCMBIT
1620 return result;
1621}
1622
1623static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1624{
1625 struct uart_amba_port *uap =
1626 container_of(port, struct uart_amba_port, port);
1627 unsigned int cr;
1628
1629 cr = pl011_read(uap, REG_CR);
1630
1631#define TIOCMBIT(tiocmbit, uartbit) \
1632 if (mctrl & tiocmbit) \
1633 cr |= uartbit; \
1634 else \
1635 cr &= ~uartbit
1636
1637 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1638 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1639 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1640 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1641 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1642
1643 if (port->status & UPSTAT_AUTORTS) {
1644 /* We need to disable auto-RTS if we want to turn RTS off */
1645 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1646 }
1647#undef TIOCMBIT
1648
1649 pl011_write(cr, uap, REG_CR);
1650}
1651
1652static void pl011_break_ctl(struct uart_port *port, int break_state)
1653{
1654 struct uart_amba_port *uap =
1655 container_of(port, struct uart_amba_port, port);
1656 unsigned long flags;
1657 unsigned int lcr_h;
1658
1659 spin_lock_irqsave(&uap->port.lock, flags);
1660 lcr_h = pl011_read(uap, REG_LCRH_TX);
1661 if (break_state == -1)
1662 lcr_h |= UART01x_LCRH_BRK;
1663 else
1664 lcr_h &= ~UART01x_LCRH_BRK;
1665 pl011_write(lcr_h, uap, REG_LCRH_TX);
1666 spin_unlock_irqrestore(&uap->port.lock, flags);
1667}
1668
1669#ifdef CONFIG_CONSOLE_POLL
1670
1671static void pl011_quiesce_irqs(struct uart_port *port)
1672{
1673 struct uart_amba_port *uap =
1674 container_of(port, struct uart_amba_port, port);
1675
1676 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1677 /*
1678 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1679 * we simply mask it. start_tx() will unmask it.
1680 *
1681 * Note we can race with start_tx(), and if the race happens, the
1682 * polling user might get another interrupt just after we clear it.
1683 * But it should be OK and can happen even w/o the race, e.g.
1684 * controller immediately got some new data and raised the IRQ.
1685 *
1686 * And whoever uses polling routines assumes that it manages the device
1687 * (including tx queue), so we're also fine with start_tx()'s caller
1688 * side.
1689 */
1690 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1691 REG_IMSC);
1692}
1693
1694static int pl011_get_poll_char(struct uart_port *port)
1695{
1696 struct uart_amba_port *uap =
1697 container_of(port, struct uart_amba_port, port);
1698 unsigned int status;
1699
1700 /*
1701 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1702 * debugger.
1703 */
1704 pl011_quiesce_irqs(port);
1705
1706 status = pl011_read(uap, REG_FR);
1707 if (status & UART01x_FR_RXFE)
1708 return NO_POLL_CHAR;
1709
1710 return pl011_read(uap, REG_DR);
1711}
1712
1713static void pl011_put_poll_char(struct uart_port *port,
1714 unsigned char ch)
1715{
1716 struct uart_amba_port *uap =
1717 container_of(port, struct uart_amba_port, port);
1718
1719 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1720 cpu_relax();
1721
1722 pl011_write(ch, uap, REG_DR);
1723}
1724
1725#endif /* CONFIG_CONSOLE_POLL */
1726
1727static int pl011_hwinit(struct uart_port *port)
1728{
1729 struct uart_amba_port *uap =
1730 container_of(port, struct uart_amba_port, port);
1731 int retval;
1732
1733 /* Optionaly enable pins to be muxed in and configured */
1734 pinctrl_pm_select_default_state(port->dev);
1735
1736 /*
1737 * Try to enable the clock producer.
1738 */
1739 retval = clk_prepare_enable(uap->clk);
1740 if (retval)
1741 return retval;
1742
1743 uap->port.uartclk = clk_get_rate(uap->clk);
1744
1745 /* Clear pending error and receive interrupts */
1746 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1747 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1748 uap, REG_ICR);
1749
1750 /*
1751 * Save interrupts enable mask, and enable RX interrupts in case if
1752 * the interrupt is used for NMI entry.
1753 */
1754 uap->im = pl011_read(uap, REG_IMSC);
1755 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1756
1757 if (dev_get_platdata(uap->port.dev)) {
1758 struct amba_pl011_data *plat;
1759
1760 plat = dev_get_platdata(uap->port.dev);
1761 if (plat->init)
1762 plat->init();
1763 }
1764 return 0;
1765}
1766
1767static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1768{
1769 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1770 pl011_reg_to_offset(uap, REG_LCRH_TX);
1771}
1772
1773static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1774{
1775 pl011_write(lcr_h, uap, REG_LCRH_RX);
1776 if (pl011_split_lcrh(uap)) {
1777 int i;
1778 /*
1779 * Wait 10 PCLKs before writing LCRH_TX register,
1780 * to get this delay write read only register 10 times
1781 */
1782 for (i = 0; i < 10; ++i)
1783 pl011_write(0xff, uap, REG_MIS);
1784 pl011_write(lcr_h, uap, REG_LCRH_TX);
1785 }
1786}
1787
1788static int pl011_allocate_irq(struct uart_amba_port *uap)
1789{
1790 pl011_write(uap->im, uap, REG_IMSC);
1791
1792 return request_irq(uap->port.irq, pl011_int, IRQF_SHARED, "uart-pl011", uap);
1793}
1794
1795/*
1796 * Enable interrupts, only timeouts when using DMA
1797 * if initial RX DMA job failed, start in interrupt mode
1798 * as well.
1799 */
1800static void pl011_enable_interrupts(struct uart_amba_port *uap)
1801{
1802 unsigned long flags;
1803 unsigned int i;
1804
1805 spin_lock_irqsave(&uap->port.lock, flags);
1806
1807 /* Clear out any spuriously appearing RX interrupts */
1808 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1809
1810 /*
1811 * RXIS is asserted only when the RX FIFO transitions from below
1812 * to above the trigger threshold. If the RX FIFO is already
1813 * full to the threshold this can't happen and RXIS will now be
1814 * stuck off. Drain the RX FIFO explicitly to fix this:
1815 */
1816 for (i = 0; i < uap->fifosize * 2; ++i) {
1817 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1818 break;
1819
1820 pl011_read(uap, REG_DR);
1821 }
1822
1823 uap->im = UART011_RTIM;
1824 if (!pl011_dma_rx_running(uap))
1825 uap->im |= UART011_RXIM;
1826 pl011_write(uap->im, uap, REG_IMSC);
1827 spin_unlock_irqrestore(&uap->port.lock, flags);
1828}
1829
1830static void pl011_unthrottle_rx(struct uart_port *port)
1831{
1832 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1833 unsigned long flags;
1834
1835 spin_lock_irqsave(&uap->port.lock, flags);
1836
1837 uap->im = UART011_RTIM;
1838 if (!pl011_dma_rx_running(uap))
1839 uap->im |= UART011_RXIM;
1840
1841 pl011_write(uap->im, uap, REG_IMSC);
1842
1843 spin_unlock_irqrestore(&uap->port.lock, flags);
1844}
1845
1846static int pl011_startup(struct uart_port *port)
1847{
1848 struct uart_amba_port *uap =
1849 container_of(port, struct uart_amba_port, port);
1850 unsigned int cr;
1851 int retval;
1852
1853 retval = pl011_hwinit(port);
1854 if (retval)
1855 goto clk_dis;
1856
1857 retval = pl011_allocate_irq(uap);
1858 if (retval)
1859 goto clk_dis;
1860
1861 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1862
1863 spin_lock_irq(&uap->port.lock);
1864
1865 cr = pl011_read(uap, REG_CR);
1866 cr &= UART011_CR_RTS | UART011_CR_DTR;
1867 cr |= UART01x_CR_UARTEN | UART011_CR_RXE;
1868
1869 if (!(port->rs485.flags & SER_RS485_ENABLED))
1870 cr |= UART011_CR_TXE;
1871
1872 pl011_write(cr, uap, REG_CR);
1873
1874 spin_unlock_irq(&uap->port.lock);
1875
1876 /*
1877 * initialise the old status of the modem signals
1878 */
1879 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1880
1881 /* Startup DMA */
1882 pl011_dma_startup(uap);
1883
1884 pl011_enable_interrupts(uap);
1885
1886 return 0;
1887
1888 clk_dis:
1889 clk_disable_unprepare(uap->clk);
1890 return retval;
1891}
1892
1893static int sbsa_uart_startup(struct uart_port *port)
1894{
1895 struct uart_amba_port *uap =
1896 container_of(port, struct uart_amba_port, port);
1897 int retval;
1898
1899 retval = pl011_hwinit(port);
1900 if (retval)
1901 return retval;
1902
1903 retval = pl011_allocate_irq(uap);
1904 if (retval)
1905 return retval;
1906
1907 /* The SBSA UART does not support any modem status lines. */
1908 uap->old_status = 0;
1909
1910 pl011_enable_interrupts(uap);
1911
1912 return 0;
1913}
1914
1915static void pl011_shutdown_channel(struct uart_amba_port *uap,
1916 unsigned int lcrh)
1917{
1918 unsigned long val;
1919
1920 val = pl011_read(uap, lcrh);
1921 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1922 pl011_write(val, uap, lcrh);
1923}
1924
1925/*
1926 * disable the port. It should not disable RTS and DTR.
1927 * Also RTS and DTR state should be preserved to restore
1928 * it during startup().
1929 */
1930static void pl011_disable_uart(struct uart_amba_port *uap)
1931{
1932 unsigned int cr;
1933
1934 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1935 spin_lock_irq(&uap->port.lock);
1936 cr = pl011_read(uap, REG_CR);
1937 cr &= UART011_CR_RTS | UART011_CR_DTR;
1938 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1939 pl011_write(cr, uap, REG_CR);
1940 spin_unlock_irq(&uap->port.lock);
1941
1942 /*
1943 * disable break condition and fifos
1944 */
1945 pl011_shutdown_channel(uap, REG_LCRH_RX);
1946 if (pl011_split_lcrh(uap))
1947 pl011_shutdown_channel(uap, REG_LCRH_TX);
1948}
1949
1950static void pl011_disable_interrupts(struct uart_amba_port *uap)
1951{
1952 spin_lock_irq(&uap->port.lock);
1953
1954 /* mask all interrupts and clear all pending ones */
1955 uap->im = 0;
1956 pl011_write(uap->im, uap, REG_IMSC);
1957 pl011_write(0xffff, uap, REG_ICR);
1958
1959 spin_unlock_irq(&uap->port.lock);
1960}
1961
1962static void pl011_shutdown(struct uart_port *port)
1963{
1964 struct uart_amba_port *uap =
1965 container_of(port, struct uart_amba_port, port);
1966
1967 pl011_disable_interrupts(uap);
1968
1969 pl011_dma_shutdown(uap);
1970
1971 if ((port->rs485.flags & SER_RS485_ENABLED) && uap->rs485_tx_started)
1972 pl011_rs485_tx_stop(uap);
1973
1974 free_irq(uap->port.irq, uap);
1975
1976 pl011_disable_uart(uap);
1977
1978 /*
1979 * Shut down the clock producer
1980 */
1981 clk_disable_unprepare(uap->clk);
1982 /* Optionally let pins go into sleep states */
1983 pinctrl_pm_select_sleep_state(port->dev);
1984
1985 if (dev_get_platdata(uap->port.dev)) {
1986 struct amba_pl011_data *plat;
1987
1988 plat = dev_get_platdata(uap->port.dev);
1989 if (plat->exit)
1990 plat->exit();
1991 }
1992
1993 if (uap->port.ops->flush_buffer)
1994 uap->port.ops->flush_buffer(port);
1995}
1996
1997static void sbsa_uart_shutdown(struct uart_port *port)
1998{
1999 struct uart_amba_port *uap =
2000 container_of(port, struct uart_amba_port, port);
2001
2002 pl011_disable_interrupts(uap);
2003
2004 free_irq(uap->port.irq, uap);
2005
2006 if (uap->port.ops->flush_buffer)
2007 uap->port.ops->flush_buffer(port);
2008}
2009
2010static void
2011pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
2012{
2013 port->read_status_mask = UART011_DR_OE | 255;
2014 if (termios->c_iflag & INPCK)
2015 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
2016 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2017 port->read_status_mask |= UART011_DR_BE;
2018
2019 /*
2020 * Characters to ignore
2021 */
2022 port->ignore_status_mask = 0;
2023 if (termios->c_iflag & IGNPAR)
2024 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
2025 if (termios->c_iflag & IGNBRK) {
2026 port->ignore_status_mask |= UART011_DR_BE;
2027 /*
2028 * If we're ignoring parity and break indicators,
2029 * ignore overruns too (for real raw support).
2030 */
2031 if (termios->c_iflag & IGNPAR)
2032 port->ignore_status_mask |= UART011_DR_OE;
2033 }
2034
2035 /*
2036 * Ignore all characters if CREAD is not set.
2037 */
2038 if ((termios->c_cflag & CREAD) == 0)
2039 port->ignore_status_mask |= UART_DUMMY_DR_RX;
2040}
2041
2042static void
2043pl011_set_termios(struct uart_port *port, struct ktermios *termios,
2044 const struct ktermios *old)
2045{
2046 struct uart_amba_port *uap =
2047 container_of(port, struct uart_amba_port, port);
2048 unsigned int lcr_h, old_cr;
2049 unsigned long flags;
2050 unsigned int baud, quot, clkdiv;
2051 unsigned int bits;
2052
2053 if (uap->vendor->oversampling)
2054 clkdiv = 8;
2055 else
2056 clkdiv = 16;
2057
2058 /*
2059 * Ask the core to calculate the divisor for us.
2060 */
2061 baud = uart_get_baud_rate(port, termios, old, 0,
2062 port->uartclk / clkdiv);
2063#ifdef CONFIG_DMA_ENGINE
2064 /*
2065 * Adjust RX DMA polling rate with baud rate if not specified.
2066 */
2067 if (uap->dmarx.auto_poll_rate)
2068 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2069#endif
2070
2071 if (baud > port->uartclk/16)
2072 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
2073 else
2074 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
2075
2076 switch (termios->c_cflag & CSIZE) {
2077 case CS5:
2078 lcr_h = UART01x_LCRH_WLEN_5;
2079 break;
2080 case CS6:
2081 lcr_h = UART01x_LCRH_WLEN_6;
2082 break;
2083 case CS7:
2084 lcr_h = UART01x_LCRH_WLEN_7;
2085 break;
2086 default: // CS8
2087 lcr_h = UART01x_LCRH_WLEN_8;
2088 break;
2089 }
2090 if (termios->c_cflag & CSTOPB)
2091 lcr_h |= UART01x_LCRH_STP2;
2092 if (termios->c_cflag & PARENB) {
2093 lcr_h |= UART01x_LCRH_PEN;
2094 if (!(termios->c_cflag & PARODD))
2095 lcr_h |= UART01x_LCRH_EPS;
2096 if (termios->c_cflag & CMSPAR)
2097 lcr_h |= UART011_LCRH_SPS;
2098 }
2099 if (uap->fifosize > 1)
2100 lcr_h |= UART01x_LCRH_FEN;
2101
2102 bits = tty_get_frame_size(termios->c_cflag);
2103
2104 spin_lock_irqsave(&port->lock, flags);
2105
2106 /*
2107 * Update the per-port timeout.
2108 */
2109 uart_update_timeout(port, termios->c_cflag, baud);
2110
2111 /*
2112 * Calculate the approximated time it takes to transmit one character
2113 * with the given baud rate. We use this as the poll interval when we
2114 * wait for the tx queue to empty.
2115 */
2116 uap->rs485_tx_drain_interval = DIV_ROUND_UP(bits * 1000 * 1000, baud);
2117
2118 pl011_setup_status_masks(port, termios);
2119
2120 if (UART_ENABLE_MS(port, termios->c_cflag))
2121 pl011_enable_ms(port);
2122
2123 if (port->rs485.flags & SER_RS485_ENABLED)
2124 termios->c_cflag &= ~CRTSCTS;
2125
2126 old_cr = pl011_read(uap, REG_CR);
2127
2128 if (termios->c_cflag & CRTSCTS) {
2129 if (old_cr & UART011_CR_RTS)
2130 old_cr |= UART011_CR_RTSEN;
2131
2132 old_cr |= UART011_CR_CTSEN;
2133 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2134 } else {
2135 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2136 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2137 }
2138
2139 if (uap->vendor->oversampling) {
2140 if (baud > port->uartclk / 16)
2141 old_cr |= ST_UART011_CR_OVSFACT;
2142 else
2143 old_cr &= ~ST_UART011_CR_OVSFACT;
2144 }
2145
2146 /*
2147 * Workaround for the ST Micro oversampling variants to
2148 * increase the bitrate slightly, by lowering the divisor,
2149 * to avoid delayed sampling of start bit at high speeds,
2150 * else we see data corruption.
2151 */
2152 if (uap->vendor->oversampling) {
2153 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2154 quot -= 1;
2155 else if ((baud > 3250000) && (quot > 2))
2156 quot -= 2;
2157 }
2158 /* Set baud rate */
2159 pl011_write(quot & 0x3f, uap, REG_FBRD);
2160 pl011_write(quot >> 6, uap, REG_IBRD);
2161
2162 /*
2163 * ----------v----------v----------v----------v-----
2164 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2165 * REG_FBRD & REG_IBRD.
2166 * ----------^----------^----------^----------^-----
2167 */
2168 pl011_write_lcr_h(uap, lcr_h);
2169 pl011_write(old_cr, uap, REG_CR);
2170
2171 spin_unlock_irqrestore(&port->lock, flags);
2172}
2173
2174static void
2175sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2176 const struct ktermios *old)
2177{
2178 struct uart_amba_port *uap =
2179 container_of(port, struct uart_amba_port, port);
2180 unsigned long flags;
2181
2182 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2183
2184 /* The SBSA UART only supports 8n1 without hardware flow control. */
2185 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2186 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2187 termios->c_cflag |= CS8 | CLOCAL;
2188
2189 spin_lock_irqsave(&port->lock, flags);
2190 uart_update_timeout(port, CS8, uap->fixed_baud);
2191 pl011_setup_status_masks(port, termios);
2192 spin_unlock_irqrestore(&port->lock, flags);
2193}
2194
2195static const char *pl011_type(struct uart_port *port)
2196{
2197 struct uart_amba_port *uap =
2198 container_of(port, struct uart_amba_port, port);
2199 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2200}
2201
2202/*
2203 * Configure/autoconfigure the port.
2204 */
2205static void pl011_config_port(struct uart_port *port, int flags)
2206{
2207 if (flags & UART_CONFIG_TYPE)
2208 port->type = PORT_AMBA;
2209}
2210
2211/*
2212 * verify the new serial_struct (for TIOCSSERIAL).
2213 */
2214static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2215{
2216 int ret = 0;
2217 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2218 ret = -EINVAL;
2219 if (ser->irq < 0 || ser->irq >= nr_irqs)
2220 ret = -EINVAL;
2221 if (ser->baud_base < 9600)
2222 ret = -EINVAL;
2223 if (port->mapbase != (unsigned long) ser->iomem_base)
2224 ret = -EINVAL;
2225 return ret;
2226}
2227
2228static int pl011_rs485_config(struct uart_port *port, struct ktermios *termios,
2229 struct serial_rs485 *rs485)
2230{
2231 struct uart_amba_port *uap =
2232 container_of(port, struct uart_amba_port, port);
2233
2234 if (port->rs485.flags & SER_RS485_ENABLED)
2235 pl011_rs485_tx_stop(uap);
2236
2237 /* Make sure auto RTS is disabled */
2238 if (rs485->flags & SER_RS485_ENABLED) {
2239 u32 cr = pl011_read(uap, REG_CR);
2240
2241 cr &= ~UART011_CR_RTSEN;
2242 pl011_write(cr, uap, REG_CR);
2243 port->status &= ~UPSTAT_AUTORTS;
2244 }
2245
2246 return 0;
2247}
2248
2249static const struct uart_ops amba_pl011_pops = {
2250 .tx_empty = pl011_tx_empty,
2251 .set_mctrl = pl011_set_mctrl,
2252 .get_mctrl = pl011_get_mctrl,
2253 .stop_tx = pl011_stop_tx,
2254 .start_tx = pl011_start_tx,
2255 .stop_rx = pl011_stop_rx,
2256 .throttle = pl011_throttle_rx,
2257 .unthrottle = pl011_unthrottle_rx,
2258 .enable_ms = pl011_enable_ms,
2259 .break_ctl = pl011_break_ctl,
2260 .startup = pl011_startup,
2261 .shutdown = pl011_shutdown,
2262 .flush_buffer = pl011_dma_flush_buffer,
2263 .set_termios = pl011_set_termios,
2264 .type = pl011_type,
2265 .config_port = pl011_config_port,
2266 .verify_port = pl011_verify_port,
2267#ifdef CONFIG_CONSOLE_POLL
2268 .poll_init = pl011_hwinit,
2269 .poll_get_char = pl011_get_poll_char,
2270 .poll_put_char = pl011_put_poll_char,
2271#endif
2272};
2273
2274static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2275{
2276}
2277
2278static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2279{
2280 return 0;
2281}
2282
2283static const struct uart_ops sbsa_uart_pops = {
2284 .tx_empty = pl011_tx_empty,
2285 .set_mctrl = sbsa_uart_set_mctrl,
2286 .get_mctrl = sbsa_uart_get_mctrl,
2287 .stop_tx = pl011_stop_tx,
2288 .start_tx = pl011_start_tx,
2289 .stop_rx = pl011_stop_rx,
2290 .startup = sbsa_uart_startup,
2291 .shutdown = sbsa_uart_shutdown,
2292 .set_termios = sbsa_uart_set_termios,
2293 .type = pl011_type,
2294 .config_port = pl011_config_port,
2295 .verify_port = pl011_verify_port,
2296#ifdef CONFIG_CONSOLE_POLL
2297 .poll_init = pl011_hwinit,
2298 .poll_get_char = pl011_get_poll_char,
2299 .poll_put_char = pl011_put_poll_char,
2300#endif
2301};
2302
2303static struct uart_amba_port *amba_ports[UART_NR];
2304
2305#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2306
2307static void pl011_console_putchar(struct uart_port *port, unsigned char ch)
2308{
2309 struct uart_amba_port *uap =
2310 container_of(port, struct uart_amba_port, port);
2311
2312 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2313 cpu_relax();
2314 pl011_write(ch, uap, REG_DR);
2315}
2316
2317static void
2318pl011_console_write(struct console *co, const char *s, unsigned int count)
2319{
2320 struct uart_amba_port *uap = amba_ports[co->index];
2321 unsigned int old_cr = 0, new_cr;
2322 unsigned long flags;
2323 int locked = 1;
2324
2325 clk_enable(uap->clk);
2326
2327 local_irq_save(flags);
2328 if (uap->port.sysrq)
2329 locked = 0;
2330 else if (oops_in_progress)
2331 locked = spin_trylock(&uap->port.lock);
2332 else
2333 spin_lock(&uap->port.lock);
2334
2335 /*
2336 * First save the CR then disable the interrupts
2337 */
2338 if (!uap->vendor->always_enabled) {
2339 old_cr = pl011_read(uap, REG_CR);
2340 new_cr = old_cr & ~UART011_CR_CTSEN;
2341 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2342 pl011_write(new_cr, uap, REG_CR);
2343 }
2344
2345 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2346
2347 /*
2348 * Finally, wait for transmitter to become empty and restore the
2349 * TCR. Allow feature register bits to be inverted to work around
2350 * errata.
2351 */
2352 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2353 & uap->vendor->fr_busy)
2354 cpu_relax();
2355 if (!uap->vendor->always_enabled)
2356 pl011_write(old_cr, uap, REG_CR);
2357
2358 if (locked)
2359 spin_unlock(&uap->port.lock);
2360 local_irq_restore(flags);
2361
2362 clk_disable(uap->clk);
2363}
2364
2365static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2366 int *parity, int *bits)
2367{
2368 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2369 unsigned int lcr_h, ibrd, fbrd;
2370
2371 lcr_h = pl011_read(uap, REG_LCRH_TX);
2372
2373 *parity = 'n';
2374 if (lcr_h & UART01x_LCRH_PEN) {
2375 if (lcr_h & UART01x_LCRH_EPS)
2376 *parity = 'e';
2377 else
2378 *parity = 'o';
2379 }
2380
2381 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2382 *bits = 7;
2383 else
2384 *bits = 8;
2385
2386 ibrd = pl011_read(uap, REG_IBRD);
2387 fbrd = pl011_read(uap, REG_FBRD);
2388
2389 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2390
2391 if (uap->vendor->oversampling) {
2392 if (pl011_read(uap, REG_CR)
2393 & ST_UART011_CR_OVSFACT)
2394 *baud *= 2;
2395 }
2396 }
2397}
2398
2399static int pl011_console_setup(struct console *co, char *options)
2400{
2401 struct uart_amba_port *uap;
2402 int baud = 38400;
2403 int bits = 8;
2404 int parity = 'n';
2405 int flow = 'n';
2406 int ret;
2407
2408 /*
2409 * Check whether an invalid uart number has been specified, and
2410 * if so, search for the first available port that does have
2411 * console support.
2412 */
2413 if (co->index >= UART_NR)
2414 co->index = 0;
2415 uap = amba_ports[co->index];
2416 if (!uap)
2417 return -ENODEV;
2418
2419 /* Allow pins to be muxed in and configured */
2420 pinctrl_pm_select_default_state(uap->port.dev);
2421
2422 ret = clk_prepare(uap->clk);
2423 if (ret)
2424 return ret;
2425
2426 if (dev_get_platdata(uap->port.dev)) {
2427 struct amba_pl011_data *plat;
2428
2429 plat = dev_get_platdata(uap->port.dev);
2430 if (plat->init)
2431 plat->init();
2432 }
2433
2434 uap->port.uartclk = clk_get_rate(uap->clk);
2435
2436 if (uap->vendor->fixed_options) {
2437 baud = uap->fixed_baud;
2438 } else {
2439 if (options)
2440 uart_parse_options(options,
2441 &baud, &parity, &bits, &flow);
2442 else
2443 pl011_console_get_options(uap, &baud, &parity, &bits);
2444 }
2445
2446 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2447}
2448
2449/**
2450 * pl011_console_match - non-standard console matching
2451 * @co: registering console
2452 * @name: name from console command line
2453 * @idx: index from console command line
2454 * @options: ptr to option string from console command line
2455 *
2456 * Only attempts to match console command lines of the form:
2457 * console=pl011,mmio|mmio32,<addr>[,<options>]
2458 * console=pl011,0x<addr>[,<options>]
2459 * This form is used to register an initial earlycon boot console and
2460 * replace it with the amba_console at pl011 driver init.
2461 *
2462 * Performs console setup for a match (as required by interface)
2463 * If no <options> are specified, then assume the h/w is already setup.
2464 *
2465 * Returns 0 if console matches; otherwise non-zero to use default matching
2466 */
2467static int pl011_console_match(struct console *co, char *name, int idx,
2468 char *options)
2469{
2470 unsigned char iotype;
2471 resource_size_t addr;
2472 int i;
2473
2474 /*
2475 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2476 * have a distinct console name, so make sure we check for that.
2477 * The actual implementation of the erratum occurs in the probe
2478 * function.
2479 */
2480 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2481 return -ENODEV;
2482
2483 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2484 return -ENODEV;
2485
2486 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2487 return -ENODEV;
2488
2489 /* try to match the port specified on the command line */
2490 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2491 struct uart_port *port;
2492
2493 if (!amba_ports[i])
2494 continue;
2495
2496 port = &amba_ports[i]->port;
2497
2498 if (port->mapbase != addr)
2499 continue;
2500
2501 co->index = i;
2502 port->cons = co;
2503 return pl011_console_setup(co, options);
2504 }
2505
2506 return -ENODEV;
2507}
2508
2509static struct uart_driver amba_reg;
2510static struct console amba_console = {
2511 .name = "ttyAMA",
2512 .write = pl011_console_write,
2513 .device = uart_console_device,
2514 .setup = pl011_console_setup,
2515 .match = pl011_console_match,
2516 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2517 .index = -1,
2518 .data = &amba_reg,
2519};
2520
2521#define AMBA_CONSOLE (&amba_console)
2522
2523static void qdf2400_e44_putc(struct uart_port *port, unsigned char c)
2524{
2525 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2526 cpu_relax();
2527 writel(c, port->membase + UART01x_DR);
2528 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2529 cpu_relax();
2530}
2531
2532static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2533{
2534 struct earlycon_device *dev = con->data;
2535
2536 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2537}
2538
2539static void pl011_putc(struct uart_port *port, unsigned char c)
2540{
2541 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2542 cpu_relax();
2543 if (port->iotype == UPIO_MEM32)
2544 writel(c, port->membase + UART01x_DR);
2545 else
2546 writeb(c, port->membase + UART01x_DR);
2547 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2548 cpu_relax();
2549}
2550
2551static void pl011_early_write(struct console *con, const char *s, unsigned n)
2552{
2553 struct earlycon_device *dev = con->data;
2554
2555 uart_console_write(&dev->port, s, n, pl011_putc);
2556}
2557
2558#ifdef CONFIG_CONSOLE_POLL
2559static int pl011_getc(struct uart_port *port)
2560{
2561 if (readl(port->membase + UART01x_FR) & UART01x_FR_RXFE)
2562 return NO_POLL_CHAR;
2563
2564 if (port->iotype == UPIO_MEM32)
2565 return readl(port->membase + UART01x_DR);
2566 else
2567 return readb(port->membase + UART01x_DR);
2568}
2569
2570static int pl011_early_read(struct console *con, char *s, unsigned int n)
2571{
2572 struct earlycon_device *dev = con->data;
2573 int ch, num_read = 0;
2574
2575 while (num_read < n) {
2576 ch = pl011_getc(&dev->port);
2577 if (ch == NO_POLL_CHAR)
2578 break;
2579
2580 s[num_read++] = ch;
2581 }
2582
2583 return num_read;
2584}
2585#else
2586#define pl011_early_read NULL
2587#endif
2588
2589/*
2590 * On non-ACPI systems, earlycon is enabled by specifying
2591 * "earlycon=pl011,<address>" on the kernel command line.
2592 *
2593 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2594 * by specifying only "earlycon" on the command line. Because it requires
2595 * SPCR, the console starts after ACPI is parsed, which is later than a
2596 * traditional early console.
2597 *
2598 * To get the traditional early console that starts before ACPI is parsed,
2599 * specify the full "earlycon=pl011,<address>" option.
2600 */
2601static int __init pl011_early_console_setup(struct earlycon_device *device,
2602 const char *opt)
2603{
2604 if (!device->port.membase)
2605 return -ENODEV;
2606
2607 device->con->write = pl011_early_write;
2608 device->con->read = pl011_early_read;
2609
2610 return 0;
2611}
2612OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2613OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2614
2615/*
2616 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2617 * Erratum 44, traditional earlycon can be enabled by specifying
2618 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2619 *
2620 * Alternatively, you can just specify "earlycon", and the early console
2621 * will be enabled with the information from the SPCR table. In this
2622 * case, the SPCR code will detect the need for the E44 work-around,
2623 * and set the console name to "qdf2400_e44".
2624 */
2625static int __init
2626qdf2400_e44_early_console_setup(struct earlycon_device *device,
2627 const char *opt)
2628{
2629 if (!device->port.membase)
2630 return -ENODEV;
2631
2632 device->con->write = qdf2400_e44_early_write;
2633 return 0;
2634}
2635EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2636
2637#else
2638#define AMBA_CONSOLE NULL
2639#endif
2640
2641static struct uart_driver amba_reg = {
2642 .owner = THIS_MODULE,
2643 .driver_name = "ttyAMA",
2644 .dev_name = "ttyAMA",
2645 .major = SERIAL_AMBA_MAJOR,
2646 .minor = SERIAL_AMBA_MINOR,
2647 .nr = UART_NR,
2648 .cons = AMBA_CONSOLE,
2649};
2650
2651static int pl011_probe_dt_alias(int index, struct device *dev)
2652{
2653 struct device_node *np;
2654 static bool seen_dev_with_alias = false;
2655 static bool seen_dev_without_alias = false;
2656 int ret = index;
2657
2658 if (!IS_ENABLED(CONFIG_OF))
2659 return ret;
2660
2661 np = dev->of_node;
2662 if (!np)
2663 return ret;
2664
2665 ret = of_alias_get_id(np, "serial");
2666 if (ret < 0) {
2667 seen_dev_without_alias = true;
2668 ret = index;
2669 } else {
2670 seen_dev_with_alias = true;
2671 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2672 dev_warn(dev, "requested serial port %d not available.\n", ret);
2673 ret = index;
2674 }
2675 }
2676
2677 if (seen_dev_with_alias && seen_dev_without_alias)
2678 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2679
2680 return ret;
2681}
2682
2683/* unregisters the driver also if no more ports are left */
2684static void pl011_unregister_port(struct uart_amba_port *uap)
2685{
2686 int i;
2687 bool busy = false;
2688
2689 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2690 if (amba_ports[i] == uap)
2691 amba_ports[i] = NULL;
2692 else if (amba_ports[i])
2693 busy = true;
2694 }
2695 pl011_dma_remove(uap);
2696 if (!busy)
2697 uart_unregister_driver(&amba_reg);
2698}
2699
2700static int pl011_find_free_port(void)
2701{
2702 int i;
2703
2704 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2705 if (amba_ports[i] == NULL)
2706 return i;
2707
2708 return -EBUSY;
2709}
2710
2711static int pl011_get_rs485_mode(struct uart_amba_port *uap)
2712{
2713 struct uart_port *port = &uap->port;
2714 int ret;
2715
2716 ret = uart_get_rs485_mode(port);
2717 if (ret)
2718 return ret;
2719
2720 return 0;
2721}
2722
2723static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2724 struct resource *mmiobase, int index)
2725{
2726 void __iomem *base;
2727 int ret;
2728
2729 base = devm_ioremap_resource(dev, mmiobase);
2730 if (IS_ERR(base))
2731 return PTR_ERR(base);
2732
2733 index = pl011_probe_dt_alias(index, dev);
2734
2735 uap->port.dev = dev;
2736 uap->port.mapbase = mmiobase->start;
2737 uap->port.membase = base;
2738 uap->port.fifosize = uap->fifosize;
2739 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_AMBA_PL011_CONSOLE);
2740 uap->port.flags = UPF_BOOT_AUTOCONF;
2741 uap->port.line = index;
2742
2743 ret = pl011_get_rs485_mode(uap);
2744 if (ret)
2745 return ret;
2746
2747 amba_ports[index] = uap;
2748
2749 return 0;
2750}
2751
2752static int pl011_register_port(struct uart_amba_port *uap)
2753{
2754 int ret, i;
2755
2756 /* Ensure interrupts from this UART are masked and cleared */
2757 pl011_write(0, uap, REG_IMSC);
2758 pl011_write(0xffff, uap, REG_ICR);
2759
2760 if (!amba_reg.state) {
2761 ret = uart_register_driver(&amba_reg);
2762 if (ret < 0) {
2763 dev_err(uap->port.dev,
2764 "Failed to register AMBA-PL011 driver\n");
2765 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2766 if (amba_ports[i] == uap)
2767 amba_ports[i] = NULL;
2768 return ret;
2769 }
2770 }
2771
2772 ret = uart_add_one_port(&amba_reg, &uap->port);
2773 if (ret)
2774 pl011_unregister_port(uap);
2775
2776 return ret;
2777}
2778
2779static const struct serial_rs485 pl011_rs485_supported = {
2780 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2781 SER_RS485_RX_DURING_TX,
2782 .delay_rts_before_send = 1,
2783 .delay_rts_after_send = 1,
2784};
2785
2786static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2787{
2788 struct uart_amba_port *uap;
2789 struct vendor_data *vendor = id->data;
2790 int portnr, ret;
2791 u32 val;
2792
2793 portnr = pl011_find_free_port();
2794 if (portnr < 0)
2795 return portnr;
2796
2797 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2798 GFP_KERNEL);
2799 if (!uap)
2800 return -ENOMEM;
2801
2802 uap->clk = devm_clk_get(&dev->dev, NULL);
2803 if (IS_ERR(uap->clk))
2804 return PTR_ERR(uap->clk);
2805
2806 uap->reg_offset = vendor->reg_offset;
2807 uap->vendor = vendor;
2808 uap->fifosize = vendor->get_fifosize(dev);
2809 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2810 uap->port.irq = dev->irq[0];
2811 uap->port.ops = &amba_pl011_pops;
2812 uap->port.rs485_config = pl011_rs485_config;
2813 uap->port.rs485_supported = pl011_rs485_supported;
2814 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2815
2816 if (device_property_read_u32(&dev->dev, "reg-io-width", &val) == 0) {
2817 switch (val) {
2818 case 1:
2819 uap->port.iotype = UPIO_MEM;
2820 break;
2821 case 4:
2822 uap->port.iotype = UPIO_MEM32;
2823 break;
2824 default:
2825 dev_warn(&dev->dev, "unsupported reg-io-width (%d)\n",
2826 val);
2827 return -EINVAL;
2828 }
2829 }
2830
2831 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2832 if (ret)
2833 return ret;
2834
2835 amba_set_drvdata(dev, uap);
2836
2837 return pl011_register_port(uap);
2838}
2839
2840static void pl011_remove(struct amba_device *dev)
2841{
2842 struct uart_amba_port *uap = amba_get_drvdata(dev);
2843
2844 uart_remove_one_port(&amba_reg, &uap->port);
2845 pl011_unregister_port(uap);
2846}
2847
2848#ifdef CONFIG_PM_SLEEP
2849static int pl011_suspend(struct device *dev)
2850{
2851 struct uart_amba_port *uap = dev_get_drvdata(dev);
2852
2853 if (!uap)
2854 return -EINVAL;
2855
2856 return uart_suspend_port(&amba_reg, &uap->port);
2857}
2858
2859static int pl011_resume(struct device *dev)
2860{
2861 struct uart_amba_port *uap = dev_get_drvdata(dev);
2862
2863 if (!uap)
2864 return -EINVAL;
2865
2866 return uart_resume_port(&amba_reg, &uap->port);
2867}
2868#endif
2869
2870static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2871
2872static int sbsa_uart_probe(struct platform_device *pdev)
2873{
2874 struct uart_amba_port *uap;
2875 struct resource *r;
2876 int portnr, ret;
2877 int baudrate;
2878
2879 /*
2880 * Check the mandatory baud rate parameter in the DT node early
2881 * so that we can easily exit with the error.
2882 */
2883 if (pdev->dev.of_node) {
2884 struct device_node *np = pdev->dev.of_node;
2885
2886 ret = of_property_read_u32(np, "current-speed", &baudrate);
2887 if (ret)
2888 return ret;
2889 } else {
2890 baudrate = 115200;
2891 }
2892
2893 portnr = pl011_find_free_port();
2894 if (portnr < 0)
2895 return portnr;
2896
2897 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2898 GFP_KERNEL);
2899 if (!uap)
2900 return -ENOMEM;
2901
2902 ret = platform_get_irq(pdev, 0);
2903 if (ret < 0)
2904 return ret;
2905 uap->port.irq = ret;
2906
2907#ifdef CONFIG_ACPI_SPCR_TABLE
2908 if (qdf2400_e44_present) {
2909 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2910 uap->vendor = &vendor_qdt_qdf2400_e44;
2911 } else
2912#endif
2913 uap->vendor = &vendor_sbsa;
2914
2915 uap->reg_offset = uap->vendor->reg_offset;
2916 uap->fifosize = 32;
2917 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2918 uap->port.ops = &sbsa_uart_pops;
2919 uap->fixed_baud = baudrate;
2920
2921 snprintf(uap->type, sizeof(uap->type), "SBSA");
2922
2923 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2924
2925 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2926 if (ret)
2927 return ret;
2928
2929 platform_set_drvdata(pdev, uap);
2930
2931 return pl011_register_port(uap);
2932}
2933
2934static int sbsa_uart_remove(struct platform_device *pdev)
2935{
2936 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2937
2938 uart_remove_one_port(&amba_reg, &uap->port);
2939 pl011_unregister_port(uap);
2940 return 0;
2941}
2942
2943static const struct of_device_id sbsa_uart_of_match[] = {
2944 { .compatible = "arm,sbsa-uart", },
2945 {},
2946};
2947MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2948
2949static const struct acpi_device_id __maybe_unused sbsa_uart_acpi_match[] = {
2950 { "ARMH0011", 0 },
2951 { "ARMHB000", 0 },
2952 {},
2953};
2954MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2955
2956static struct platform_driver arm_sbsa_uart_platform_driver = {
2957 .probe = sbsa_uart_probe,
2958 .remove = sbsa_uart_remove,
2959 .driver = {
2960 .name = "sbsa-uart",
2961 .pm = &pl011_dev_pm_ops,
2962 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2963 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2964 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2965 },
2966};
2967
2968static const struct amba_id pl011_ids[] = {
2969 {
2970 .id = 0x00041011,
2971 .mask = 0x000fffff,
2972 .data = &vendor_arm,
2973 },
2974 {
2975 .id = 0x00380802,
2976 .mask = 0x00ffffff,
2977 .data = &vendor_st,
2978 },
2979 { 0, 0 },
2980};
2981
2982MODULE_DEVICE_TABLE(amba, pl011_ids);
2983
2984static struct amba_driver pl011_driver = {
2985 .drv = {
2986 .name = "uart-pl011",
2987 .pm = &pl011_dev_pm_ops,
2988 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2989 },
2990 .id_table = pl011_ids,
2991 .probe = pl011_probe,
2992 .remove = pl011_remove,
2993};
2994
2995static int __init pl011_init(void)
2996{
2997 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2998
2999 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
3000 pr_warn("could not register SBSA UART platform driver\n");
3001 return amba_driver_register(&pl011_driver);
3002}
3003
3004static void __exit pl011_exit(void)
3005{
3006 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
3007 amba_driver_unregister(&pl011_driver);
3008}
3009
3010/*
3011 * While this can be a module, if builtin it's most likely the console
3012 * So let's leave module_exit but move module_init to an earlier place
3013 */
3014arch_initcall(pl011_init);
3015module_exit(pl011_exit);
3016
3017MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
3018MODULE_DESCRIPTION("ARM AMBA serial port driver");
3019MODULE_LICENSE("GPL");
1/*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33#define SUPPORT_SYSRQ
34#endif
35
36#include <linux/module.h>
37#include <linux/ioport.h>
38#include <linux/init.h>
39#include <linux/console.h>
40#include <linux/sysrq.h>
41#include <linux/device.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/serial.h>
46#include <linux/amba/bus.h>
47#include <linux/amba/serial.h>
48#include <linux/clk.h>
49#include <linux/slab.h>
50#include <linux/dmaengine.h>
51#include <linux/dma-mapping.h>
52#include <linux/scatterlist.h>
53#include <linux/delay.h>
54#include <linux/types.h>
55#include <linux/pinctrl/consumer.h>
56
57#include <asm/io.h>
58#include <asm/sizes.h>
59
60#define UART_NR 14
61
62#define SERIAL_AMBA_MAJOR 204
63#define SERIAL_AMBA_MINOR 64
64#define SERIAL_AMBA_NR UART_NR
65
66#define AMBA_ISR_PASS_LIMIT 256
67
68#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
69#define UART_DUMMY_DR_RX (1 << 16)
70
71/* There is by now at least one vendor with differing details, so handle it */
72struct vendor_data {
73 unsigned int ifls;
74 unsigned int fifosize;
75 unsigned int lcrh_tx;
76 unsigned int lcrh_rx;
77 bool oversampling;
78 bool interrupt_may_hang; /* vendor-specific */
79 bool dma_threshold;
80 bool cts_event_workaround;
81};
82
83static struct vendor_data vendor_arm = {
84 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
85 .fifosize = 16,
86 .lcrh_tx = UART011_LCRH,
87 .lcrh_rx = UART011_LCRH,
88 .oversampling = false,
89 .dma_threshold = false,
90 .cts_event_workaround = false,
91};
92
93static struct vendor_data vendor_st = {
94 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
95 .fifosize = 64,
96 .lcrh_tx = ST_UART011_LCRH_TX,
97 .lcrh_rx = ST_UART011_LCRH_RX,
98 .oversampling = true,
99 .interrupt_may_hang = true,
100 .dma_threshold = true,
101 .cts_event_workaround = true,
102};
103
104static struct uart_amba_port *amba_ports[UART_NR];
105
106/* Deals with DMA transactions */
107
108struct pl011_sgbuf {
109 struct scatterlist sg;
110 char *buf;
111};
112
113struct pl011_dmarx_data {
114 struct dma_chan *chan;
115 struct completion complete;
116 bool use_buf_b;
117 struct pl011_sgbuf sgbuf_a;
118 struct pl011_sgbuf sgbuf_b;
119 dma_cookie_t cookie;
120 bool running;
121};
122
123struct pl011_dmatx_data {
124 struct dma_chan *chan;
125 struct scatterlist sg;
126 char *buf;
127 bool queued;
128};
129
130/*
131 * We wrap our port structure around the generic uart_port.
132 */
133struct uart_amba_port {
134 struct uart_port port;
135 struct clk *clk;
136 /* Two optional pin states - default & sleep */
137 struct pinctrl *pinctrl;
138 struct pinctrl_state *pins_default;
139 struct pinctrl_state *pins_sleep;
140 const struct vendor_data *vendor;
141 unsigned int dmacr; /* dma control reg */
142 unsigned int im; /* interrupt mask */
143 unsigned int old_status;
144 unsigned int fifosize; /* vendor-specific */
145 unsigned int lcrh_tx; /* vendor-specific */
146 unsigned int lcrh_rx; /* vendor-specific */
147 unsigned int old_cr; /* state during shutdown */
148 bool autorts;
149 char type[12];
150 bool interrupt_may_hang; /* vendor-specific */
151#ifdef CONFIG_DMA_ENGINE
152 /* DMA stuff */
153 bool using_tx_dma;
154 bool using_rx_dma;
155 struct pl011_dmarx_data dmarx;
156 struct pl011_dmatx_data dmatx;
157#endif
158};
159
160/*
161 * Reads up to 256 characters from the FIFO or until it's empty and
162 * inserts them into the TTY layer. Returns the number of characters
163 * read from the FIFO.
164 */
165static int pl011_fifo_to_tty(struct uart_amba_port *uap)
166{
167 u16 status, ch;
168 unsigned int flag, max_count = 256;
169 int fifotaken = 0;
170
171 while (max_count--) {
172 status = readw(uap->port.membase + UART01x_FR);
173 if (status & UART01x_FR_RXFE)
174 break;
175
176 /* Take chars from the FIFO and update status */
177 ch = readw(uap->port.membase + UART01x_DR) |
178 UART_DUMMY_DR_RX;
179 flag = TTY_NORMAL;
180 uap->port.icount.rx++;
181 fifotaken++;
182
183 if (unlikely(ch & UART_DR_ERROR)) {
184 if (ch & UART011_DR_BE) {
185 ch &= ~(UART011_DR_FE | UART011_DR_PE);
186 uap->port.icount.brk++;
187 if (uart_handle_break(&uap->port))
188 continue;
189 } else if (ch & UART011_DR_PE)
190 uap->port.icount.parity++;
191 else if (ch & UART011_DR_FE)
192 uap->port.icount.frame++;
193 if (ch & UART011_DR_OE)
194 uap->port.icount.overrun++;
195
196 ch &= uap->port.read_status_mask;
197
198 if (ch & UART011_DR_BE)
199 flag = TTY_BREAK;
200 else if (ch & UART011_DR_PE)
201 flag = TTY_PARITY;
202 else if (ch & UART011_DR_FE)
203 flag = TTY_FRAME;
204 }
205
206 if (uart_handle_sysrq_char(&uap->port, ch & 255))
207 continue;
208
209 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
210 }
211
212 return fifotaken;
213}
214
215
216/*
217 * All the DMA operation mode stuff goes inside this ifdef.
218 * This assumes that you have a generic DMA device interface,
219 * no custom DMA interfaces are supported.
220 */
221#ifdef CONFIG_DMA_ENGINE
222
223#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
224
225static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
226 enum dma_data_direction dir)
227{
228 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
229 if (!sg->buf)
230 return -ENOMEM;
231
232 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
233
234 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
235 kfree(sg->buf);
236 return -EINVAL;
237 }
238 return 0;
239}
240
241static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
242 enum dma_data_direction dir)
243{
244 if (sg->buf) {
245 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
246 kfree(sg->buf);
247 }
248}
249
250static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
251{
252 /* DMA is the sole user of the platform data right now */
253 struct amba_pl011_data *plat = uap->port.dev->platform_data;
254 struct dma_slave_config tx_conf = {
255 .dst_addr = uap->port.mapbase + UART01x_DR,
256 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
257 .direction = DMA_MEM_TO_DEV,
258 .dst_maxburst = uap->fifosize >> 1,
259 .device_fc = false,
260 };
261 struct dma_chan *chan;
262 dma_cap_mask_t mask;
263
264 /* We need platform data */
265 if (!plat || !plat->dma_filter) {
266 dev_info(uap->port.dev, "no DMA platform data\n");
267 return;
268 }
269
270 /* Try to acquire a generic DMA engine slave TX channel */
271 dma_cap_zero(mask);
272 dma_cap_set(DMA_SLAVE, mask);
273
274 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
275 if (!chan) {
276 dev_err(uap->port.dev, "no TX DMA channel!\n");
277 return;
278 }
279
280 dmaengine_slave_config(chan, &tx_conf);
281 uap->dmatx.chan = chan;
282
283 dev_info(uap->port.dev, "DMA channel TX %s\n",
284 dma_chan_name(uap->dmatx.chan));
285
286 /* Optionally make use of an RX channel as well */
287 if (plat->dma_rx_param) {
288 struct dma_slave_config rx_conf = {
289 .src_addr = uap->port.mapbase + UART01x_DR,
290 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
291 .direction = DMA_DEV_TO_MEM,
292 .src_maxburst = uap->fifosize >> 1,
293 .device_fc = false,
294 };
295
296 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
297 if (!chan) {
298 dev_err(uap->port.dev, "no RX DMA channel!\n");
299 return;
300 }
301
302 dmaengine_slave_config(chan, &rx_conf);
303 uap->dmarx.chan = chan;
304
305 dev_info(uap->port.dev, "DMA channel RX %s\n",
306 dma_chan_name(uap->dmarx.chan));
307 }
308}
309
310#ifndef MODULE
311/*
312 * Stack up the UARTs and let the above initcall be done at device
313 * initcall time, because the serial driver is called as an arch
314 * initcall, and at this time the DMA subsystem is not yet registered.
315 * At this point the driver will switch over to using DMA where desired.
316 */
317struct dma_uap {
318 struct list_head node;
319 struct uart_amba_port *uap;
320};
321
322static LIST_HEAD(pl011_dma_uarts);
323
324static int __init pl011_dma_initcall(void)
325{
326 struct list_head *node, *tmp;
327
328 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
329 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
330 pl011_dma_probe_initcall(dmau->uap);
331 list_del(node);
332 kfree(dmau);
333 }
334 return 0;
335}
336
337device_initcall(pl011_dma_initcall);
338
339static void pl011_dma_probe(struct uart_amba_port *uap)
340{
341 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
342 if (dmau) {
343 dmau->uap = uap;
344 list_add_tail(&dmau->node, &pl011_dma_uarts);
345 }
346}
347#else
348static void pl011_dma_probe(struct uart_amba_port *uap)
349{
350 pl011_dma_probe_initcall(uap);
351}
352#endif
353
354static void pl011_dma_remove(struct uart_amba_port *uap)
355{
356 /* TODO: remove the initcall if it has not yet executed */
357 if (uap->dmatx.chan)
358 dma_release_channel(uap->dmatx.chan);
359 if (uap->dmarx.chan)
360 dma_release_channel(uap->dmarx.chan);
361}
362
363/* Forward declare this for the refill routine */
364static int pl011_dma_tx_refill(struct uart_amba_port *uap);
365
366/*
367 * The current DMA TX buffer has been sent.
368 * Try to queue up another DMA buffer.
369 */
370static void pl011_dma_tx_callback(void *data)
371{
372 struct uart_amba_port *uap = data;
373 struct pl011_dmatx_data *dmatx = &uap->dmatx;
374 unsigned long flags;
375 u16 dmacr;
376
377 spin_lock_irqsave(&uap->port.lock, flags);
378 if (uap->dmatx.queued)
379 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
380 DMA_TO_DEVICE);
381
382 dmacr = uap->dmacr;
383 uap->dmacr = dmacr & ~UART011_TXDMAE;
384 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
385
386 /*
387 * If TX DMA was disabled, it means that we've stopped the DMA for
388 * some reason (eg, XOFF received, or we want to send an X-char.)
389 *
390 * Note: we need to be careful here of a potential race between DMA
391 * and the rest of the driver - if the driver disables TX DMA while
392 * a TX buffer completing, we must update the tx queued status to
393 * get further refills (hence we check dmacr).
394 */
395 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
396 uart_circ_empty(&uap->port.state->xmit)) {
397 uap->dmatx.queued = false;
398 spin_unlock_irqrestore(&uap->port.lock, flags);
399 return;
400 }
401
402 if (pl011_dma_tx_refill(uap) <= 0) {
403 /*
404 * We didn't queue a DMA buffer for some reason, but we
405 * have data pending to be sent. Re-enable the TX IRQ.
406 */
407 uap->im |= UART011_TXIM;
408 writew(uap->im, uap->port.membase + UART011_IMSC);
409 }
410 spin_unlock_irqrestore(&uap->port.lock, flags);
411}
412
413/*
414 * Try to refill the TX DMA buffer.
415 * Locking: called with port lock held and IRQs disabled.
416 * Returns:
417 * 1 if we queued up a TX DMA buffer.
418 * 0 if we didn't want to handle this by DMA
419 * <0 on error
420 */
421static int pl011_dma_tx_refill(struct uart_amba_port *uap)
422{
423 struct pl011_dmatx_data *dmatx = &uap->dmatx;
424 struct dma_chan *chan = dmatx->chan;
425 struct dma_device *dma_dev = chan->device;
426 struct dma_async_tx_descriptor *desc;
427 struct circ_buf *xmit = &uap->port.state->xmit;
428 unsigned int count;
429
430 /*
431 * Try to avoid the overhead involved in using DMA if the
432 * transaction fits in the first half of the FIFO, by using
433 * the standard interrupt handling. This ensures that we
434 * issue a uart_write_wakeup() at the appropriate time.
435 */
436 count = uart_circ_chars_pending(xmit);
437 if (count < (uap->fifosize >> 1)) {
438 uap->dmatx.queued = false;
439 return 0;
440 }
441
442 /*
443 * Bodge: don't send the last character by DMA, as this
444 * will prevent XON from notifying us to restart DMA.
445 */
446 count -= 1;
447
448 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
449 if (count > PL011_DMA_BUFFER_SIZE)
450 count = PL011_DMA_BUFFER_SIZE;
451
452 if (xmit->tail < xmit->head)
453 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
454 else {
455 size_t first = UART_XMIT_SIZE - xmit->tail;
456 size_t second = xmit->head;
457
458 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
459 if (second)
460 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
461 }
462
463 dmatx->sg.length = count;
464
465 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
466 uap->dmatx.queued = false;
467 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
468 return -EBUSY;
469 }
470
471 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
472 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
473 if (!desc) {
474 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
475 uap->dmatx.queued = false;
476 /*
477 * If DMA cannot be used right now, we complete this
478 * transaction via IRQ and let the TTY layer retry.
479 */
480 dev_dbg(uap->port.dev, "TX DMA busy\n");
481 return -EBUSY;
482 }
483
484 /* Some data to go along to the callback */
485 desc->callback = pl011_dma_tx_callback;
486 desc->callback_param = uap;
487
488 /* All errors should happen at prepare time */
489 dmaengine_submit(desc);
490
491 /* Fire the DMA transaction */
492 dma_dev->device_issue_pending(chan);
493
494 uap->dmacr |= UART011_TXDMAE;
495 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
496 uap->dmatx.queued = true;
497
498 /*
499 * Now we know that DMA will fire, so advance the ring buffer
500 * with the stuff we just dispatched.
501 */
502 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
503 uap->port.icount.tx += count;
504
505 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
506 uart_write_wakeup(&uap->port);
507
508 return 1;
509}
510
511/*
512 * We received a transmit interrupt without a pending X-char but with
513 * pending characters.
514 * Locking: called with port lock held and IRQs disabled.
515 * Returns:
516 * false if we want to use PIO to transmit
517 * true if we queued a DMA buffer
518 */
519static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
520{
521 if (!uap->using_tx_dma)
522 return false;
523
524 /*
525 * If we already have a TX buffer queued, but received a
526 * TX interrupt, it will be because we've just sent an X-char.
527 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
528 */
529 if (uap->dmatx.queued) {
530 uap->dmacr |= UART011_TXDMAE;
531 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
532 uap->im &= ~UART011_TXIM;
533 writew(uap->im, uap->port.membase + UART011_IMSC);
534 return true;
535 }
536
537 /*
538 * We don't have a TX buffer queued, so try to queue one.
539 * If we successfully queued a buffer, mask the TX IRQ.
540 */
541 if (pl011_dma_tx_refill(uap) > 0) {
542 uap->im &= ~UART011_TXIM;
543 writew(uap->im, uap->port.membase + UART011_IMSC);
544 return true;
545 }
546 return false;
547}
548
549/*
550 * Stop the DMA transmit (eg, due to received XOFF).
551 * Locking: called with port lock held and IRQs disabled.
552 */
553static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
554{
555 if (uap->dmatx.queued) {
556 uap->dmacr &= ~UART011_TXDMAE;
557 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
558 }
559}
560
561/*
562 * Try to start a DMA transmit, or in the case of an XON/OFF
563 * character queued for send, try to get that character out ASAP.
564 * Locking: called with port lock held and IRQs disabled.
565 * Returns:
566 * false if we want the TX IRQ to be enabled
567 * true if we have a buffer queued
568 */
569static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
570{
571 u16 dmacr;
572
573 if (!uap->using_tx_dma)
574 return false;
575
576 if (!uap->port.x_char) {
577 /* no X-char, try to push chars out in DMA mode */
578 bool ret = true;
579
580 if (!uap->dmatx.queued) {
581 if (pl011_dma_tx_refill(uap) > 0) {
582 uap->im &= ~UART011_TXIM;
583 ret = true;
584 } else {
585 uap->im |= UART011_TXIM;
586 ret = false;
587 }
588 writew(uap->im, uap->port.membase + UART011_IMSC);
589 } else if (!(uap->dmacr & UART011_TXDMAE)) {
590 uap->dmacr |= UART011_TXDMAE;
591 writew(uap->dmacr,
592 uap->port.membase + UART011_DMACR);
593 }
594 return ret;
595 }
596
597 /*
598 * We have an X-char to send. Disable DMA to prevent it loading
599 * the TX fifo, and then see if we can stuff it into the FIFO.
600 */
601 dmacr = uap->dmacr;
602 uap->dmacr &= ~UART011_TXDMAE;
603 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
604
605 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
606 /*
607 * No space in the FIFO, so enable the transmit interrupt
608 * so we know when there is space. Note that once we've
609 * loaded the character, we should just re-enable DMA.
610 */
611 return false;
612 }
613
614 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
615 uap->port.icount.tx++;
616 uap->port.x_char = 0;
617
618 /* Success - restore the DMA state */
619 uap->dmacr = dmacr;
620 writew(dmacr, uap->port.membase + UART011_DMACR);
621
622 return true;
623}
624
625/*
626 * Flush the transmit buffer.
627 * Locking: called with port lock held and IRQs disabled.
628 */
629static void pl011_dma_flush_buffer(struct uart_port *port)
630{
631 struct uart_amba_port *uap = (struct uart_amba_port *)port;
632
633 if (!uap->using_tx_dma)
634 return;
635
636 /* Avoid deadlock with the DMA engine callback */
637 spin_unlock(&uap->port.lock);
638 dmaengine_terminate_all(uap->dmatx.chan);
639 spin_lock(&uap->port.lock);
640 if (uap->dmatx.queued) {
641 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
642 DMA_TO_DEVICE);
643 uap->dmatx.queued = false;
644 uap->dmacr &= ~UART011_TXDMAE;
645 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
646 }
647}
648
649static void pl011_dma_rx_callback(void *data);
650
651static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
652{
653 struct dma_chan *rxchan = uap->dmarx.chan;
654 struct pl011_dmarx_data *dmarx = &uap->dmarx;
655 struct dma_async_tx_descriptor *desc;
656 struct pl011_sgbuf *sgbuf;
657
658 if (!rxchan)
659 return -EIO;
660
661 /* Start the RX DMA job */
662 sgbuf = uap->dmarx.use_buf_b ?
663 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
664 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
665 DMA_DEV_TO_MEM,
666 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
667 /*
668 * If the DMA engine is busy and cannot prepare a
669 * channel, no big deal, the driver will fall back
670 * to interrupt mode as a result of this error code.
671 */
672 if (!desc) {
673 uap->dmarx.running = false;
674 dmaengine_terminate_all(rxchan);
675 return -EBUSY;
676 }
677
678 /* Some data to go along to the callback */
679 desc->callback = pl011_dma_rx_callback;
680 desc->callback_param = uap;
681 dmarx->cookie = dmaengine_submit(desc);
682 dma_async_issue_pending(rxchan);
683
684 uap->dmacr |= UART011_RXDMAE;
685 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
686 uap->dmarx.running = true;
687
688 uap->im &= ~UART011_RXIM;
689 writew(uap->im, uap->port.membase + UART011_IMSC);
690
691 return 0;
692}
693
694/*
695 * This is called when either the DMA job is complete, or
696 * the FIFO timeout interrupt occurred. This must be called
697 * with the port spinlock uap->port.lock held.
698 */
699static void pl011_dma_rx_chars(struct uart_amba_port *uap,
700 u32 pending, bool use_buf_b,
701 bool readfifo)
702{
703 struct tty_struct *tty = uap->port.state->port.tty;
704 struct pl011_sgbuf *sgbuf = use_buf_b ?
705 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
706 struct device *dev = uap->dmarx.chan->device->dev;
707 int dma_count = 0;
708 u32 fifotaken = 0; /* only used for vdbg() */
709
710 /* Pick everything from the DMA first */
711 if (pending) {
712 /* Sync in buffer */
713 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
714
715 /*
716 * First take all chars in the DMA pipe, then look in the FIFO.
717 * Note that tty_insert_flip_buf() tries to take as many chars
718 * as it can.
719 */
720 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
721 sgbuf->buf, pending);
722
723 /* Return buffer to device */
724 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
725
726 uap->port.icount.rx += dma_count;
727 if (dma_count < pending)
728 dev_warn(uap->port.dev,
729 "couldn't insert all characters (TTY is full?)\n");
730 }
731
732 /*
733 * Only continue with trying to read the FIFO if all DMA chars have
734 * been taken first.
735 */
736 if (dma_count == pending && readfifo) {
737 /* Clear any error flags */
738 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
739 uap->port.membase + UART011_ICR);
740
741 /*
742 * If we read all the DMA'd characters, and we had an
743 * incomplete buffer, that could be due to an rx error, or
744 * maybe we just timed out. Read any pending chars and check
745 * the error status.
746 *
747 * Error conditions will only occur in the FIFO, these will
748 * trigger an immediate interrupt and stop the DMA job, so we
749 * will always find the error in the FIFO, never in the DMA
750 * buffer.
751 */
752 fifotaken = pl011_fifo_to_tty(uap);
753 }
754
755 spin_unlock(&uap->port.lock);
756 dev_vdbg(uap->port.dev,
757 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
758 dma_count, fifotaken);
759 tty_flip_buffer_push(tty);
760 spin_lock(&uap->port.lock);
761}
762
763static void pl011_dma_rx_irq(struct uart_amba_port *uap)
764{
765 struct pl011_dmarx_data *dmarx = &uap->dmarx;
766 struct dma_chan *rxchan = dmarx->chan;
767 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
768 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
769 size_t pending;
770 struct dma_tx_state state;
771 enum dma_status dmastat;
772
773 /*
774 * Pause the transfer so we can trust the current counter,
775 * do this before we pause the PL011 block, else we may
776 * overflow the FIFO.
777 */
778 if (dmaengine_pause(rxchan))
779 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
780 dmastat = rxchan->device->device_tx_status(rxchan,
781 dmarx->cookie, &state);
782 if (dmastat != DMA_PAUSED)
783 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
784
785 /* Disable RX DMA - incoming data will wait in the FIFO */
786 uap->dmacr &= ~UART011_RXDMAE;
787 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
788 uap->dmarx.running = false;
789
790 pending = sgbuf->sg.length - state.residue;
791 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
792 /* Then we terminate the transfer - we now know our residue */
793 dmaengine_terminate_all(rxchan);
794
795 /*
796 * This will take the chars we have so far and insert
797 * into the framework.
798 */
799 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
800
801 /* Switch buffer & re-trigger DMA job */
802 dmarx->use_buf_b = !dmarx->use_buf_b;
803 if (pl011_dma_rx_trigger_dma(uap)) {
804 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
805 "fall back to interrupt mode\n");
806 uap->im |= UART011_RXIM;
807 writew(uap->im, uap->port.membase + UART011_IMSC);
808 }
809}
810
811static void pl011_dma_rx_callback(void *data)
812{
813 struct uart_amba_port *uap = data;
814 struct pl011_dmarx_data *dmarx = &uap->dmarx;
815 struct dma_chan *rxchan = dmarx->chan;
816 bool lastbuf = dmarx->use_buf_b;
817 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
818 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
819 size_t pending;
820 struct dma_tx_state state;
821 int ret;
822
823 /*
824 * This completion interrupt occurs typically when the
825 * RX buffer is totally stuffed but no timeout has yet
826 * occurred. When that happens, we just want the RX
827 * routine to flush out the secondary DMA buffer while
828 * we immediately trigger the next DMA job.
829 */
830 spin_lock_irq(&uap->port.lock);
831 /*
832 * Rx data can be taken by the UART interrupts during
833 * the DMA irq handler. So we check the residue here.
834 */
835 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
836 pending = sgbuf->sg.length - state.residue;
837 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
838 /* Then we terminate the transfer - we now know our residue */
839 dmaengine_terminate_all(rxchan);
840
841 uap->dmarx.running = false;
842 dmarx->use_buf_b = !lastbuf;
843 ret = pl011_dma_rx_trigger_dma(uap);
844
845 pl011_dma_rx_chars(uap, pending, lastbuf, false);
846 spin_unlock_irq(&uap->port.lock);
847 /*
848 * Do this check after we picked the DMA chars so we don't
849 * get some IRQ immediately from RX.
850 */
851 if (ret) {
852 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
853 "fall back to interrupt mode\n");
854 uap->im |= UART011_RXIM;
855 writew(uap->im, uap->port.membase + UART011_IMSC);
856 }
857}
858
859/*
860 * Stop accepting received characters, when we're shutting down or
861 * suspending this port.
862 * Locking: called with port lock held and IRQs disabled.
863 */
864static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
865{
866 /* FIXME. Just disable the DMA enable */
867 uap->dmacr &= ~UART011_RXDMAE;
868 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
869}
870
871static void pl011_dma_startup(struct uart_amba_port *uap)
872{
873 int ret;
874
875 if (!uap->dmatx.chan)
876 return;
877
878 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
879 if (!uap->dmatx.buf) {
880 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
881 uap->port.fifosize = uap->fifosize;
882 return;
883 }
884
885 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
886
887 /* The DMA buffer is now the FIFO the TTY subsystem can use */
888 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
889 uap->using_tx_dma = true;
890
891 if (!uap->dmarx.chan)
892 goto skip_rx;
893
894 /* Allocate and map DMA RX buffers */
895 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
896 DMA_FROM_DEVICE);
897 if (ret) {
898 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
899 "RX buffer A", ret);
900 goto skip_rx;
901 }
902
903 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
904 DMA_FROM_DEVICE);
905 if (ret) {
906 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
907 "RX buffer B", ret);
908 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
909 DMA_FROM_DEVICE);
910 goto skip_rx;
911 }
912
913 uap->using_rx_dma = true;
914
915skip_rx:
916 /* Turn on DMA error (RX/TX will be enabled on demand) */
917 uap->dmacr |= UART011_DMAONERR;
918 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
919
920 /*
921 * ST Micro variants has some specific dma burst threshold
922 * compensation. Set this to 16 bytes, so burst will only
923 * be issued above/below 16 bytes.
924 */
925 if (uap->vendor->dma_threshold)
926 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
927 uap->port.membase + ST_UART011_DMAWM);
928
929 if (uap->using_rx_dma) {
930 if (pl011_dma_rx_trigger_dma(uap))
931 dev_dbg(uap->port.dev, "could not trigger initial "
932 "RX DMA job, fall back to interrupt mode\n");
933 }
934}
935
936static void pl011_dma_shutdown(struct uart_amba_port *uap)
937{
938 if (!(uap->using_tx_dma || uap->using_rx_dma))
939 return;
940
941 /* Disable RX and TX DMA */
942 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
943 barrier();
944
945 spin_lock_irq(&uap->port.lock);
946 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
947 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
948 spin_unlock_irq(&uap->port.lock);
949
950 if (uap->using_tx_dma) {
951 /* In theory, this should already be done by pl011_dma_flush_buffer */
952 dmaengine_terminate_all(uap->dmatx.chan);
953 if (uap->dmatx.queued) {
954 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
955 DMA_TO_DEVICE);
956 uap->dmatx.queued = false;
957 }
958
959 kfree(uap->dmatx.buf);
960 uap->using_tx_dma = false;
961 }
962
963 if (uap->using_rx_dma) {
964 dmaengine_terminate_all(uap->dmarx.chan);
965 /* Clean up the RX DMA */
966 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
967 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
968 uap->using_rx_dma = false;
969 }
970}
971
972static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
973{
974 return uap->using_rx_dma;
975}
976
977static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
978{
979 return uap->using_rx_dma && uap->dmarx.running;
980}
981
982
983#else
984/* Blank functions if the DMA engine is not available */
985static inline void pl011_dma_probe(struct uart_amba_port *uap)
986{
987}
988
989static inline void pl011_dma_remove(struct uart_amba_port *uap)
990{
991}
992
993static inline void pl011_dma_startup(struct uart_amba_port *uap)
994{
995}
996
997static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
998{
999}
1000
1001static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1002{
1003 return false;
1004}
1005
1006static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1007{
1008}
1009
1010static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1011{
1012 return false;
1013}
1014
1015static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1016{
1017}
1018
1019static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1020{
1021}
1022
1023static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1024{
1025 return -EIO;
1026}
1027
1028static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1029{
1030 return false;
1031}
1032
1033static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1034{
1035 return false;
1036}
1037
1038#define pl011_dma_flush_buffer NULL
1039#endif
1040
1041static void pl011_stop_tx(struct uart_port *port)
1042{
1043 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1044
1045 uap->im &= ~UART011_TXIM;
1046 writew(uap->im, uap->port.membase + UART011_IMSC);
1047 pl011_dma_tx_stop(uap);
1048}
1049
1050static void pl011_start_tx(struct uart_port *port)
1051{
1052 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1053
1054 if (!pl011_dma_tx_start(uap)) {
1055 uap->im |= UART011_TXIM;
1056 writew(uap->im, uap->port.membase + UART011_IMSC);
1057 }
1058}
1059
1060static void pl011_stop_rx(struct uart_port *port)
1061{
1062 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1063
1064 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1065 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1066 writew(uap->im, uap->port.membase + UART011_IMSC);
1067
1068 pl011_dma_rx_stop(uap);
1069}
1070
1071static void pl011_enable_ms(struct uart_port *port)
1072{
1073 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1074
1075 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1076 writew(uap->im, uap->port.membase + UART011_IMSC);
1077}
1078
1079static void pl011_rx_chars(struct uart_amba_port *uap)
1080{
1081 struct tty_struct *tty = uap->port.state->port.tty;
1082
1083 pl011_fifo_to_tty(uap);
1084
1085 spin_unlock(&uap->port.lock);
1086 tty_flip_buffer_push(tty);
1087 /*
1088 * If we were temporarily out of DMA mode for a while,
1089 * attempt to switch back to DMA mode again.
1090 */
1091 if (pl011_dma_rx_available(uap)) {
1092 if (pl011_dma_rx_trigger_dma(uap)) {
1093 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1094 "fall back to interrupt mode again\n");
1095 uap->im |= UART011_RXIM;
1096 } else
1097 uap->im &= ~UART011_RXIM;
1098 writew(uap->im, uap->port.membase + UART011_IMSC);
1099 }
1100 spin_lock(&uap->port.lock);
1101}
1102
1103static void pl011_tx_chars(struct uart_amba_port *uap)
1104{
1105 struct circ_buf *xmit = &uap->port.state->xmit;
1106 int count;
1107
1108 if (uap->port.x_char) {
1109 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1110 uap->port.icount.tx++;
1111 uap->port.x_char = 0;
1112 return;
1113 }
1114 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1115 pl011_stop_tx(&uap->port);
1116 return;
1117 }
1118
1119 /* If we are using DMA mode, try to send some characters. */
1120 if (pl011_dma_tx_irq(uap))
1121 return;
1122
1123 count = uap->fifosize >> 1;
1124 do {
1125 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1126 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1127 uap->port.icount.tx++;
1128 if (uart_circ_empty(xmit))
1129 break;
1130 } while (--count > 0);
1131
1132 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1133 uart_write_wakeup(&uap->port);
1134
1135 if (uart_circ_empty(xmit))
1136 pl011_stop_tx(&uap->port);
1137}
1138
1139static void pl011_modem_status(struct uart_amba_port *uap)
1140{
1141 unsigned int status, delta;
1142
1143 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1144
1145 delta = status ^ uap->old_status;
1146 uap->old_status = status;
1147
1148 if (!delta)
1149 return;
1150
1151 if (delta & UART01x_FR_DCD)
1152 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1153
1154 if (delta & UART01x_FR_DSR)
1155 uap->port.icount.dsr++;
1156
1157 if (delta & UART01x_FR_CTS)
1158 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1159
1160 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1161}
1162
1163static irqreturn_t pl011_int(int irq, void *dev_id)
1164{
1165 struct uart_amba_port *uap = dev_id;
1166 unsigned long flags;
1167 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1168 int handled = 0;
1169 unsigned int dummy_read;
1170
1171 spin_lock_irqsave(&uap->port.lock, flags);
1172
1173 status = readw(uap->port.membase + UART011_MIS);
1174 if (status) {
1175 do {
1176 if (uap->vendor->cts_event_workaround) {
1177 /* workaround to make sure that all bits are unlocked.. */
1178 writew(0x00, uap->port.membase + UART011_ICR);
1179
1180 /*
1181 * WA: introduce 26ns(1 uart clk) delay before W1C;
1182 * single apb access will incur 2 pclk(133.12Mhz) delay,
1183 * so add 2 dummy reads
1184 */
1185 dummy_read = readw(uap->port.membase + UART011_ICR);
1186 dummy_read = readw(uap->port.membase + UART011_ICR);
1187 }
1188
1189 writew(status & ~(UART011_TXIS|UART011_RTIS|
1190 UART011_RXIS),
1191 uap->port.membase + UART011_ICR);
1192
1193 if (status & (UART011_RTIS|UART011_RXIS)) {
1194 if (pl011_dma_rx_running(uap))
1195 pl011_dma_rx_irq(uap);
1196 else
1197 pl011_rx_chars(uap);
1198 }
1199 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1200 UART011_CTSMIS|UART011_RIMIS))
1201 pl011_modem_status(uap);
1202 if (status & UART011_TXIS)
1203 pl011_tx_chars(uap);
1204
1205 if (pass_counter-- == 0)
1206 break;
1207
1208 status = readw(uap->port.membase + UART011_MIS);
1209 } while (status != 0);
1210 handled = 1;
1211 }
1212
1213 spin_unlock_irqrestore(&uap->port.lock, flags);
1214
1215 return IRQ_RETVAL(handled);
1216}
1217
1218static unsigned int pl01x_tx_empty(struct uart_port *port)
1219{
1220 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1221 unsigned int status = readw(uap->port.membase + UART01x_FR);
1222 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1223}
1224
1225static unsigned int pl01x_get_mctrl(struct uart_port *port)
1226{
1227 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1228 unsigned int result = 0;
1229 unsigned int status = readw(uap->port.membase + UART01x_FR);
1230
1231#define TIOCMBIT(uartbit, tiocmbit) \
1232 if (status & uartbit) \
1233 result |= tiocmbit
1234
1235 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1236 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1237 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1238 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1239#undef TIOCMBIT
1240 return result;
1241}
1242
1243static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1244{
1245 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1246 unsigned int cr;
1247
1248 cr = readw(uap->port.membase + UART011_CR);
1249
1250#define TIOCMBIT(tiocmbit, uartbit) \
1251 if (mctrl & tiocmbit) \
1252 cr |= uartbit; \
1253 else \
1254 cr &= ~uartbit
1255
1256 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1257 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1258 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1259 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1260 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1261
1262 if (uap->autorts) {
1263 /* We need to disable auto-RTS if we want to turn RTS off */
1264 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1265 }
1266#undef TIOCMBIT
1267
1268 writew(cr, uap->port.membase + UART011_CR);
1269}
1270
1271static void pl011_break_ctl(struct uart_port *port, int break_state)
1272{
1273 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1274 unsigned long flags;
1275 unsigned int lcr_h;
1276
1277 spin_lock_irqsave(&uap->port.lock, flags);
1278 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1279 if (break_state == -1)
1280 lcr_h |= UART01x_LCRH_BRK;
1281 else
1282 lcr_h &= ~UART01x_LCRH_BRK;
1283 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1284 spin_unlock_irqrestore(&uap->port.lock, flags);
1285}
1286
1287#ifdef CONFIG_CONSOLE_POLL
1288static int pl010_get_poll_char(struct uart_port *port)
1289{
1290 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1291 unsigned int status;
1292
1293 status = readw(uap->port.membase + UART01x_FR);
1294 if (status & UART01x_FR_RXFE)
1295 return NO_POLL_CHAR;
1296
1297 return readw(uap->port.membase + UART01x_DR);
1298}
1299
1300static void pl010_put_poll_char(struct uart_port *port,
1301 unsigned char ch)
1302{
1303 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1304
1305 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1306 barrier();
1307
1308 writew(ch, uap->port.membase + UART01x_DR);
1309}
1310
1311#endif /* CONFIG_CONSOLE_POLL */
1312
1313static int pl011_startup(struct uart_port *port)
1314{
1315 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1316 unsigned int cr;
1317 int retval;
1318
1319 /* Optionaly enable pins to be muxed in and configured */
1320 if (!IS_ERR(uap->pins_default)) {
1321 retval = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1322 if (retval)
1323 dev_err(port->dev,
1324 "could not set default pins\n");
1325 }
1326
1327 retval = clk_prepare(uap->clk);
1328 if (retval)
1329 goto out;
1330
1331 /*
1332 * Try to enable the clock producer.
1333 */
1334 retval = clk_enable(uap->clk);
1335 if (retval)
1336 goto clk_unprep;
1337
1338 uap->port.uartclk = clk_get_rate(uap->clk);
1339
1340 /* Clear pending error and receive interrupts */
1341 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1342 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1343
1344 /*
1345 * Allocate the IRQ
1346 */
1347 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1348 if (retval)
1349 goto clk_dis;
1350
1351 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1352
1353 /*
1354 * Provoke TX FIFO interrupt into asserting.
1355 */
1356 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1357 writew(cr, uap->port.membase + UART011_CR);
1358 writew(0, uap->port.membase + UART011_FBRD);
1359 writew(1, uap->port.membase + UART011_IBRD);
1360 writew(0, uap->port.membase + uap->lcrh_rx);
1361 if (uap->lcrh_tx != uap->lcrh_rx) {
1362 int i;
1363 /*
1364 * Wait 10 PCLKs before writing LCRH_TX register,
1365 * to get this delay write read only register 10 times
1366 */
1367 for (i = 0; i < 10; ++i)
1368 writew(0xff, uap->port.membase + UART011_MIS);
1369 writew(0, uap->port.membase + uap->lcrh_tx);
1370 }
1371 writew(0, uap->port.membase + UART01x_DR);
1372 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1373 barrier();
1374
1375 /* restore RTS and DTR */
1376 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1377 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1378 writew(cr, uap->port.membase + UART011_CR);
1379
1380 /*
1381 * initialise the old status of the modem signals
1382 */
1383 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1384
1385 /* Startup DMA */
1386 pl011_dma_startup(uap);
1387
1388 /*
1389 * Finally, enable interrupts, only timeouts when using DMA
1390 * if initial RX DMA job failed, start in interrupt mode
1391 * as well.
1392 */
1393 spin_lock_irq(&uap->port.lock);
1394 /* Clear out any spuriously appearing RX interrupts */
1395 writew(UART011_RTIS | UART011_RXIS,
1396 uap->port.membase + UART011_ICR);
1397 uap->im = UART011_RTIM;
1398 if (!pl011_dma_rx_running(uap))
1399 uap->im |= UART011_RXIM;
1400 writew(uap->im, uap->port.membase + UART011_IMSC);
1401 spin_unlock_irq(&uap->port.lock);
1402
1403 if (uap->port.dev->platform_data) {
1404 struct amba_pl011_data *plat;
1405
1406 plat = uap->port.dev->platform_data;
1407 if (plat->init)
1408 plat->init();
1409 }
1410
1411 return 0;
1412
1413 clk_dis:
1414 clk_disable(uap->clk);
1415 clk_unprep:
1416 clk_unprepare(uap->clk);
1417 out:
1418 return retval;
1419}
1420
1421static void pl011_shutdown_channel(struct uart_amba_port *uap,
1422 unsigned int lcrh)
1423{
1424 unsigned long val;
1425
1426 val = readw(uap->port.membase + lcrh);
1427 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1428 writew(val, uap->port.membase + lcrh);
1429}
1430
1431static void pl011_shutdown(struct uart_port *port)
1432{
1433 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1434 unsigned int cr;
1435 int retval;
1436
1437 /*
1438 * disable all interrupts
1439 */
1440 spin_lock_irq(&uap->port.lock);
1441 uap->im = 0;
1442 writew(uap->im, uap->port.membase + UART011_IMSC);
1443 writew(0xffff, uap->port.membase + UART011_ICR);
1444 spin_unlock_irq(&uap->port.lock);
1445
1446 pl011_dma_shutdown(uap);
1447
1448 /*
1449 * Free the interrupt
1450 */
1451 free_irq(uap->port.irq, uap);
1452
1453 /*
1454 * disable the port
1455 * disable the port. It should not disable RTS and DTR.
1456 * Also RTS and DTR state should be preserved to restore
1457 * it during startup().
1458 */
1459 uap->autorts = false;
1460 cr = readw(uap->port.membase + UART011_CR);
1461 uap->old_cr = cr;
1462 cr &= UART011_CR_RTS | UART011_CR_DTR;
1463 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1464 writew(cr, uap->port.membase + UART011_CR);
1465
1466 /*
1467 * disable break condition and fifos
1468 */
1469 pl011_shutdown_channel(uap, uap->lcrh_rx);
1470 if (uap->lcrh_rx != uap->lcrh_tx)
1471 pl011_shutdown_channel(uap, uap->lcrh_tx);
1472
1473 /*
1474 * Shut down the clock producer
1475 */
1476 clk_disable(uap->clk);
1477 clk_unprepare(uap->clk);
1478 /* Optionally let pins go into sleep states */
1479 if (!IS_ERR(uap->pins_sleep)) {
1480 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep);
1481 if (retval)
1482 dev_err(port->dev,
1483 "could not set pins to sleep state\n");
1484 }
1485
1486
1487 if (uap->port.dev->platform_data) {
1488 struct amba_pl011_data *plat;
1489
1490 plat = uap->port.dev->platform_data;
1491 if (plat->exit)
1492 plat->exit();
1493 }
1494
1495}
1496
1497static void
1498pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1499 struct ktermios *old)
1500{
1501 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1502 unsigned int lcr_h, old_cr;
1503 unsigned long flags;
1504 unsigned int baud, quot, clkdiv;
1505
1506 if (uap->vendor->oversampling)
1507 clkdiv = 8;
1508 else
1509 clkdiv = 16;
1510
1511 /*
1512 * Ask the core to calculate the divisor for us.
1513 */
1514 baud = uart_get_baud_rate(port, termios, old, 0,
1515 port->uartclk / clkdiv);
1516
1517 if (baud > port->uartclk/16)
1518 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1519 else
1520 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1521
1522 switch (termios->c_cflag & CSIZE) {
1523 case CS5:
1524 lcr_h = UART01x_LCRH_WLEN_5;
1525 break;
1526 case CS6:
1527 lcr_h = UART01x_LCRH_WLEN_6;
1528 break;
1529 case CS7:
1530 lcr_h = UART01x_LCRH_WLEN_7;
1531 break;
1532 default: // CS8
1533 lcr_h = UART01x_LCRH_WLEN_8;
1534 break;
1535 }
1536 if (termios->c_cflag & CSTOPB)
1537 lcr_h |= UART01x_LCRH_STP2;
1538 if (termios->c_cflag & PARENB) {
1539 lcr_h |= UART01x_LCRH_PEN;
1540 if (!(termios->c_cflag & PARODD))
1541 lcr_h |= UART01x_LCRH_EPS;
1542 }
1543 if (uap->fifosize > 1)
1544 lcr_h |= UART01x_LCRH_FEN;
1545
1546 spin_lock_irqsave(&port->lock, flags);
1547
1548 /*
1549 * Update the per-port timeout.
1550 */
1551 uart_update_timeout(port, termios->c_cflag, baud);
1552
1553 port->read_status_mask = UART011_DR_OE | 255;
1554 if (termios->c_iflag & INPCK)
1555 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1556 if (termios->c_iflag & (BRKINT | PARMRK))
1557 port->read_status_mask |= UART011_DR_BE;
1558
1559 /*
1560 * Characters to ignore
1561 */
1562 port->ignore_status_mask = 0;
1563 if (termios->c_iflag & IGNPAR)
1564 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1565 if (termios->c_iflag & IGNBRK) {
1566 port->ignore_status_mask |= UART011_DR_BE;
1567 /*
1568 * If we're ignoring parity and break indicators,
1569 * ignore overruns too (for real raw support).
1570 */
1571 if (termios->c_iflag & IGNPAR)
1572 port->ignore_status_mask |= UART011_DR_OE;
1573 }
1574
1575 /*
1576 * Ignore all characters if CREAD is not set.
1577 */
1578 if ((termios->c_cflag & CREAD) == 0)
1579 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1580
1581 if (UART_ENABLE_MS(port, termios->c_cflag))
1582 pl011_enable_ms(port);
1583
1584 /* first, disable everything */
1585 old_cr = readw(port->membase + UART011_CR);
1586 writew(0, port->membase + UART011_CR);
1587
1588 if (termios->c_cflag & CRTSCTS) {
1589 if (old_cr & UART011_CR_RTS)
1590 old_cr |= UART011_CR_RTSEN;
1591
1592 old_cr |= UART011_CR_CTSEN;
1593 uap->autorts = true;
1594 } else {
1595 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1596 uap->autorts = false;
1597 }
1598
1599 if (uap->vendor->oversampling) {
1600 if (baud > port->uartclk / 16)
1601 old_cr |= ST_UART011_CR_OVSFACT;
1602 else
1603 old_cr &= ~ST_UART011_CR_OVSFACT;
1604 }
1605
1606 /*
1607 * Workaround for the ST Micro oversampling variants to
1608 * increase the bitrate slightly, by lowering the divisor,
1609 * to avoid delayed sampling of start bit at high speeds,
1610 * else we see data corruption.
1611 */
1612 if (uap->vendor->oversampling) {
1613 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1614 quot -= 1;
1615 else if ((baud > 3250000) && (quot > 2))
1616 quot -= 2;
1617 }
1618 /* Set baud rate */
1619 writew(quot & 0x3f, port->membase + UART011_FBRD);
1620 writew(quot >> 6, port->membase + UART011_IBRD);
1621
1622 /*
1623 * ----------v----------v----------v----------v-----
1624 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1625 * UART011_FBRD & UART011_IBRD.
1626 * ----------^----------^----------^----------^-----
1627 */
1628 writew(lcr_h, port->membase + uap->lcrh_rx);
1629 if (uap->lcrh_rx != uap->lcrh_tx) {
1630 int i;
1631 /*
1632 * Wait 10 PCLKs before writing LCRH_TX register,
1633 * to get this delay write read only register 10 times
1634 */
1635 for (i = 0; i < 10; ++i)
1636 writew(0xff, uap->port.membase + UART011_MIS);
1637 writew(lcr_h, port->membase + uap->lcrh_tx);
1638 }
1639 writew(old_cr, port->membase + UART011_CR);
1640
1641 spin_unlock_irqrestore(&port->lock, flags);
1642}
1643
1644static const char *pl011_type(struct uart_port *port)
1645{
1646 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1647 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1648}
1649
1650/*
1651 * Release the memory region(s) being used by 'port'
1652 */
1653static void pl010_release_port(struct uart_port *port)
1654{
1655 release_mem_region(port->mapbase, SZ_4K);
1656}
1657
1658/*
1659 * Request the memory region(s) being used by 'port'
1660 */
1661static int pl010_request_port(struct uart_port *port)
1662{
1663 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1664 != NULL ? 0 : -EBUSY;
1665}
1666
1667/*
1668 * Configure/autoconfigure the port.
1669 */
1670static void pl010_config_port(struct uart_port *port, int flags)
1671{
1672 if (flags & UART_CONFIG_TYPE) {
1673 port->type = PORT_AMBA;
1674 pl010_request_port(port);
1675 }
1676}
1677
1678/*
1679 * verify the new serial_struct (for TIOCSSERIAL).
1680 */
1681static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
1682{
1683 int ret = 0;
1684 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1685 ret = -EINVAL;
1686 if (ser->irq < 0 || ser->irq >= nr_irqs)
1687 ret = -EINVAL;
1688 if (ser->baud_base < 9600)
1689 ret = -EINVAL;
1690 return ret;
1691}
1692
1693static struct uart_ops amba_pl011_pops = {
1694 .tx_empty = pl01x_tx_empty,
1695 .set_mctrl = pl011_set_mctrl,
1696 .get_mctrl = pl01x_get_mctrl,
1697 .stop_tx = pl011_stop_tx,
1698 .start_tx = pl011_start_tx,
1699 .stop_rx = pl011_stop_rx,
1700 .enable_ms = pl011_enable_ms,
1701 .break_ctl = pl011_break_ctl,
1702 .startup = pl011_startup,
1703 .shutdown = pl011_shutdown,
1704 .flush_buffer = pl011_dma_flush_buffer,
1705 .set_termios = pl011_set_termios,
1706 .type = pl011_type,
1707 .release_port = pl010_release_port,
1708 .request_port = pl010_request_port,
1709 .config_port = pl010_config_port,
1710 .verify_port = pl010_verify_port,
1711#ifdef CONFIG_CONSOLE_POLL
1712 .poll_get_char = pl010_get_poll_char,
1713 .poll_put_char = pl010_put_poll_char,
1714#endif
1715};
1716
1717static struct uart_amba_port *amba_ports[UART_NR];
1718
1719#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1720
1721static void pl011_console_putchar(struct uart_port *port, int ch)
1722{
1723 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1724
1725 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1726 barrier();
1727 writew(ch, uap->port.membase + UART01x_DR);
1728}
1729
1730static void
1731pl011_console_write(struct console *co, const char *s, unsigned int count)
1732{
1733 struct uart_amba_port *uap = amba_ports[co->index];
1734 unsigned int status, old_cr, new_cr;
1735 unsigned long flags;
1736 int locked = 1;
1737
1738 clk_enable(uap->clk);
1739
1740 local_irq_save(flags);
1741 if (uap->port.sysrq)
1742 locked = 0;
1743 else if (oops_in_progress)
1744 locked = spin_trylock(&uap->port.lock);
1745 else
1746 spin_lock(&uap->port.lock);
1747
1748 /*
1749 * First save the CR then disable the interrupts
1750 */
1751 old_cr = readw(uap->port.membase + UART011_CR);
1752 new_cr = old_cr & ~UART011_CR_CTSEN;
1753 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1754 writew(new_cr, uap->port.membase + UART011_CR);
1755
1756 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1757
1758 /*
1759 * Finally, wait for transmitter to become empty
1760 * and restore the TCR
1761 */
1762 do {
1763 status = readw(uap->port.membase + UART01x_FR);
1764 } while (status & UART01x_FR_BUSY);
1765 writew(old_cr, uap->port.membase + UART011_CR);
1766
1767 if (locked)
1768 spin_unlock(&uap->port.lock);
1769 local_irq_restore(flags);
1770
1771 clk_disable(uap->clk);
1772}
1773
1774static void __init
1775pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1776 int *parity, int *bits)
1777{
1778 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1779 unsigned int lcr_h, ibrd, fbrd;
1780
1781 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1782
1783 *parity = 'n';
1784 if (lcr_h & UART01x_LCRH_PEN) {
1785 if (lcr_h & UART01x_LCRH_EPS)
1786 *parity = 'e';
1787 else
1788 *parity = 'o';
1789 }
1790
1791 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1792 *bits = 7;
1793 else
1794 *bits = 8;
1795
1796 ibrd = readw(uap->port.membase + UART011_IBRD);
1797 fbrd = readw(uap->port.membase + UART011_FBRD);
1798
1799 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1800
1801 if (uap->vendor->oversampling) {
1802 if (readw(uap->port.membase + UART011_CR)
1803 & ST_UART011_CR_OVSFACT)
1804 *baud *= 2;
1805 }
1806 }
1807}
1808
1809static int __init pl011_console_setup(struct console *co, char *options)
1810{
1811 struct uart_amba_port *uap;
1812 int baud = 38400;
1813 int bits = 8;
1814 int parity = 'n';
1815 int flow = 'n';
1816 int ret;
1817
1818 /*
1819 * Check whether an invalid uart number has been specified, and
1820 * if so, search for the first available port that does have
1821 * console support.
1822 */
1823 if (co->index >= UART_NR)
1824 co->index = 0;
1825 uap = amba_ports[co->index];
1826 if (!uap)
1827 return -ENODEV;
1828
1829 /* Allow pins to be muxed in and configured */
1830 if (!IS_ERR(uap->pins_default)) {
1831 ret = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1832 if (ret)
1833 dev_err(uap->port.dev,
1834 "could not set default pins\n");
1835 }
1836
1837 ret = clk_prepare(uap->clk);
1838 if (ret)
1839 return ret;
1840
1841 if (uap->port.dev->platform_data) {
1842 struct amba_pl011_data *plat;
1843
1844 plat = uap->port.dev->platform_data;
1845 if (plat->init)
1846 plat->init();
1847 }
1848
1849 uap->port.uartclk = clk_get_rate(uap->clk);
1850
1851 if (options)
1852 uart_parse_options(options, &baud, &parity, &bits, &flow);
1853 else
1854 pl011_console_get_options(uap, &baud, &parity, &bits);
1855
1856 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1857}
1858
1859static struct uart_driver amba_reg;
1860static struct console amba_console = {
1861 .name = "ttyAMA",
1862 .write = pl011_console_write,
1863 .device = uart_console_device,
1864 .setup = pl011_console_setup,
1865 .flags = CON_PRINTBUFFER,
1866 .index = -1,
1867 .data = &amba_reg,
1868};
1869
1870#define AMBA_CONSOLE (&amba_console)
1871#else
1872#define AMBA_CONSOLE NULL
1873#endif
1874
1875static struct uart_driver amba_reg = {
1876 .owner = THIS_MODULE,
1877 .driver_name = "ttyAMA",
1878 .dev_name = "ttyAMA",
1879 .major = SERIAL_AMBA_MAJOR,
1880 .minor = SERIAL_AMBA_MINOR,
1881 .nr = UART_NR,
1882 .cons = AMBA_CONSOLE,
1883};
1884
1885static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1886{
1887 struct uart_amba_port *uap;
1888 struct vendor_data *vendor = id->data;
1889 void __iomem *base;
1890 int i, ret;
1891
1892 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1893 if (amba_ports[i] == NULL)
1894 break;
1895
1896 if (i == ARRAY_SIZE(amba_ports)) {
1897 ret = -EBUSY;
1898 goto out;
1899 }
1900
1901 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1902 if (uap == NULL) {
1903 ret = -ENOMEM;
1904 goto out;
1905 }
1906
1907 base = ioremap(dev->res.start, resource_size(&dev->res));
1908 if (!base) {
1909 ret = -ENOMEM;
1910 goto free;
1911 }
1912
1913 uap->pinctrl = devm_pinctrl_get(&dev->dev);
1914 if (IS_ERR(uap->pinctrl)) {
1915 ret = PTR_ERR(uap->pinctrl);
1916 goto unmap;
1917 }
1918 uap->pins_default = pinctrl_lookup_state(uap->pinctrl,
1919 PINCTRL_STATE_DEFAULT);
1920 if (IS_ERR(uap->pins_default))
1921 dev_err(&dev->dev, "could not get default pinstate\n");
1922
1923 uap->pins_sleep = pinctrl_lookup_state(uap->pinctrl,
1924 PINCTRL_STATE_SLEEP);
1925 if (IS_ERR(uap->pins_sleep))
1926 dev_dbg(&dev->dev, "could not get sleep pinstate\n");
1927
1928 uap->clk = clk_get(&dev->dev, NULL);
1929 if (IS_ERR(uap->clk)) {
1930 ret = PTR_ERR(uap->clk);
1931 goto unmap;
1932 }
1933
1934 uap->vendor = vendor;
1935 uap->lcrh_rx = vendor->lcrh_rx;
1936 uap->lcrh_tx = vendor->lcrh_tx;
1937 uap->old_cr = 0;
1938 uap->fifosize = vendor->fifosize;
1939 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1940 uap->port.dev = &dev->dev;
1941 uap->port.mapbase = dev->res.start;
1942 uap->port.membase = base;
1943 uap->port.iotype = UPIO_MEM;
1944 uap->port.irq = dev->irq[0];
1945 uap->port.fifosize = uap->fifosize;
1946 uap->port.ops = &amba_pl011_pops;
1947 uap->port.flags = UPF_BOOT_AUTOCONF;
1948 uap->port.line = i;
1949 pl011_dma_probe(uap);
1950
1951 /* Ensure interrupts from this UART are masked and cleared */
1952 writew(0, uap->port.membase + UART011_IMSC);
1953 writew(0xffff, uap->port.membase + UART011_ICR);
1954
1955 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1956
1957 amba_ports[i] = uap;
1958
1959 amba_set_drvdata(dev, uap);
1960 ret = uart_add_one_port(&amba_reg, &uap->port);
1961 if (ret) {
1962 amba_set_drvdata(dev, NULL);
1963 amba_ports[i] = NULL;
1964 pl011_dma_remove(uap);
1965 clk_put(uap->clk);
1966 unmap:
1967 iounmap(base);
1968 free:
1969 kfree(uap);
1970 }
1971 out:
1972 return ret;
1973}
1974
1975static int pl011_remove(struct amba_device *dev)
1976{
1977 struct uart_amba_port *uap = amba_get_drvdata(dev);
1978 int i;
1979
1980 amba_set_drvdata(dev, NULL);
1981
1982 uart_remove_one_port(&amba_reg, &uap->port);
1983
1984 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1985 if (amba_ports[i] == uap)
1986 amba_ports[i] = NULL;
1987
1988 pl011_dma_remove(uap);
1989 iounmap(uap->port.membase);
1990 clk_put(uap->clk);
1991 kfree(uap);
1992 return 0;
1993}
1994
1995#ifdef CONFIG_PM
1996static int pl011_suspend(struct amba_device *dev, pm_message_t state)
1997{
1998 struct uart_amba_port *uap = amba_get_drvdata(dev);
1999
2000 if (!uap)
2001 return -EINVAL;
2002
2003 return uart_suspend_port(&amba_reg, &uap->port);
2004}
2005
2006static int pl011_resume(struct amba_device *dev)
2007{
2008 struct uart_amba_port *uap = amba_get_drvdata(dev);
2009
2010 if (!uap)
2011 return -EINVAL;
2012
2013 return uart_resume_port(&amba_reg, &uap->port);
2014}
2015#endif
2016
2017static struct amba_id pl011_ids[] = {
2018 {
2019 .id = 0x00041011,
2020 .mask = 0x000fffff,
2021 .data = &vendor_arm,
2022 },
2023 {
2024 .id = 0x00380802,
2025 .mask = 0x00ffffff,
2026 .data = &vendor_st,
2027 },
2028 { 0, 0 },
2029};
2030
2031MODULE_DEVICE_TABLE(amba, pl011_ids);
2032
2033static struct amba_driver pl011_driver = {
2034 .drv = {
2035 .name = "uart-pl011",
2036 },
2037 .id_table = pl011_ids,
2038 .probe = pl011_probe,
2039 .remove = pl011_remove,
2040#ifdef CONFIG_PM
2041 .suspend = pl011_suspend,
2042 .resume = pl011_resume,
2043#endif
2044};
2045
2046static int __init pl011_init(void)
2047{
2048 int ret;
2049 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2050
2051 ret = uart_register_driver(&amba_reg);
2052 if (ret == 0) {
2053 ret = amba_driver_register(&pl011_driver);
2054 if (ret)
2055 uart_unregister_driver(&amba_reg);
2056 }
2057 return ret;
2058}
2059
2060static void __exit pl011_exit(void)
2061{
2062 amba_driver_unregister(&pl011_driver);
2063 uart_unregister_driver(&amba_reg);
2064}
2065
2066/*
2067 * While this can be a module, if builtin it's most likely the console
2068 * So let's leave module_exit but move module_init to an earlier place
2069 */
2070arch_initcall(pl011_init);
2071module_exit(pl011_exit);
2072
2073MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2074MODULE_DESCRIPTION("ARM AMBA serial port driver");
2075MODULE_LICENSE("GPL");