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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
4 *
5 * Copyright (c) 2000 Nils Faerber
6 *
7 * Based on rtc.c by Paul Gortmaker
8 *
9 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
10 *
11 * Modifications from:
12 * CIH <cih@coventive.com>
13 * Nicolas Pitre <nico@fluxnic.net>
14 * Andrew Christian <andrew.christian@hp.com>
15 *
16 * Converted to the RTC subsystem and Driver Model
17 * by Richard Purdie <rpurdie@rpsys.net>
18 */
19
20#include <linux/platform_device.h>
21#include <linux/module.h>
22#include <linux/clk.h>
23#include <linux/rtc.h>
24#include <linux/init.h>
25#include <linux/fs.h>
26#include <linux/interrupt.h>
27#include <linux/slab.h>
28#include <linux/string.h>
29#include <linux/of.h>
30#include <linux/pm.h>
31#include <linux/bitops.h>
32#include <linux/io.h>
33
34#define RTSR_HZE BIT(3) /* HZ interrupt enable */
35#define RTSR_ALE BIT(2) /* RTC alarm interrupt enable */
36#define RTSR_HZ BIT(1) /* HZ rising-edge detected */
37#define RTSR_AL BIT(0) /* RTC alarm detected */
38
39#include "rtc-sa1100.h"
40
41#define RTC_DEF_DIVIDER (32768 - 1)
42#define RTC_DEF_TRIM 0
43#define RTC_FREQ 1024
44
45
46static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
47{
48 struct sa1100_rtc *info = dev_get_drvdata(dev_id);
49 struct rtc_device *rtc = info->rtc;
50 unsigned int rtsr;
51 unsigned long events = 0;
52
53 spin_lock(&info->lock);
54
55 rtsr = readl_relaxed(info->rtsr);
56 /* clear interrupt sources */
57 writel_relaxed(0, info->rtsr);
58 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
59 * See also the comments in sa1100_rtc_probe(). */
60 if (rtsr & (RTSR_ALE | RTSR_HZE)) {
61 /* This is the original code, before there was the if test
62 * above. This code does not clear interrupts that were not
63 * enabled. */
64 writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr);
65 } else {
66 /* For some reason, it is possible to enter this routine
67 * without interruptions enabled, it has been tested with
68 * several units (Bug in SA11xx chip?).
69 *
70 * This situation leads to an infinite "loop" of interrupt
71 * routine calling and as a result the processor seems to
72 * lock on its first call to open(). */
73 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
74 }
75
76 /* clear alarm interrupt if it has occurred */
77 if (rtsr & RTSR_AL)
78 rtsr &= ~RTSR_ALE;
79 writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr);
80
81 /* update irq data & counter */
82 if (rtsr & RTSR_AL)
83 events |= RTC_AF | RTC_IRQF;
84 if (rtsr & RTSR_HZ)
85 events |= RTC_UF | RTC_IRQF;
86
87 rtc_update_irq(rtc, 1, events);
88
89 spin_unlock(&info->lock);
90
91 return IRQ_HANDLED;
92}
93
94static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
95{
96 u32 rtsr;
97 struct sa1100_rtc *info = dev_get_drvdata(dev);
98
99 spin_lock_irq(&info->lock);
100 rtsr = readl_relaxed(info->rtsr);
101 if (enabled)
102 rtsr |= RTSR_ALE;
103 else
104 rtsr &= ~RTSR_ALE;
105 writel_relaxed(rtsr, info->rtsr);
106 spin_unlock_irq(&info->lock);
107 return 0;
108}
109
110static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
111{
112 struct sa1100_rtc *info = dev_get_drvdata(dev);
113
114 rtc_time64_to_tm(readl_relaxed(info->rcnr), tm);
115 return 0;
116}
117
118static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
119{
120 struct sa1100_rtc *info = dev_get_drvdata(dev);
121
122 writel_relaxed(rtc_tm_to_time64(tm), info->rcnr);
123
124 return 0;
125}
126
127static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
128{
129 u32 rtsr;
130 struct sa1100_rtc *info = dev_get_drvdata(dev);
131
132 rtsr = readl_relaxed(info->rtsr);
133 alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
134 alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
135 return 0;
136}
137
138static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
139{
140 struct sa1100_rtc *info = dev_get_drvdata(dev);
141
142 spin_lock_irq(&info->lock);
143 writel_relaxed(readl_relaxed(info->rtsr) &
144 (RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr);
145 writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar);
146 if (alrm->enabled)
147 writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr);
148 else
149 writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr);
150 spin_unlock_irq(&info->lock);
151
152 return 0;
153}
154
155static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
156{
157 struct sa1100_rtc *info = dev_get_drvdata(dev);
158
159 seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr));
160 seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr));
161
162 return 0;
163}
164
165static const struct rtc_class_ops sa1100_rtc_ops = {
166 .read_time = sa1100_rtc_read_time,
167 .set_time = sa1100_rtc_set_time,
168 .read_alarm = sa1100_rtc_read_alarm,
169 .set_alarm = sa1100_rtc_set_alarm,
170 .proc = sa1100_rtc_proc,
171 .alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
172};
173
174int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info)
175{
176 int ret;
177
178 spin_lock_init(&info->lock);
179
180 info->clk = devm_clk_get(&pdev->dev, NULL);
181 if (IS_ERR(info->clk)) {
182 dev_err(&pdev->dev, "failed to find rtc clock source\n");
183 return PTR_ERR(info->clk);
184 }
185
186 ret = clk_prepare_enable(info->clk);
187 if (ret)
188 return ret;
189 /*
190 * According to the manual we should be able to let RTTR be zero
191 * and then a default diviser for a 32.768KHz clock is used.
192 * Apparently this doesn't work, at least for my SA1110 rev 5.
193 * If the clock divider is uninitialized then reset it to the
194 * default value to get the 1Hz clock.
195 */
196 if (readl_relaxed(info->rttr) == 0) {
197 writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr);
198 dev_warn(&pdev->dev, "warning: "
199 "initializing default clock divider/trim value\n");
200 /* The current RTC value probably doesn't make sense either */
201 writel_relaxed(0, info->rcnr);
202 }
203
204 info->rtc->ops = &sa1100_rtc_ops;
205 info->rtc->max_user_freq = RTC_FREQ;
206 info->rtc->range_max = U32_MAX;
207
208 ret = devm_rtc_register_device(info->rtc);
209 if (ret) {
210 clk_disable_unprepare(info->clk);
211 return ret;
212 }
213
214 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
215 * See also the comments in sa1100_rtc_interrupt().
216 *
217 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
218 * interrupt pending, even though interrupts were never enabled.
219 * In this case, this bit it must be reset before enabling
220 * interruptions to avoid a nonexistent interrupt to occur.
221 *
222 * In principle, the same problem would apply to bit 0, although it has
223 * never been observed to happen.
224 *
225 * This issue is addressed both here and in sa1100_rtc_interrupt().
226 * If the issue is not addressed here, in the times when the processor
227 * wakes up with the bit set there will be one spurious interrupt.
228 *
229 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
230 * safe side, once the condition that lead to this strange
231 * initialization is unknown and could in principle happen during
232 * normal processing.
233 *
234 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
235 * the corresponding bits in RTSR. */
236 writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
237
238 return 0;
239}
240EXPORT_SYMBOL_GPL(sa1100_rtc_init);
241
242static int sa1100_rtc_probe(struct platform_device *pdev)
243{
244 struct sa1100_rtc *info;
245 void __iomem *base;
246 int irq_1hz, irq_alarm;
247 int ret;
248
249 irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
250 irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
251 if (irq_1hz < 0 || irq_alarm < 0)
252 return -ENODEV;
253
254 info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL);
255 if (!info)
256 return -ENOMEM;
257 info->irq_1hz = irq_1hz;
258 info->irq_alarm = irq_alarm;
259
260 info->rtc = devm_rtc_allocate_device(&pdev->dev);
261 if (IS_ERR(info->rtc))
262 return PTR_ERR(info->rtc);
263
264 ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0,
265 "rtc 1Hz", &pdev->dev);
266 if (ret) {
267 dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz);
268 return ret;
269 }
270 ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0,
271 "rtc Alrm", &pdev->dev);
272 if (ret) {
273 dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm);
274 return ret;
275 }
276
277 base = devm_platform_ioremap_resource(pdev, 0);
278 if (IS_ERR(base))
279 return PTR_ERR(base);
280
281 if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
282 of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
283 info->rcnr = base + 0x04;
284 info->rtsr = base + 0x10;
285 info->rtar = base + 0x00;
286 info->rttr = base + 0x08;
287 } else {
288 info->rcnr = base + 0x0;
289 info->rtsr = base + 0x8;
290 info->rtar = base + 0x4;
291 info->rttr = base + 0xc;
292 }
293
294 platform_set_drvdata(pdev, info);
295 device_init_wakeup(&pdev->dev, 1);
296
297 return sa1100_rtc_init(pdev, info);
298}
299
300static int sa1100_rtc_remove(struct platform_device *pdev)
301{
302 struct sa1100_rtc *info = platform_get_drvdata(pdev);
303
304 if (info) {
305 spin_lock_irq(&info->lock);
306 writel_relaxed(0, info->rtsr);
307 spin_unlock_irq(&info->lock);
308 clk_disable_unprepare(info->clk);
309 }
310
311 return 0;
312}
313
314#ifdef CONFIG_PM_SLEEP
315static int sa1100_rtc_suspend(struct device *dev)
316{
317 struct sa1100_rtc *info = dev_get_drvdata(dev);
318 if (device_may_wakeup(dev))
319 enable_irq_wake(info->irq_alarm);
320 return 0;
321}
322
323static int sa1100_rtc_resume(struct device *dev)
324{
325 struct sa1100_rtc *info = dev_get_drvdata(dev);
326 if (device_may_wakeup(dev))
327 disable_irq_wake(info->irq_alarm);
328 return 0;
329}
330#endif
331
332static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend,
333 sa1100_rtc_resume);
334
335#ifdef CONFIG_OF
336static const struct of_device_id sa1100_rtc_dt_ids[] = {
337 { .compatible = "mrvl,sa1100-rtc", },
338 { .compatible = "mrvl,mmp-rtc", },
339 {}
340};
341MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
342#endif
343
344static struct platform_driver sa1100_rtc_driver = {
345 .probe = sa1100_rtc_probe,
346 .remove = sa1100_rtc_remove,
347 .driver = {
348 .name = "sa1100-rtc",
349 .pm = &sa1100_rtc_pm_ops,
350 .of_match_table = of_match_ptr(sa1100_rtc_dt_ids),
351 },
352};
353
354module_platform_driver(sa1100_rtc_driver);
355
356MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
357MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
358MODULE_LICENSE("GPL");
359MODULE_ALIAS("platform:sa1100-rtc");
1/*
2 * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
3 *
4 * Copyright (c) 2000 Nils Faerber
5 *
6 * Based on rtc.c by Paul Gortmaker
7 *
8 * Original Driver by Nils Faerber <nils@kernelconcepts.de>
9 *
10 * Modifications from:
11 * CIH <cih@coventive.com>
12 * Nicolas Pitre <nico@fluxnic.net>
13 * Andrew Christian <andrew.christian@hp.com>
14 *
15 * Converted to the RTC subsystem and Driver Model
16 * by Richard Purdie <rpurdie@rpsys.net>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
22 */
23
24#include <linux/platform_device.h>
25#include <linux/module.h>
26#include <linux/clk.h>
27#include <linux/rtc.h>
28#include <linux/init.h>
29#include <linux/fs.h>
30#include <linux/interrupt.h>
31#include <linux/slab.h>
32#include <linux/string.h>
33#include <linux/of.h>
34#include <linux/pm.h>
35#include <linux/bitops.h>
36#include <linux/io.h>
37
38#include <mach/hardware.h>
39#include <mach/irqs.h>
40
41#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
42#include <mach/regs-rtc.h>
43#endif
44
45#define RTC_DEF_DIVIDER (32768 - 1)
46#define RTC_DEF_TRIM 0
47#define RTC_FREQ 1024
48
49struct sa1100_rtc {
50 spinlock_t lock;
51 int irq_1hz;
52 int irq_alarm;
53 struct rtc_device *rtc;
54 struct clk *clk;
55};
56
57static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
58{
59 struct sa1100_rtc *info = dev_get_drvdata(dev_id);
60 struct rtc_device *rtc = info->rtc;
61 unsigned int rtsr;
62 unsigned long events = 0;
63
64 spin_lock(&info->lock);
65
66 rtsr = RTSR;
67 /* clear interrupt sources */
68 RTSR = 0;
69 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
70 * See also the comments in sa1100_rtc_probe(). */
71 if (rtsr & (RTSR_ALE | RTSR_HZE)) {
72 /* This is the original code, before there was the if test
73 * above. This code does not clear interrupts that were not
74 * enabled. */
75 RTSR = (RTSR_AL | RTSR_HZ) & (rtsr >> 2);
76 } else {
77 /* For some reason, it is possible to enter this routine
78 * without interruptions enabled, it has been tested with
79 * several units (Bug in SA11xx chip?).
80 *
81 * This situation leads to an infinite "loop" of interrupt
82 * routine calling and as a result the processor seems to
83 * lock on its first call to open(). */
84 RTSR = RTSR_AL | RTSR_HZ;
85 }
86
87 /* clear alarm interrupt if it has occurred */
88 if (rtsr & RTSR_AL)
89 rtsr &= ~RTSR_ALE;
90 RTSR = rtsr & (RTSR_ALE | RTSR_HZE);
91
92 /* update irq data & counter */
93 if (rtsr & RTSR_AL)
94 events |= RTC_AF | RTC_IRQF;
95 if (rtsr & RTSR_HZ)
96 events |= RTC_UF | RTC_IRQF;
97
98 rtc_update_irq(rtc, 1, events);
99
100 spin_unlock(&info->lock);
101
102 return IRQ_HANDLED;
103}
104
105static int sa1100_rtc_open(struct device *dev)
106{
107 struct sa1100_rtc *info = dev_get_drvdata(dev);
108 struct rtc_device *rtc = info->rtc;
109 int ret;
110
111 ret = clk_prepare_enable(info->clk);
112 if (ret)
113 goto fail_clk;
114 ret = request_irq(info->irq_1hz, sa1100_rtc_interrupt, 0, "rtc 1Hz", dev);
115 if (ret) {
116 dev_err(dev, "IRQ %d already in use.\n", info->irq_1hz);
117 goto fail_ui;
118 }
119 ret = request_irq(info->irq_alarm, sa1100_rtc_interrupt, 0, "rtc Alrm", dev);
120 if (ret) {
121 dev_err(dev, "IRQ %d already in use.\n", info->irq_alarm);
122 goto fail_ai;
123 }
124 rtc->max_user_freq = RTC_FREQ;
125 rtc_irq_set_freq(rtc, NULL, RTC_FREQ);
126
127 return 0;
128
129 fail_ai:
130 free_irq(info->irq_1hz, dev);
131 fail_ui:
132 clk_disable_unprepare(info->clk);
133 fail_clk:
134 return ret;
135}
136
137static void sa1100_rtc_release(struct device *dev)
138{
139 struct sa1100_rtc *info = dev_get_drvdata(dev);
140
141 spin_lock_irq(&info->lock);
142 RTSR = 0;
143 spin_unlock_irq(&info->lock);
144
145 free_irq(info->irq_alarm, dev);
146 free_irq(info->irq_1hz, dev);
147 clk_disable_unprepare(info->clk);
148}
149
150static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
151{
152 struct sa1100_rtc *info = dev_get_drvdata(dev);
153
154 spin_lock_irq(&info->lock);
155 if (enabled)
156 RTSR |= RTSR_ALE;
157 else
158 RTSR &= ~RTSR_ALE;
159 spin_unlock_irq(&info->lock);
160 return 0;
161}
162
163static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
164{
165 rtc_time_to_tm(RCNR, tm);
166 return 0;
167}
168
169static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
170{
171 unsigned long time;
172 int ret;
173
174 ret = rtc_tm_to_time(tm, &time);
175 if (ret == 0)
176 RCNR = time;
177 return ret;
178}
179
180static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
181{
182 u32 rtsr;
183
184 rtsr = RTSR;
185 alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
186 alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
187 return 0;
188}
189
190static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
191{
192 struct sa1100_rtc *info = dev_get_drvdata(dev);
193 unsigned long time;
194 int ret;
195
196 spin_lock_irq(&info->lock);
197 ret = rtc_tm_to_time(&alrm->time, &time);
198 if (ret != 0)
199 goto out;
200 RTSR = RTSR & (RTSR_HZE|RTSR_ALE|RTSR_AL);
201 RTAR = time;
202 if (alrm->enabled)
203 RTSR |= RTSR_ALE;
204 else
205 RTSR &= ~RTSR_ALE;
206out:
207 spin_unlock_irq(&info->lock);
208
209 return ret;
210}
211
212static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
213{
214 seq_printf(seq, "trim/divider\t\t: 0x%08x\n", (u32) RTTR);
215 seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", (u32)RTSR);
216
217 return 0;
218}
219
220static const struct rtc_class_ops sa1100_rtc_ops = {
221 .open = sa1100_rtc_open,
222 .release = sa1100_rtc_release,
223 .read_time = sa1100_rtc_read_time,
224 .set_time = sa1100_rtc_set_time,
225 .read_alarm = sa1100_rtc_read_alarm,
226 .set_alarm = sa1100_rtc_set_alarm,
227 .proc = sa1100_rtc_proc,
228 .alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
229};
230
231static int sa1100_rtc_probe(struct platform_device *pdev)
232{
233 struct rtc_device *rtc;
234 struct sa1100_rtc *info;
235 int irq_1hz, irq_alarm, ret = 0;
236
237 irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
238 irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
239 if (irq_1hz < 0 || irq_alarm < 0)
240 return -ENODEV;
241
242 info = kzalloc(sizeof(struct sa1100_rtc), GFP_KERNEL);
243 if (!info)
244 return -ENOMEM;
245 info->clk = clk_get(&pdev->dev, NULL);
246 if (IS_ERR(info->clk)) {
247 dev_err(&pdev->dev, "failed to find rtc clock source\n");
248 ret = PTR_ERR(info->clk);
249 goto err_clk;
250 }
251 info->irq_1hz = irq_1hz;
252 info->irq_alarm = irq_alarm;
253 spin_lock_init(&info->lock);
254 platform_set_drvdata(pdev, info);
255
256 /*
257 * According to the manual we should be able to let RTTR be zero
258 * and then a default diviser for a 32.768KHz clock is used.
259 * Apparently this doesn't work, at least for my SA1110 rev 5.
260 * If the clock divider is uninitialized then reset it to the
261 * default value to get the 1Hz clock.
262 */
263 if (RTTR == 0) {
264 RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
265 dev_warn(&pdev->dev, "warning: "
266 "initializing default clock divider/trim value\n");
267 /* The current RTC value probably doesn't make sense either */
268 RCNR = 0;
269 }
270
271 device_init_wakeup(&pdev->dev, 1);
272
273 rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops,
274 THIS_MODULE);
275
276 if (IS_ERR(rtc)) {
277 ret = PTR_ERR(rtc);
278 goto err_dev;
279 }
280 info->rtc = rtc;
281
282 /* Fix for a nasty initialization problem the in SA11xx RTSR register.
283 * See also the comments in sa1100_rtc_interrupt().
284 *
285 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
286 * interrupt pending, even though interrupts were never enabled.
287 * In this case, this bit it must be reset before enabling
288 * interruptions to avoid a nonexistent interrupt to occur.
289 *
290 * In principle, the same problem would apply to bit 0, although it has
291 * never been observed to happen.
292 *
293 * This issue is addressed both here and in sa1100_rtc_interrupt().
294 * If the issue is not addressed here, in the times when the processor
295 * wakes up with the bit set there will be one spurious interrupt.
296 *
297 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
298 * safe side, once the condition that lead to this strange
299 * initialization is unknown and could in principle happen during
300 * normal processing.
301 *
302 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
303 * the corresponding bits in RTSR. */
304 RTSR = RTSR_AL | RTSR_HZ;
305
306 return 0;
307err_dev:
308 platform_set_drvdata(pdev, NULL);
309 clk_put(info->clk);
310err_clk:
311 kfree(info);
312 return ret;
313}
314
315static int sa1100_rtc_remove(struct platform_device *pdev)
316{
317 struct sa1100_rtc *info = platform_get_drvdata(pdev);
318
319 if (info) {
320 rtc_device_unregister(info->rtc);
321 clk_put(info->clk);
322 platform_set_drvdata(pdev, NULL);
323 kfree(info);
324 }
325
326 return 0;
327}
328
329#ifdef CONFIG_PM
330static int sa1100_rtc_suspend(struct device *dev)
331{
332 struct sa1100_rtc *info = dev_get_drvdata(dev);
333 if (device_may_wakeup(dev))
334 enable_irq_wake(info->irq_alarm);
335 return 0;
336}
337
338static int sa1100_rtc_resume(struct device *dev)
339{
340 struct sa1100_rtc *info = dev_get_drvdata(dev);
341 if (device_may_wakeup(dev))
342 disable_irq_wake(info->irq_alarm);
343 return 0;
344}
345
346static const struct dev_pm_ops sa1100_rtc_pm_ops = {
347 .suspend = sa1100_rtc_suspend,
348 .resume = sa1100_rtc_resume,
349};
350#endif
351
352static struct of_device_id sa1100_rtc_dt_ids[] = {
353 { .compatible = "mrvl,sa1100-rtc", },
354 { .compatible = "mrvl,mmp-rtc", },
355 {}
356};
357MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
358
359static struct platform_driver sa1100_rtc_driver = {
360 .probe = sa1100_rtc_probe,
361 .remove = sa1100_rtc_remove,
362 .driver = {
363 .name = "sa1100-rtc",
364#ifdef CONFIG_PM
365 .pm = &sa1100_rtc_pm_ops,
366#endif
367 .of_match_table = sa1100_rtc_dt_ids,
368 },
369};
370
371module_platform_driver(sa1100_rtc_driver);
372
373MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
374MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
375MODULE_LICENSE("GPL");
376MODULE_ALIAS("platform:sa1100-rtc");