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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Allwinner sun4i USB phy driver
4 *
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
6 *
7 * Based on code from
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9 *
10 * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
11 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
12 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/extcon-provider.h>
19#include <linux/gpio/consumer.h>
20#include <linux/io.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/mutex.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_device.h>
28#include <linux/of_gpio.h>
29#include <linux/phy/phy.h>
30#include <linux/phy/phy-sun4i-usb.h>
31#include <linux/platform_device.h>
32#include <linux/power_supply.h>
33#include <linux/regulator/consumer.h>
34#include <linux/reset.h>
35#include <linux/spinlock.h>
36#include <linux/usb/of.h>
37#include <linux/workqueue.h>
38
39#define REG_ISCR 0x00
40#define REG_PHYCTL_A10 0x04
41#define REG_PHYBIST 0x08
42#define REG_PHYTUNE 0x0c
43#define REG_PHYCTL_A33 0x10
44#define REG_PHY_OTGCTL 0x20
45
46#define REG_HCI_PHY_CTL 0x10
47
48#define PHYCTL_DATA BIT(7)
49
50#define OTGCTL_ROUTE_MUSB BIT(0)
51
52#define SUNXI_AHB_ICHR8_EN BIT(10)
53#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
54#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
55#define SUNXI_ULPI_BYPASS_EN BIT(0)
56
57/* ISCR, Interface Status and Control bits */
58#define ISCR_ID_PULLUP_EN (1 << 17)
59#define ISCR_DPDM_PULLUP_EN (1 << 16)
60/* sunxi has the phy id/vbus pins not connected, so we use the force bits */
61#define ISCR_FORCE_ID_MASK (3 << 14)
62#define ISCR_FORCE_ID_LOW (2 << 14)
63#define ISCR_FORCE_ID_HIGH (3 << 14)
64#define ISCR_FORCE_VBUS_MASK (3 << 12)
65#define ISCR_FORCE_VBUS_LOW (2 << 12)
66#define ISCR_FORCE_VBUS_HIGH (3 << 12)
67
68/* Common Control Bits for Both PHYs */
69#define PHY_PLL_BW 0x03
70#define PHY_RES45_CAL_EN 0x0c
71
72/* Private Control Bits for Each PHY */
73#define PHY_TX_AMPLITUDE_TUNE 0x20
74#define PHY_TX_SLEWRATE_TUNE 0x22
75#define PHY_VBUSVALID_TH_SEL 0x25
76#define PHY_PULLUP_RES_SEL 0x27
77#define PHY_OTG_FUNC_EN 0x28
78#define PHY_VBUS_DET_EN 0x29
79#define PHY_DISCON_TH_SEL 0x2a
80#define PHY_SQUELCH_DETECT 0x3c
81
82/* A83T specific control bits for PHY0 */
83#define PHY_CTL_VBUSVLDEXT BIT(5)
84#define PHY_CTL_SIDDQ BIT(3)
85#define PHY_CTL_H3_SIDDQ BIT(1)
86
87/* A83T specific control bits for PHY2 HSIC */
88#define SUNXI_EHCI_HS_FORCE BIT(20)
89#define SUNXI_HSIC_CONNECT_DET BIT(17)
90#define SUNXI_HSIC_CONNECT_INT BIT(16)
91#define SUNXI_HSIC BIT(1)
92
93#define MAX_PHYS 4
94
95/*
96 * Note do not raise the debounce time, we must report Vusb high within 100ms
97 * otherwise we get Vbus errors
98 */
99#define DEBOUNCE_TIME msecs_to_jiffies(50)
100#define POLL_TIME msecs_to_jiffies(250)
101
102enum sun4i_usb_phy_type {
103 sun4i_a10_phy,
104 sun6i_a31_phy,
105 sun8i_a33_phy,
106 sun8i_a83t_phy,
107 sun8i_h3_phy,
108 sun8i_r40_phy,
109 sun8i_v3s_phy,
110 sun50i_a64_phy,
111 sun50i_h6_phy,
112};
113
114struct sun4i_usb_phy_cfg {
115 int num_phys;
116 int hsic_index;
117 enum sun4i_usb_phy_type type;
118 u32 disc_thresh;
119 u32 hci_phy_ctl_clear;
120 u8 phyctl_offset;
121 bool dedicated_clocks;
122 bool phy0_dual_route;
123 bool needs_phy2_siddq;
124 int missing_phys;
125};
126
127struct sun4i_usb_phy_data {
128 void __iomem *base;
129 const struct sun4i_usb_phy_cfg *cfg;
130 enum usb_dr_mode dr_mode;
131 spinlock_t reg_lock; /* guard access to phyctl reg */
132 struct sun4i_usb_phy {
133 struct phy *phy;
134 void __iomem *pmu;
135 struct regulator *vbus;
136 struct reset_control *reset;
137 struct clk *clk;
138 struct clk *clk2;
139 bool regulator_on;
140 int index;
141 } phys[MAX_PHYS];
142 /* phy0 / otg related variables */
143 struct extcon_dev *extcon;
144 bool phy0_init;
145 struct gpio_desc *id_det_gpio;
146 struct gpio_desc *vbus_det_gpio;
147 struct power_supply *vbus_power_supply;
148 struct notifier_block vbus_power_nb;
149 bool vbus_power_nb_registered;
150 bool force_session_end;
151 int id_det_irq;
152 int vbus_det_irq;
153 int id_det;
154 int vbus_det;
155 struct delayed_work detect;
156};
157
158#define to_sun4i_usb_phy_data(phy) \
159 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
160
161static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set)
162{
163 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
164 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
165 u32 iscr;
166
167 iscr = readl(data->base + REG_ISCR);
168 iscr &= ~clr;
169 iscr |= set;
170 writel(iscr, data->base + REG_ISCR);
171}
172
173static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val)
174{
175 if (val)
176 val = ISCR_FORCE_ID_HIGH;
177 else
178 val = ISCR_FORCE_ID_LOW;
179
180 sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_ID_MASK, val);
181}
182
183static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val)
184{
185 if (val)
186 val = ISCR_FORCE_VBUS_HIGH;
187 else
188 val = ISCR_FORCE_VBUS_LOW;
189
190 sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_VBUS_MASK, val);
191}
192
193static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
194 int len)
195{
196 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
197 u32 temp, usbc_bit = BIT(phy->index * 2);
198 void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
199 unsigned long flags;
200 int i;
201
202 spin_lock_irqsave(&phy_data->reg_lock, flags);
203
204 if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
205 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
206 writel(0, phyctl);
207 }
208
209 for (i = 0; i < len; i++) {
210 temp = readl(phyctl);
211
212 /* clear the address portion */
213 temp &= ~(0xff << 8);
214
215 /* set the address */
216 temp |= ((addr + i) << 8);
217 writel(temp, phyctl);
218
219 /* set the data bit and clear usbc bit*/
220 temp = readb(phyctl);
221 if (data & 0x1)
222 temp |= PHYCTL_DATA;
223 else
224 temp &= ~PHYCTL_DATA;
225 temp &= ~usbc_bit;
226 writeb(temp, phyctl);
227
228 /* pulse usbc_bit */
229 temp = readb(phyctl);
230 temp |= usbc_bit;
231 writeb(temp, phyctl);
232
233 temp = readb(phyctl);
234 temp &= ~usbc_bit;
235 writeb(temp, phyctl);
236
237 data >>= 1;
238 }
239
240 spin_unlock_irqrestore(&phy_data->reg_lock, flags);
241}
242
243static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
244{
245 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
246 u32 bits, reg_value;
247
248 if (!phy->pmu)
249 return;
250
251 bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
252 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
253
254 /* A83T USB2 is HSIC */
255 if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
256 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
257 SUNXI_HSIC;
258
259 reg_value = readl(phy->pmu);
260
261 if (enable)
262 reg_value |= bits;
263 else
264 reg_value &= ~bits;
265
266 writel(reg_value, phy->pmu);
267}
268
269static int sun4i_usb_phy_init(struct phy *_phy)
270{
271 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
272 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
273 int ret;
274 u32 val;
275
276 ret = clk_prepare_enable(phy->clk);
277 if (ret)
278 return ret;
279
280 ret = clk_prepare_enable(phy->clk2);
281 if (ret) {
282 clk_disable_unprepare(phy->clk);
283 return ret;
284 }
285
286 ret = reset_control_deassert(phy->reset);
287 if (ret) {
288 clk_disable_unprepare(phy->clk2);
289 clk_disable_unprepare(phy->clk);
290 return ret;
291 }
292
293 /* Some PHYs on some SoCs need the help of PHY2 to work. */
294 if (data->cfg->needs_phy2_siddq && phy->index != 2) {
295 struct sun4i_usb_phy *phy2 = &data->phys[2];
296
297 ret = clk_prepare_enable(phy2->clk);
298 if (ret) {
299 reset_control_assert(phy->reset);
300 clk_disable_unprepare(phy->clk2);
301 clk_disable_unprepare(phy->clk);
302 return ret;
303 }
304
305 ret = reset_control_deassert(phy2->reset);
306 if (ret) {
307 clk_disable_unprepare(phy2->clk);
308 reset_control_assert(phy->reset);
309 clk_disable_unprepare(phy->clk2);
310 clk_disable_unprepare(phy->clk);
311 return ret;
312 }
313
314 /*
315 * This extra clock is just needed to access the
316 * REG_HCI_PHY_CTL PMU register for PHY2.
317 */
318 ret = clk_prepare_enable(phy2->clk2);
319 if (ret) {
320 reset_control_assert(phy2->reset);
321 clk_disable_unprepare(phy2->clk);
322 reset_control_assert(phy->reset);
323 clk_disable_unprepare(phy->clk2);
324 clk_disable_unprepare(phy->clk);
325 return ret;
326 }
327
328 if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
329 val = readl(phy2->pmu + REG_HCI_PHY_CTL);
330 val &= ~data->cfg->hci_phy_ctl_clear;
331 writel(val, phy2->pmu + REG_HCI_PHY_CTL);
332 }
333
334 clk_disable_unprepare(phy->clk2);
335 }
336
337 if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
338 val = readl(phy->pmu + REG_HCI_PHY_CTL);
339 val &= ~data->cfg->hci_phy_ctl_clear;
340 writel(val, phy->pmu + REG_HCI_PHY_CTL);
341 }
342
343 if (data->cfg->type == sun8i_a83t_phy ||
344 data->cfg->type == sun50i_h6_phy) {
345 if (phy->index == 0) {
346 val = readl(data->base + data->cfg->phyctl_offset);
347 val |= PHY_CTL_VBUSVLDEXT;
348 val &= ~PHY_CTL_SIDDQ;
349 writel(val, data->base + data->cfg->phyctl_offset);
350 }
351 } else {
352 /* Enable USB 45 Ohm resistor calibration */
353 if (phy->index == 0)
354 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
355
356 /* Adjust PHY's magnitude and rate */
357 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
358
359 /* Disconnect threshold adjustment */
360 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
361 data->cfg->disc_thresh, 2);
362 }
363
364 sun4i_usb_phy_passby(phy, 1);
365
366 if (phy->index == 0) {
367 data->phy0_init = true;
368
369 /* Enable pull-ups */
370 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
371 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
372
373 /* Force ISCR and cable state updates */
374 data->id_det = -1;
375 data->vbus_det = -1;
376 queue_delayed_work(system_wq, &data->detect, 0);
377 }
378
379 return 0;
380}
381
382static int sun4i_usb_phy_exit(struct phy *_phy)
383{
384 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
385 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
386
387 if (phy->index == 0) {
388 if (data->cfg->type == sun8i_a83t_phy ||
389 data->cfg->type == sun50i_h6_phy) {
390 void __iomem *phyctl = data->base +
391 data->cfg->phyctl_offset;
392
393 writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
394 }
395
396 /* Disable pull-ups */
397 sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
398 sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
399 data->phy0_init = false;
400 }
401
402 if (data->cfg->needs_phy2_siddq && phy->index != 2) {
403 struct sun4i_usb_phy *phy2 = &data->phys[2];
404
405 clk_disable_unprepare(phy2->clk);
406 reset_control_assert(phy2->reset);
407 }
408
409 sun4i_usb_phy_passby(phy, 0);
410 reset_control_assert(phy->reset);
411 clk_disable_unprepare(phy->clk2);
412 clk_disable_unprepare(phy->clk);
413
414 return 0;
415}
416
417static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
418{
419 switch (data->dr_mode) {
420 case USB_DR_MODE_OTG:
421 if (data->id_det_gpio)
422 return gpiod_get_value_cansleep(data->id_det_gpio);
423 else
424 return 1; /* Fallback to peripheral mode */
425 case USB_DR_MODE_HOST:
426 return 0;
427 case USB_DR_MODE_PERIPHERAL:
428 default:
429 return 1;
430 }
431}
432
433static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
434{
435 if (data->vbus_det_gpio)
436 return gpiod_get_value_cansleep(data->vbus_det_gpio);
437
438 if (data->vbus_power_supply) {
439 union power_supply_propval val;
440 int r;
441
442 r = power_supply_get_property(data->vbus_power_supply,
443 POWER_SUPPLY_PROP_PRESENT, &val);
444 if (r == 0)
445 return val.intval;
446 }
447
448 /* Fallback: report vbus as high */
449 return 1;
450}
451
452static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
453{
454 return data->vbus_det_gpio || data->vbus_power_supply;
455}
456
457static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
458{
459 if ((data->id_det_gpio && data->id_det_irq <= 0) ||
460 (data->vbus_det_gpio && data->vbus_det_irq <= 0))
461 return true;
462
463 /*
464 * The A31/A23/A33 companion pmics (AXP221/AXP223) do not
465 * generate vbus change interrupts when the board is driving
466 * vbus using the N_VBUSEN pin on the pmic, so we must poll
467 * when using the pmic for vbus-det _and_ we're driving vbus.
468 */
469 if ((data->cfg->type == sun6i_a31_phy ||
470 data->cfg->type == sun8i_a33_phy) &&
471 data->vbus_power_supply && data->phys[0].regulator_on)
472 return true;
473
474 return false;
475}
476
477static int sun4i_usb_phy_power_on(struct phy *_phy)
478{
479 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
480 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
481 int ret;
482
483 if (!phy->vbus || phy->regulator_on)
484 return 0;
485
486 /* For phy0 only turn on Vbus if we don't have an ext. Vbus */
487 if (phy->index == 0 && sun4i_usb_phy0_have_vbus_det(data) &&
488 data->vbus_det) {
489 dev_warn(&_phy->dev, "External vbus detected, not enabling our own vbus\n");
490 return 0;
491 }
492
493 ret = regulator_enable(phy->vbus);
494 if (ret)
495 return ret;
496
497 phy->regulator_on = true;
498
499 /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */
500 if (phy->index == 0 && sun4i_usb_phy0_poll(data))
501 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
502
503 return 0;
504}
505
506static int sun4i_usb_phy_power_off(struct phy *_phy)
507{
508 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
509 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
510
511 if (!phy->vbus || !phy->regulator_on)
512 return 0;
513
514 regulator_disable(phy->vbus);
515 phy->regulator_on = false;
516
517 /*
518 * phy0 vbus typically slowly discharges, sometimes this causes the
519 * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan.
520 */
521 if (phy->index == 0 && !sun4i_usb_phy0_poll(data))
522 mod_delayed_work(system_wq, &data->detect, POLL_TIME);
523
524 return 0;
525}
526
527static int sun4i_usb_phy_set_mode(struct phy *_phy,
528 enum phy_mode mode, int submode)
529{
530 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
531 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
532 int new_mode;
533
534 if (phy->index != 0) {
535 if (mode == PHY_MODE_USB_HOST)
536 return 0;
537 return -EINVAL;
538 }
539
540 switch (mode) {
541 case PHY_MODE_USB_HOST:
542 new_mode = USB_DR_MODE_HOST;
543 break;
544 case PHY_MODE_USB_DEVICE:
545 new_mode = USB_DR_MODE_PERIPHERAL;
546 break;
547 case PHY_MODE_USB_OTG:
548 new_mode = USB_DR_MODE_OTG;
549 break;
550 default:
551 return -EINVAL;
552 }
553
554 if (new_mode != data->dr_mode) {
555 dev_info(&_phy->dev, "Changing dr_mode to %d\n", new_mode);
556 data->dr_mode = new_mode;
557 }
558
559 data->id_det = -1; /* Force reprocessing of id */
560 data->force_session_end = true;
561 queue_delayed_work(system_wq, &data->detect, 0);
562
563 return 0;
564}
565
566void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
567{
568 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
569
570 sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
571}
572EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
573
574static const struct phy_ops sun4i_usb_phy_ops = {
575 .init = sun4i_usb_phy_init,
576 .exit = sun4i_usb_phy_exit,
577 .power_on = sun4i_usb_phy_power_on,
578 .power_off = sun4i_usb_phy_power_off,
579 .set_mode = sun4i_usb_phy_set_mode,
580 .owner = THIS_MODULE,
581};
582
583static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
584{
585 u32 regval;
586
587 regval = readl(data->base + REG_PHY_OTGCTL);
588 if (id_det == 0) {
589 /* Host mode. Route phy0 to EHCI/OHCI */
590 regval &= ~OTGCTL_ROUTE_MUSB;
591 } else {
592 /* Peripheral mode. Route phy0 to MUSB */
593 regval |= OTGCTL_ROUTE_MUSB;
594 }
595 writel(regval, data->base + REG_PHY_OTGCTL);
596}
597
598static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
599{
600 struct sun4i_usb_phy_data *data =
601 container_of(work, struct sun4i_usb_phy_data, detect.work);
602 struct phy *phy0 = data->phys[0].phy;
603 struct sun4i_usb_phy *phy;
604 bool force_session_end, id_notify = false, vbus_notify = false;
605 int id_det, vbus_det;
606
607 if (!phy0)
608 return;
609
610 phy = phy_get_drvdata(phy0);
611 id_det = sun4i_usb_phy0_get_id_det(data);
612 vbus_det = sun4i_usb_phy0_get_vbus_det(data);
613
614 mutex_lock(&phy0->mutex);
615
616 if (!data->phy0_init) {
617 mutex_unlock(&phy0->mutex);
618 return;
619 }
620
621 force_session_end = data->force_session_end;
622 data->force_session_end = false;
623
624 if (id_det != data->id_det) {
625 /* id-change, force session end if we've no vbus detection */
626 if (data->dr_mode == USB_DR_MODE_OTG &&
627 !sun4i_usb_phy0_have_vbus_det(data))
628 force_session_end = true;
629
630 /* When entering host mode (id = 0) force end the session now */
631 if (force_session_end && id_det == 0) {
632 sun4i_usb_phy0_set_vbus_detect(phy0, 0);
633 msleep(200);
634 sun4i_usb_phy0_set_vbus_detect(phy0, 1);
635 }
636 sun4i_usb_phy0_set_id_detect(phy0, id_det);
637 data->id_det = id_det;
638 id_notify = true;
639 }
640
641 if (vbus_det != data->vbus_det) {
642 sun4i_usb_phy0_set_vbus_detect(phy0, vbus_det);
643 data->vbus_det = vbus_det;
644 vbus_notify = true;
645 }
646
647 mutex_unlock(&phy0->mutex);
648
649 if (id_notify) {
650 extcon_set_state_sync(data->extcon, EXTCON_USB_HOST,
651 !id_det);
652 /* When leaving host mode force end the session here */
653 if (force_session_end && id_det == 1) {
654 mutex_lock(&phy0->mutex);
655 sun4i_usb_phy0_set_vbus_detect(phy0, 0);
656 msleep(1000);
657 sun4i_usb_phy0_set_vbus_detect(phy0, 1);
658 mutex_unlock(&phy0->mutex);
659 }
660
661 /* Enable PHY0 passby for host mode only. */
662 sun4i_usb_phy_passby(phy, !id_det);
663
664 /* Re-route PHY0 if necessary */
665 if (data->cfg->phy0_dual_route)
666 sun4i_usb_phy0_reroute(data, id_det);
667 }
668
669 if (vbus_notify)
670 extcon_set_state_sync(data->extcon, EXTCON_USB, vbus_det);
671
672 if (sun4i_usb_phy0_poll(data))
673 queue_delayed_work(system_wq, &data->detect, POLL_TIME);
674}
675
676static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id)
677{
678 struct sun4i_usb_phy_data *data = dev_id;
679
680 /* vbus or id changed, let the pins settle and then scan them */
681 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
682
683 return IRQ_HANDLED;
684}
685
686static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb,
687 unsigned long val, void *v)
688{
689 struct sun4i_usb_phy_data *data =
690 container_of(nb, struct sun4i_usb_phy_data, vbus_power_nb);
691 struct power_supply *psy = v;
692
693 /* Properties on the vbus_power_supply changed, scan vbus_det */
694 if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply)
695 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
696
697 return NOTIFY_OK;
698}
699
700static struct phy *sun4i_usb_phy_xlate(struct device *dev,
701 struct of_phandle_args *args)
702{
703 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
704
705 if (args->args[0] >= data->cfg->num_phys)
706 return ERR_PTR(-ENODEV);
707
708 if (data->cfg->missing_phys & BIT(args->args[0]))
709 return ERR_PTR(-ENODEV);
710
711 return data->phys[args->args[0]].phy;
712}
713
714static int sun4i_usb_phy_remove(struct platform_device *pdev)
715{
716 struct device *dev = &pdev->dev;
717 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
718
719 if (data->vbus_power_nb_registered)
720 power_supply_unreg_notifier(&data->vbus_power_nb);
721 if (data->id_det_irq > 0)
722 devm_free_irq(dev, data->id_det_irq, data);
723 if (data->vbus_det_irq > 0)
724 devm_free_irq(dev, data->vbus_det_irq, data);
725
726 cancel_delayed_work_sync(&data->detect);
727
728 return 0;
729}
730
731static const unsigned int sun4i_usb_phy0_cable[] = {
732 EXTCON_USB,
733 EXTCON_USB_HOST,
734 EXTCON_NONE,
735};
736
737static int sun4i_usb_phy_probe(struct platform_device *pdev)
738{
739 struct sun4i_usb_phy_data *data;
740 struct device *dev = &pdev->dev;
741 struct device_node *np = dev->of_node;
742 struct phy_provider *phy_provider;
743 int i, ret;
744
745 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
746 if (!data)
747 return -ENOMEM;
748
749 spin_lock_init(&data->reg_lock);
750 INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
751 dev_set_drvdata(dev, data);
752 data->cfg = of_device_get_match_data(dev);
753 if (!data->cfg)
754 return -EINVAL;
755
756 data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
757 if (IS_ERR(data->base))
758 return PTR_ERR(data->base);
759
760 data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
761 GPIOD_IN);
762 if (IS_ERR(data->id_det_gpio)) {
763 dev_err(dev, "Couldn't request ID GPIO\n");
764 return PTR_ERR(data->id_det_gpio);
765 }
766
767 data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
768 GPIOD_IN);
769 if (IS_ERR(data->vbus_det_gpio)) {
770 dev_err(dev, "Couldn't request VBUS detect GPIO\n");
771 return PTR_ERR(data->vbus_det_gpio);
772 }
773
774 if (of_find_property(np, "usb0_vbus_power-supply", NULL)) {
775 data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
776 "usb0_vbus_power-supply");
777 if (IS_ERR(data->vbus_power_supply)) {
778 dev_err(dev, "Couldn't get the VBUS power supply\n");
779 return PTR_ERR(data->vbus_power_supply);
780 }
781
782 if (!data->vbus_power_supply)
783 return -EPROBE_DEFER;
784 }
785
786 data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
787
788 data->extcon = devm_extcon_dev_allocate(dev, sun4i_usb_phy0_cable);
789 if (IS_ERR(data->extcon)) {
790 dev_err(dev, "Couldn't allocate our extcon device\n");
791 return PTR_ERR(data->extcon);
792 }
793
794 ret = devm_extcon_dev_register(dev, data->extcon);
795 if (ret) {
796 dev_err(dev, "failed to register extcon: %d\n", ret);
797 return ret;
798 }
799
800 for (i = 0; i < data->cfg->num_phys; i++) {
801 struct sun4i_usb_phy *phy = data->phys + i;
802 char name[16];
803
804 if (data->cfg->missing_phys & BIT(i))
805 continue;
806
807 snprintf(name, sizeof(name), "usb%d_vbus", i);
808 phy->vbus = devm_regulator_get_optional(dev, name);
809 if (IS_ERR(phy->vbus)) {
810 if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
811 dev_err(dev,
812 "Couldn't get regulator %s... Deferring probe\n",
813 name);
814 return -EPROBE_DEFER;
815 }
816
817 phy->vbus = NULL;
818 }
819
820 if (data->cfg->dedicated_clocks)
821 snprintf(name, sizeof(name), "usb%d_phy", i);
822 else
823 strscpy(name, "usb_phy", sizeof(name));
824
825 phy->clk = devm_clk_get(dev, name);
826 if (IS_ERR(phy->clk)) {
827 dev_err(dev, "failed to get clock %s\n", name);
828 return PTR_ERR(phy->clk);
829 }
830
831 /* The first PHY is always tied to OTG, and never HSIC */
832 if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
833 /* HSIC needs secondary clock */
834 snprintf(name, sizeof(name), "usb%d_hsic_12M", i);
835 phy->clk2 = devm_clk_get(dev, name);
836 if (IS_ERR(phy->clk2)) {
837 dev_err(dev, "failed to get clock %s\n", name);
838 return PTR_ERR(phy->clk2);
839 }
840 } else {
841 snprintf(name, sizeof(name), "pmu%d_clk", i);
842 phy->clk2 = devm_clk_get_optional(dev, name);
843 if (IS_ERR(phy->clk2)) {
844 dev_err(dev, "failed to get clock %s\n", name);
845 return PTR_ERR(phy->clk2);
846 }
847 }
848
849 snprintf(name, sizeof(name), "usb%d_reset", i);
850 phy->reset = devm_reset_control_get(dev, name);
851 if (IS_ERR(phy->reset)) {
852 dev_err(dev, "failed to get reset %s\n", name);
853 return PTR_ERR(phy->reset);
854 }
855
856 if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
857 snprintf(name, sizeof(name), "pmu%d", i);
858 phy->pmu = devm_platform_ioremap_resource_byname(pdev, name);
859 if (IS_ERR(phy->pmu))
860 return PTR_ERR(phy->pmu);
861 }
862
863 phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops);
864 if (IS_ERR(phy->phy)) {
865 dev_err(dev, "failed to create PHY %d\n", i);
866 return PTR_ERR(phy->phy);
867 }
868
869 phy->index = i;
870 phy_set_drvdata(phy->phy, &data->phys[i]);
871 }
872
873 data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
874 if (data->id_det_irq > 0) {
875 ret = devm_request_irq(dev, data->id_det_irq,
876 sun4i_usb_phy0_id_vbus_det_irq,
877 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
878 "usb0-id-det", data);
879 if (ret) {
880 dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
881 return ret;
882 }
883 }
884
885 data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
886 if (data->vbus_det_irq > 0) {
887 ret = devm_request_irq(dev, data->vbus_det_irq,
888 sun4i_usb_phy0_id_vbus_det_irq,
889 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
890 "usb0-vbus-det", data);
891 if (ret) {
892 dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
893 data->vbus_det_irq = -1;
894 sun4i_usb_phy_remove(pdev); /* Stop detect work */
895 return ret;
896 }
897 }
898
899 if (data->vbus_power_supply) {
900 data->vbus_power_nb.notifier_call = sun4i_usb_phy0_vbus_notify;
901 data->vbus_power_nb.priority = 0;
902 ret = power_supply_reg_notifier(&data->vbus_power_nb);
903 if (ret) {
904 sun4i_usb_phy_remove(pdev); /* Stop detect work */
905 return ret;
906 }
907 data->vbus_power_nb_registered = true;
908 }
909
910 phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
911 if (IS_ERR(phy_provider)) {
912 sun4i_usb_phy_remove(pdev); /* Stop detect work */
913 return PTR_ERR(phy_provider);
914 }
915
916 dev_dbg(dev, "successfully loaded\n");
917
918 return 0;
919}
920
921static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
922 .num_phys = 3,
923 .type = sun4i_a10_phy,
924 .disc_thresh = 3,
925 .phyctl_offset = REG_PHYCTL_A10,
926 .dedicated_clocks = false,
927};
928
929static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
930 .num_phys = 2,
931 .type = sun4i_a10_phy,
932 .disc_thresh = 2,
933 .phyctl_offset = REG_PHYCTL_A10,
934 .dedicated_clocks = false,
935};
936
937static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
938 .num_phys = 3,
939 .type = sun6i_a31_phy,
940 .disc_thresh = 3,
941 .phyctl_offset = REG_PHYCTL_A10,
942 .dedicated_clocks = true,
943};
944
945static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
946 .num_phys = 3,
947 .type = sun4i_a10_phy,
948 .disc_thresh = 2,
949 .phyctl_offset = REG_PHYCTL_A10,
950 .dedicated_clocks = false,
951};
952
953static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
954 .num_phys = 2,
955 .type = sun6i_a31_phy,
956 .disc_thresh = 3,
957 .phyctl_offset = REG_PHYCTL_A10,
958 .dedicated_clocks = true,
959};
960
961static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
962 .num_phys = 2,
963 .type = sun8i_a33_phy,
964 .disc_thresh = 3,
965 .phyctl_offset = REG_PHYCTL_A33,
966 .dedicated_clocks = true,
967};
968
969static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
970 .num_phys = 3,
971 .hsic_index = 2,
972 .type = sun8i_a83t_phy,
973 .phyctl_offset = REG_PHYCTL_A33,
974 .dedicated_clocks = true,
975};
976
977static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
978 .num_phys = 4,
979 .type = sun8i_h3_phy,
980 .disc_thresh = 3,
981 .phyctl_offset = REG_PHYCTL_A33,
982 .dedicated_clocks = true,
983 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
984 .phy0_dual_route = true,
985};
986
987static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
988 .num_phys = 3,
989 .type = sun8i_r40_phy,
990 .disc_thresh = 3,
991 .phyctl_offset = REG_PHYCTL_A33,
992 .dedicated_clocks = true,
993 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
994 .phy0_dual_route = true,
995};
996
997static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
998 .num_phys = 1,
999 .type = sun8i_v3s_phy,
1000 .disc_thresh = 3,
1001 .phyctl_offset = REG_PHYCTL_A33,
1002 .dedicated_clocks = true,
1003 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
1004 .phy0_dual_route = true,
1005};
1006
1007static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
1008 .num_phys = 2,
1009 .type = sun50i_h6_phy,
1010 .phyctl_offset = REG_PHYCTL_A33,
1011 .dedicated_clocks = true,
1012 .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1013 .phy0_dual_route = true,
1014};
1015
1016static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
1017 .num_phys = 2,
1018 .type = sun50i_a64_phy,
1019 .disc_thresh = 3,
1020 .phyctl_offset = REG_PHYCTL_A33,
1021 .dedicated_clocks = true,
1022 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
1023 .phy0_dual_route = true,
1024};
1025
1026static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
1027 .num_phys = 4,
1028 .type = sun50i_h6_phy,
1029 .phyctl_offset = REG_PHYCTL_A33,
1030 .dedicated_clocks = true,
1031 .phy0_dual_route = true,
1032 .missing_phys = BIT(1) | BIT(2),
1033};
1034
1035static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
1036 .num_phys = 4,
1037 .type = sun50i_h6_phy,
1038 .disc_thresh = 3,
1039 .phyctl_offset = REG_PHYCTL_A33,
1040 .dedicated_clocks = true,
1041 .phy0_dual_route = true,
1042 .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1043 .needs_phy2_siddq = true,
1044};
1045
1046static const struct of_device_id sun4i_usb_phy_of_match[] = {
1047 { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
1048 { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
1049 { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
1050 { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
1051 { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
1052 { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
1053 { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
1054 { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
1055 { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg },
1056 { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
1057 { .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg },
1058 { .compatible = "allwinner,sun50i-a64-usb-phy",
1059 .data = &sun50i_a64_cfg},
1060 { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
1061 { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
1062 { },
1063};
1064MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
1065
1066static struct platform_driver sun4i_usb_phy_driver = {
1067 .probe = sun4i_usb_phy_probe,
1068 .remove = sun4i_usb_phy_remove,
1069 .driver = {
1070 .of_match_table = sun4i_usb_phy_of_match,
1071 .name = "sun4i-usb-phy",
1072 }
1073};
1074module_platform_driver(sun4i_usb_phy_driver);
1075
1076MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
1077MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
1078MODULE_LICENSE("GPL v2");