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1// SPDX-License-Identifier: BSD-3-Clause
2/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
3 * Microchip VCAP API
4 */
5
6/* This file is autogenerated by cml-utils 2022-10-13 10:04:41 +0200.
7 * Commit ID: fd7cafd175899f0672c73afb3a30fc872500ae86
8 */
9
10#include <linux/types.h>
11#include <linux/kernel.h>
12
13#include "vcap_api.h"
14#include "sparx5_vcap_ag_api.h"
15
16/* keyfields */
17static const struct vcap_field is2_mac_etype_keyfield[] = {
18 [VCAP_KF_TYPE] = {
19 .type = VCAP_FIELD_U32,
20 .offset = 0,
21 .width = 4,
22 },
23 [VCAP_KF_LOOKUP_FIRST_IS] = {
24 .type = VCAP_FIELD_BIT,
25 .offset = 4,
26 .width = 1,
27 },
28 [VCAP_KF_LOOKUP_PAG] = {
29 .type = VCAP_FIELD_U32,
30 .offset = 5,
31 .width = 8,
32 },
33 [VCAP_KF_IF_IGR_PORT_MASK_L3] = {
34 .type = VCAP_FIELD_BIT,
35 .offset = 13,
36 .width = 1,
37 },
38 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
39 .type = VCAP_FIELD_U32,
40 .offset = 14,
41 .width = 4,
42 },
43 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
44 .type = VCAP_FIELD_U32,
45 .offset = 18,
46 .width = 2,
47 },
48 [VCAP_KF_IF_IGR_PORT_MASK] = {
49 .type = VCAP_FIELD_U32,
50 .offset = 20,
51 .width = 32,
52 },
53 [VCAP_KF_L2_MC_IS] = {
54 .type = VCAP_FIELD_BIT,
55 .offset = 52,
56 .width = 1,
57 },
58 [VCAP_KF_L2_BC_IS] = {
59 .type = VCAP_FIELD_BIT,
60 .offset = 53,
61 .width = 1,
62 },
63 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
64 .type = VCAP_FIELD_BIT,
65 .offset = 54,
66 .width = 1,
67 },
68 [VCAP_KF_ISDX_GT0_IS] = {
69 .type = VCAP_FIELD_BIT,
70 .offset = 55,
71 .width = 1,
72 },
73 [VCAP_KF_ISDX_CLS] = {
74 .type = VCAP_FIELD_U32,
75 .offset = 56,
76 .width = 12,
77 },
78 [VCAP_KF_8021Q_VID_CLS] = {
79 .type = VCAP_FIELD_U32,
80 .offset = 68,
81 .width = 13,
82 },
83 [VCAP_KF_8021Q_DEI_CLS] = {
84 .type = VCAP_FIELD_BIT,
85 .offset = 81,
86 .width = 1,
87 },
88 [VCAP_KF_8021Q_PCP_CLS] = {
89 .type = VCAP_FIELD_U32,
90 .offset = 82,
91 .width = 3,
92 },
93 [VCAP_KF_L2_FWD_IS] = {
94 .type = VCAP_FIELD_BIT,
95 .offset = 85,
96 .width = 1,
97 },
98 [VCAP_KF_L3_RT_IS] = {
99 .type = VCAP_FIELD_BIT,
100 .offset = 88,
101 .width = 1,
102 },
103 [VCAP_KF_L3_DST_IS] = {
104 .type = VCAP_FIELD_BIT,
105 .offset = 89,
106 .width = 1,
107 },
108 [VCAP_KF_L2_DMAC] = {
109 .type = VCAP_FIELD_U48,
110 .offset = 90,
111 .width = 48,
112 },
113 [VCAP_KF_L2_SMAC] = {
114 .type = VCAP_FIELD_U48,
115 .offset = 138,
116 .width = 48,
117 },
118 [VCAP_KF_ETYPE_LEN_IS] = {
119 .type = VCAP_FIELD_BIT,
120 .offset = 186,
121 .width = 1,
122 },
123 [VCAP_KF_ETYPE] = {
124 .type = VCAP_FIELD_U32,
125 .offset = 187,
126 .width = 16,
127 },
128 [VCAP_KF_L2_PAYLOAD_ETYPE] = {
129 .type = VCAP_FIELD_U64,
130 .offset = 203,
131 .width = 64,
132 },
133 [VCAP_KF_L4_RNG] = {
134 .type = VCAP_FIELD_U32,
135 .offset = 267,
136 .width = 16,
137 },
138 [VCAP_KF_OAM_CCM_CNTS_EQ0] = {
139 .type = VCAP_FIELD_BIT,
140 .offset = 283,
141 .width = 1,
142 },
143 [VCAP_KF_OAM_Y1731_IS] = {
144 .type = VCAP_FIELD_BIT,
145 .offset = 284,
146 .width = 1,
147 },
148};
149
150static const struct vcap_field is2_arp_keyfield[] = {
151 [VCAP_KF_TYPE] = {
152 .type = VCAP_FIELD_U32,
153 .offset = 0,
154 .width = 4,
155 },
156 [VCAP_KF_LOOKUP_FIRST_IS] = {
157 .type = VCAP_FIELD_BIT,
158 .offset = 4,
159 .width = 1,
160 },
161 [VCAP_KF_LOOKUP_PAG] = {
162 .type = VCAP_FIELD_U32,
163 .offset = 5,
164 .width = 8,
165 },
166 [VCAP_KF_IF_IGR_PORT_MASK_L3] = {
167 .type = VCAP_FIELD_BIT,
168 .offset = 13,
169 .width = 1,
170 },
171 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
172 .type = VCAP_FIELD_U32,
173 .offset = 14,
174 .width = 4,
175 },
176 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
177 .type = VCAP_FIELD_U32,
178 .offset = 18,
179 .width = 2,
180 },
181 [VCAP_KF_IF_IGR_PORT_MASK] = {
182 .type = VCAP_FIELD_U32,
183 .offset = 20,
184 .width = 32,
185 },
186 [VCAP_KF_L2_MC_IS] = {
187 .type = VCAP_FIELD_BIT,
188 .offset = 52,
189 .width = 1,
190 },
191 [VCAP_KF_L2_BC_IS] = {
192 .type = VCAP_FIELD_BIT,
193 .offset = 53,
194 .width = 1,
195 },
196 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
197 .type = VCAP_FIELD_BIT,
198 .offset = 54,
199 .width = 1,
200 },
201 [VCAP_KF_ISDX_GT0_IS] = {
202 .type = VCAP_FIELD_BIT,
203 .offset = 55,
204 .width = 1,
205 },
206 [VCAP_KF_ISDX_CLS] = {
207 .type = VCAP_FIELD_U32,
208 .offset = 56,
209 .width = 12,
210 },
211 [VCAP_KF_8021Q_VID_CLS] = {
212 .type = VCAP_FIELD_U32,
213 .offset = 68,
214 .width = 13,
215 },
216 [VCAP_KF_8021Q_DEI_CLS] = {
217 .type = VCAP_FIELD_BIT,
218 .offset = 81,
219 .width = 1,
220 },
221 [VCAP_KF_8021Q_PCP_CLS] = {
222 .type = VCAP_FIELD_U32,
223 .offset = 82,
224 .width = 3,
225 },
226 [VCAP_KF_L2_FWD_IS] = {
227 .type = VCAP_FIELD_BIT,
228 .offset = 85,
229 .width = 1,
230 },
231 [VCAP_KF_L2_SMAC] = {
232 .type = VCAP_FIELD_U48,
233 .offset = 86,
234 .width = 48,
235 },
236 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
237 .type = VCAP_FIELD_BIT,
238 .offset = 134,
239 .width = 1,
240 },
241 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
242 .type = VCAP_FIELD_BIT,
243 .offset = 135,
244 .width = 1,
245 },
246 [VCAP_KF_ARP_LEN_OK_IS] = {
247 .type = VCAP_FIELD_BIT,
248 .offset = 136,
249 .width = 1,
250 },
251 [VCAP_KF_ARP_TGT_MATCH_IS] = {
252 .type = VCAP_FIELD_BIT,
253 .offset = 137,
254 .width = 1,
255 },
256 [VCAP_KF_ARP_SENDER_MATCH_IS] = {
257 .type = VCAP_FIELD_BIT,
258 .offset = 138,
259 .width = 1,
260 },
261 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
262 .type = VCAP_FIELD_BIT,
263 .offset = 139,
264 .width = 1,
265 },
266 [VCAP_KF_ARP_OPCODE] = {
267 .type = VCAP_FIELD_U32,
268 .offset = 140,
269 .width = 2,
270 },
271 [VCAP_KF_L3_IP4_DIP] = {
272 .type = VCAP_FIELD_U32,
273 .offset = 142,
274 .width = 32,
275 },
276 [VCAP_KF_L3_IP4_SIP] = {
277 .type = VCAP_FIELD_U32,
278 .offset = 174,
279 .width = 32,
280 },
281 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
282 .type = VCAP_FIELD_BIT,
283 .offset = 206,
284 .width = 1,
285 },
286 [VCAP_KF_L4_RNG] = {
287 .type = VCAP_FIELD_U32,
288 .offset = 207,
289 .width = 16,
290 },
291};
292
293static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {
294 [VCAP_KF_TYPE] = {
295 .type = VCAP_FIELD_U32,
296 .offset = 0,
297 .width = 4,
298 },
299 [VCAP_KF_LOOKUP_FIRST_IS] = {
300 .type = VCAP_FIELD_BIT,
301 .offset = 4,
302 .width = 1,
303 },
304 [VCAP_KF_LOOKUP_PAG] = {
305 .type = VCAP_FIELD_U32,
306 .offset = 5,
307 .width = 8,
308 },
309 [VCAP_KF_IF_IGR_PORT_MASK_L3] = {
310 .type = VCAP_FIELD_BIT,
311 .offset = 13,
312 .width = 1,
313 },
314 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
315 .type = VCAP_FIELD_U32,
316 .offset = 14,
317 .width = 4,
318 },
319 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
320 .type = VCAP_FIELD_U32,
321 .offset = 18,
322 .width = 2,
323 },
324 [VCAP_KF_IF_IGR_PORT_MASK] = {
325 .type = VCAP_FIELD_U32,
326 .offset = 20,
327 .width = 32,
328 },
329 [VCAP_KF_L2_MC_IS] = {
330 .type = VCAP_FIELD_BIT,
331 .offset = 52,
332 .width = 1,
333 },
334 [VCAP_KF_L2_BC_IS] = {
335 .type = VCAP_FIELD_BIT,
336 .offset = 53,
337 .width = 1,
338 },
339 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
340 .type = VCAP_FIELD_BIT,
341 .offset = 54,
342 .width = 1,
343 },
344 [VCAP_KF_ISDX_GT0_IS] = {
345 .type = VCAP_FIELD_BIT,
346 .offset = 55,
347 .width = 1,
348 },
349 [VCAP_KF_ISDX_CLS] = {
350 .type = VCAP_FIELD_U32,
351 .offset = 56,
352 .width = 12,
353 },
354 [VCAP_KF_8021Q_VID_CLS] = {
355 .type = VCAP_FIELD_U32,
356 .offset = 68,
357 .width = 13,
358 },
359 [VCAP_KF_8021Q_DEI_CLS] = {
360 .type = VCAP_FIELD_BIT,
361 .offset = 81,
362 .width = 1,
363 },
364 [VCAP_KF_8021Q_PCP_CLS] = {
365 .type = VCAP_FIELD_U32,
366 .offset = 82,
367 .width = 3,
368 },
369 [VCAP_KF_L2_FWD_IS] = {
370 .type = VCAP_FIELD_BIT,
371 .offset = 85,
372 .width = 1,
373 },
374 [VCAP_KF_L3_RT_IS] = {
375 .type = VCAP_FIELD_BIT,
376 .offset = 88,
377 .width = 1,
378 },
379 [VCAP_KF_L3_DST_IS] = {
380 .type = VCAP_FIELD_BIT,
381 .offset = 89,
382 .width = 1,
383 },
384 [VCAP_KF_IP4_IS] = {
385 .type = VCAP_FIELD_BIT,
386 .offset = 90,
387 .width = 1,
388 },
389 [VCAP_KF_L3_FRAGMENT_TYPE] = {
390 .type = VCAP_FIELD_U32,
391 .offset = 91,
392 .width = 2,
393 },
394 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
395 .type = VCAP_FIELD_BIT,
396 .offset = 93,
397 .width = 1,
398 },
399 [VCAP_KF_L3_OPTIONS_IS] = {
400 .type = VCAP_FIELD_BIT,
401 .offset = 94,
402 .width = 1,
403 },
404 [VCAP_KF_L3_TTL_GT0] = {
405 .type = VCAP_FIELD_BIT,
406 .offset = 95,
407 .width = 1,
408 },
409 [VCAP_KF_L3_TOS] = {
410 .type = VCAP_FIELD_U32,
411 .offset = 96,
412 .width = 8,
413 },
414 [VCAP_KF_L3_IP4_DIP] = {
415 .type = VCAP_FIELD_U32,
416 .offset = 104,
417 .width = 32,
418 },
419 [VCAP_KF_L3_IP4_SIP] = {
420 .type = VCAP_FIELD_U32,
421 .offset = 136,
422 .width = 32,
423 },
424 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
425 .type = VCAP_FIELD_BIT,
426 .offset = 168,
427 .width = 1,
428 },
429 [VCAP_KF_TCP_IS] = {
430 .type = VCAP_FIELD_BIT,
431 .offset = 169,
432 .width = 1,
433 },
434 [VCAP_KF_L4_DPORT] = {
435 .type = VCAP_FIELD_U32,
436 .offset = 170,
437 .width = 16,
438 },
439 [VCAP_KF_L4_SPORT] = {
440 .type = VCAP_FIELD_U32,
441 .offset = 186,
442 .width = 16,
443 },
444 [VCAP_KF_L4_RNG] = {
445 .type = VCAP_FIELD_U32,
446 .offset = 202,
447 .width = 16,
448 },
449 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
450 .type = VCAP_FIELD_BIT,
451 .offset = 218,
452 .width = 1,
453 },
454 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
455 .type = VCAP_FIELD_BIT,
456 .offset = 219,
457 .width = 1,
458 },
459 [VCAP_KF_L4_FIN] = {
460 .type = VCAP_FIELD_BIT,
461 .offset = 220,
462 .width = 1,
463 },
464 [VCAP_KF_L4_SYN] = {
465 .type = VCAP_FIELD_BIT,
466 .offset = 221,
467 .width = 1,
468 },
469 [VCAP_KF_L4_RST] = {
470 .type = VCAP_FIELD_BIT,
471 .offset = 222,
472 .width = 1,
473 },
474 [VCAP_KF_L4_PSH] = {
475 .type = VCAP_FIELD_BIT,
476 .offset = 223,
477 .width = 1,
478 },
479 [VCAP_KF_L4_ACK] = {
480 .type = VCAP_FIELD_BIT,
481 .offset = 224,
482 .width = 1,
483 },
484 [VCAP_KF_L4_URG] = {
485 .type = VCAP_FIELD_BIT,
486 .offset = 225,
487 .width = 1,
488 },
489 [VCAP_KF_L4_PAYLOAD] = {
490 .type = VCAP_FIELD_U64,
491 .offset = 226,
492 .width = 64,
493 },
494};
495
496static const struct vcap_field is2_ip4_other_keyfield[] = {
497 [VCAP_KF_TYPE] = {
498 .type = VCAP_FIELD_U32,
499 .offset = 0,
500 .width = 4,
501 },
502 [VCAP_KF_LOOKUP_FIRST_IS] = {
503 .type = VCAP_FIELD_BIT,
504 .offset = 4,
505 .width = 1,
506 },
507 [VCAP_KF_LOOKUP_PAG] = {
508 .type = VCAP_FIELD_U32,
509 .offset = 5,
510 .width = 8,
511 },
512 [VCAP_KF_IF_IGR_PORT_MASK_L3] = {
513 .type = VCAP_FIELD_BIT,
514 .offset = 13,
515 .width = 1,
516 },
517 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
518 .type = VCAP_FIELD_U32,
519 .offset = 14,
520 .width = 4,
521 },
522 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
523 .type = VCAP_FIELD_U32,
524 .offset = 18,
525 .width = 2,
526 },
527 [VCAP_KF_IF_IGR_PORT_MASK] = {
528 .type = VCAP_FIELD_U32,
529 .offset = 20,
530 .width = 32,
531 },
532 [VCAP_KF_L2_MC_IS] = {
533 .type = VCAP_FIELD_BIT,
534 .offset = 52,
535 .width = 1,
536 },
537 [VCAP_KF_L2_BC_IS] = {
538 .type = VCAP_FIELD_BIT,
539 .offset = 53,
540 .width = 1,
541 },
542 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
543 .type = VCAP_FIELD_BIT,
544 .offset = 54,
545 .width = 1,
546 },
547 [VCAP_KF_ISDX_GT0_IS] = {
548 .type = VCAP_FIELD_BIT,
549 .offset = 55,
550 .width = 1,
551 },
552 [VCAP_KF_ISDX_CLS] = {
553 .type = VCAP_FIELD_U32,
554 .offset = 56,
555 .width = 12,
556 },
557 [VCAP_KF_8021Q_VID_CLS] = {
558 .type = VCAP_FIELD_U32,
559 .offset = 68,
560 .width = 13,
561 },
562 [VCAP_KF_8021Q_DEI_CLS] = {
563 .type = VCAP_FIELD_BIT,
564 .offset = 81,
565 .width = 1,
566 },
567 [VCAP_KF_8021Q_PCP_CLS] = {
568 .type = VCAP_FIELD_U32,
569 .offset = 82,
570 .width = 3,
571 },
572 [VCAP_KF_L2_FWD_IS] = {
573 .type = VCAP_FIELD_BIT,
574 .offset = 85,
575 .width = 1,
576 },
577 [VCAP_KF_L3_RT_IS] = {
578 .type = VCAP_FIELD_BIT,
579 .offset = 88,
580 .width = 1,
581 },
582 [VCAP_KF_L3_DST_IS] = {
583 .type = VCAP_FIELD_BIT,
584 .offset = 89,
585 .width = 1,
586 },
587 [VCAP_KF_IP4_IS] = {
588 .type = VCAP_FIELD_BIT,
589 .offset = 90,
590 .width = 1,
591 },
592 [VCAP_KF_L3_FRAGMENT_TYPE] = {
593 .type = VCAP_FIELD_U32,
594 .offset = 91,
595 .width = 2,
596 },
597 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
598 .type = VCAP_FIELD_BIT,
599 .offset = 93,
600 .width = 1,
601 },
602 [VCAP_KF_L3_OPTIONS_IS] = {
603 .type = VCAP_FIELD_BIT,
604 .offset = 94,
605 .width = 1,
606 },
607 [VCAP_KF_L3_TTL_GT0] = {
608 .type = VCAP_FIELD_BIT,
609 .offset = 95,
610 .width = 1,
611 },
612 [VCAP_KF_L3_TOS] = {
613 .type = VCAP_FIELD_U32,
614 .offset = 96,
615 .width = 8,
616 },
617 [VCAP_KF_L3_IP4_DIP] = {
618 .type = VCAP_FIELD_U32,
619 .offset = 104,
620 .width = 32,
621 },
622 [VCAP_KF_L3_IP4_SIP] = {
623 .type = VCAP_FIELD_U32,
624 .offset = 136,
625 .width = 32,
626 },
627 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
628 .type = VCAP_FIELD_BIT,
629 .offset = 168,
630 .width = 1,
631 },
632 [VCAP_KF_L3_IP_PROTO] = {
633 .type = VCAP_FIELD_U32,
634 .offset = 169,
635 .width = 8,
636 },
637 [VCAP_KF_L4_RNG] = {
638 .type = VCAP_FIELD_U32,
639 .offset = 177,
640 .width = 16,
641 },
642 [VCAP_KF_L3_PAYLOAD] = {
643 .type = VCAP_FIELD_U112,
644 .offset = 193,
645 .width = 96,
646 },
647};
648
649static const struct vcap_field is2_ip6_std_keyfield[] = {
650 [VCAP_KF_TYPE] = {
651 .type = VCAP_FIELD_U32,
652 .offset = 0,
653 .width = 4,
654 },
655 [VCAP_KF_LOOKUP_FIRST_IS] = {
656 .type = VCAP_FIELD_BIT,
657 .offset = 4,
658 .width = 1,
659 },
660 [VCAP_KF_LOOKUP_PAG] = {
661 .type = VCAP_FIELD_U32,
662 .offset = 5,
663 .width = 8,
664 },
665 [VCAP_KF_IF_IGR_PORT_MASK_L3] = {
666 .type = VCAP_FIELD_BIT,
667 .offset = 13,
668 .width = 1,
669 },
670 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
671 .type = VCAP_FIELD_U32,
672 .offset = 14,
673 .width = 4,
674 },
675 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
676 .type = VCAP_FIELD_U32,
677 .offset = 18,
678 .width = 2,
679 },
680 [VCAP_KF_IF_IGR_PORT_MASK] = {
681 .type = VCAP_FIELD_U32,
682 .offset = 20,
683 .width = 32,
684 },
685 [VCAP_KF_L2_MC_IS] = {
686 .type = VCAP_FIELD_BIT,
687 .offset = 52,
688 .width = 1,
689 },
690 [VCAP_KF_L2_BC_IS] = {
691 .type = VCAP_FIELD_BIT,
692 .offset = 53,
693 .width = 1,
694 },
695 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
696 .type = VCAP_FIELD_BIT,
697 .offset = 54,
698 .width = 1,
699 },
700 [VCAP_KF_ISDX_GT0_IS] = {
701 .type = VCAP_FIELD_BIT,
702 .offset = 55,
703 .width = 1,
704 },
705 [VCAP_KF_ISDX_CLS] = {
706 .type = VCAP_FIELD_U32,
707 .offset = 56,
708 .width = 12,
709 },
710 [VCAP_KF_8021Q_VID_CLS] = {
711 .type = VCAP_FIELD_U32,
712 .offset = 68,
713 .width = 13,
714 },
715 [VCAP_KF_8021Q_DEI_CLS] = {
716 .type = VCAP_FIELD_BIT,
717 .offset = 81,
718 .width = 1,
719 },
720 [VCAP_KF_8021Q_PCP_CLS] = {
721 .type = VCAP_FIELD_U32,
722 .offset = 82,
723 .width = 3,
724 },
725 [VCAP_KF_L2_FWD_IS] = {
726 .type = VCAP_FIELD_BIT,
727 .offset = 85,
728 .width = 1,
729 },
730 [VCAP_KF_L3_RT_IS] = {
731 .type = VCAP_FIELD_BIT,
732 .offset = 88,
733 .width = 1,
734 },
735 [VCAP_KF_L3_TTL_GT0] = {
736 .type = VCAP_FIELD_BIT,
737 .offset = 90,
738 .width = 1,
739 },
740 [VCAP_KF_L3_IP6_SIP] = {
741 .type = VCAP_FIELD_U128,
742 .offset = 91,
743 .width = 128,
744 },
745 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
746 .type = VCAP_FIELD_BIT,
747 .offset = 219,
748 .width = 1,
749 },
750 [VCAP_KF_L3_IP_PROTO] = {
751 .type = VCAP_FIELD_U32,
752 .offset = 220,
753 .width = 8,
754 },
755 [VCAP_KF_L4_RNG] = {
756 .type = VCAP_FIELD_U32,
757 .offset = 228,
758 .width = 16,
759 },
760 [VCAP_KF_L3_PAYLOAD] = {
761 .type = VCAP_FIELD_U48,
762 .offset = 244,
763 .width = 40,
764 },
765};
766
767static const struct vcap_field is2_ip_7tuple_keyfield[] = {
768 [VCAP_KF_TYPE] = {
769 .type = VCAP_FIELD_U32,
770 .offset = 0,
771 .width = 2,
772 },
773 [VCAP_KF_LOOKUP_FIRST_IS] = {
774 .type = VCAP_FIELD_BIT,
775 .offset = 2,
776 .width = 1,
777 },
778 [VCAP_KF_LOOKUP_PAG] = {
779 .type = VCAP_FIELD_U32,
780 .offset = 3,
781 .width = 8,
782 },
783 [VCAP_KF_IF_IGR_PORT_MASK_L3] = {
784 .type = VCAP_FIELD_BIT,
785 .offset = 11,
786 .width = 1,
787 },
788 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
789 .type = VCAP_FIELD_U32,
790 .offset = 12,
791 .width = 4,
792 },
793 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
794 .type = VCAP_FIELD_U32,
795 .offset = 16,
796 .width = 2,
797 },
798 [VCAP_KF_IF_IGR_PORT_MASK] = {
799 .type = VCAP_FIELD_U72,
800 .offset = 18,
801 .width = 65,
802 },
803 [VCAP_KF_L2_MC_IS] = {
804 .type = VCAP_FIELD_BIT,
805 .offset = 83,
806 .width = 1,
807 },
808 [VCAP_KF_L2_BC_IS] = {
809 .type = VCAP_FIELD_BIT,
810 .offset = 84,
811 .width = 1,
812 },
813 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
814 .type = VCAP_FIELD_BIT,
815 .offset = 85,
816 .width = 1,
817 },
818 [VCAP_KF_ISDX_GT0_IS] = {
819 .type = VCAP_FIELD_BIT,
820 .offset = 86,
821 .width = 1,
822 },
823 [VCAP_KF_ISDX_CLS] = {
824 .type = VCAP_FIELD_U32,
825 .offset = 87,
826 .width = 12,
827 },
828 [VCAP_KF_8021Q_VID_CLS] = {
829 .type = VCAP_FIELD_U32,
830 .offset = 99,
831 .width = 13,
832 },
833 [VCAP_KF_8021Q_DEI_CLS] = {
834 .type = VCAP_FIELD_BIT,
835 .offset = 112,
836 .width = 1,
837 },
838 [VCAP_KF_8021Q_PCP_CLS] = {
839 .type = VCAP_FIELD_U32,
840 .offset = 113,
841 .width = 3,
842 },
843 [VCAP_KF_L2_FWD_IS] = {
844 .type = VCAP_FIELD_BIT,
845 .offset = 116,
846 .width = 1,
847 },
848 [VCAP_KF_L3_RT_IS] = {
849 .type = VCAP_FIELD_BIT,
850 .offset = 119,
851 .width = 1,
852 },
853 [VCAP_KF_L3_DST_IS] = {
854 .type = VCAP_FIELD_BIT,
855 .offset = 120,
856 .width = 1,
857 },
858 [VCAP_KF_L2_DMAC] = {
859 .type = VCAP_FIELD_U48,
860 .offset = 121,
861 .width = 48,
862 },
863 [VCAP_KF_L2_SMAC] = {
864 .type = VCAP_FIELD_U48,
865 .offset = 169,
866 .width = 48,
867 },
868 [VCAP_KF_IP4_IS] = {
869 .type = VCAP_FIELD_BIT,
870 .offset = 217,
871 .width = 1,
872 },
873 [VCAP_KF_L3_TTL_GT0] = {
874 .type = VCAP_FIELD_BIT,
875 .offset = 218,
876 .width = 1,
877 },
878 [VCAP_KF_L3_TOS] = {
879 .type = VCAP_FIELD_U32,
880 .offset = 219,
881 .width = 8,
882 },
883 [VCAP_KF_L3_IP6_DIP] = {
884 .type = VCAP_FIELD_U128,
885 .offset = 227,
886 .width = 128,
887 },
888 [VCAP_KF_L3_IP6_SIP] = {
889 .type = VCAP_FIELD_U128,
890 .offset = 355,
891 .width = 128,
892 },
893 [VCAP_KF_L3_DIP_EQ_SIP_IS] = {
894 .type = VCAP_FIELD_BIT,
895 .offset = 483,
896 .width = 1,
897 },
898 [VCAP_KF_TCP_UDP_IS] = {
899 .type = VCAP_FIELD_BIT,
900 .offset = 484,
901 .width = 1,
902 },
903 [VCAP_KF_TCP_IS] = {
904 .type = VCAP_FIELD_BIT,
905 .offset = 485,
906 .width = 1,
907 },
908 [VCAP_KF_L4_DPORT] = {
909 .type = VCAP_FIELD_U32,
910 .offset = 486,
911 .width = 16,
912 },
913 [VCAP_KF_L4_SPORT] = {
914 .type = VCAP_FIELD_U32,
915 .offset = 502,
916 .width = 16,
917 },
918 [VCAP_KF_L4_RNG] = {
919 .type = VCAP_FIELD_U32,
920 .offset = 518,
921 .width = 16,
922 },
923 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
924 .type = VCAP_FIELD_BIT,
925 .offset = 534,
926 .width = 1,
927 },
928 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
929 .type = VCAP_FIELD_BIT,
930 .offset = 535,
931 .width = 1,
932 },
933 [VCAP_KF_L4_FIN] = {
934 .type = VCAP_FIELD_BIT,
935 .offset = 536,
936 .width = 1,
937 },
938 [VCAP_KF_L4_SYN] = {
939 .type = VCAP_FIELD_BIT,
940 .offset = 537,
941 .width = 1,
942 },
943 [VCAP_KF_L4_RST] = {
944 .type = VCAP_FIELD_BIT,
945 .offset = 538,
946 .width = 1,
947 },
948 [VCAP_KF_L4_PSH] = {
949 .type = VCAP_FIELD_BIT,
950 .offset = 539,
951 .width = 1,
952 },
953 [VCAP_KF_L4_ACK] = {
954 .type = VCAP_FIELD_BIT,
955 .offset = 540,
956 .width = 1,
957 },
958 [VCAP_KF_L4_URG] = {
959 .type = VCAP_FIELD_BIT,
960 .offset = 541,
961 .width = 1,
962 },
963 [VCAP_KF_L4_PAYLOAD] = {
964 .type = VCAP_FIELD_U64,
965 .offset = 542,
966 .width = 64,
967 },
968};
969
970/* keyfield_set */
971static const struct vcap_set is2_keyfield_set[] = {
972 [VCAP_KFS_MAC_ETYPE] = {
973 .type_id = 0,
974 .sw_per_item = 6,
975 .sw_cnt = 2,
976 },
977 [VCAP_KFS_ARP] = {
978 .type_id = 3,
979 .sw_per_item = 6,
980 .sw_cnt = 2,
981 },
982 [VCAP_KFS_IP4_TCP_UDP] = {
983 .type_id = 4,
984 .sw_per_item = 6,
985 .sw_cnt = 2,
986 },
987 [VCAP_KFS_IP4_OTHER] = {
988 .type_id = 5,
989 .sw_per_item = 6,
990 .sw_cnt = 2,
991 },
992 [VCAP_KFS_IP6_STD] = {
993 .type_id = 6,
994 .sw_per_item = 6,
995 .sw_cnt = 2,
996 },
997 [VCAP_KFS_IP_7TUPLE] = {
998 .type_id = 1,
999 .sw_per_item = 12,
1000 .sw_cnt = 1,
1001 },
1002};
1003
1004/* keyfield_set map */
1005static const struct vcap_field *is2_keyfield_set_map[] = {
1006 [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,
1007 [VCAP_KFS_ARP] = is2_arp_keyfield,
1008 [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,
1009 [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,
1010 [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,
1011 [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield,
1012};
1013
1014/* keyfield_set map sizes */
1015static int is2_keyfield_set_map_size[] = {
1016 [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),
1017 [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),
1018 [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),
1019 [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),
1020 [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),
1021 [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield),
1022};
1023
1024/* actionfields */
1025static const struct vcap_field is2_base_type_actionfield[] = {
1026 [VCAP_AF_PIPELINE_FORCE_ENA] = {
1027 .type = VCAP_FIELD_BIT,
1028 .offset = 1,
1029 .width = 1,
1030 },
1031 [VCAP_AF_PIPELINE_PT] = {
1032 .type = VCAP_FIELD_U32,
1033 .offset = 2,
1034 .width = 5,
1035 },
1036 [VCAP_AF_HIT_ME_ONCE] = {
1037 .type = VCAP_FIELD_BIT,
1038 .offset = 7,
1039 .width = 1,
1040 },
1041 [VCAP_AF_INTR_ENA] = {
1042 .type = VCAP_FIELD_BIT,
1043 .offset = 8,
1044 .width = 1,
1045 },
1046 [VCAP_AF_CPU_COPY_ENA] = {
1047 .type = VCAP_FIELD_BIT,
1048 .offset = 9,
1049 .width = 1,
1050 },
1051 [VCAP_AF_CPU_QUEUE_NUM] = {
1052 .type = VCAP_FIELD_U32,
1053 .offset = 10,
1054 .width = 3,
1055 },
1056 [VCAP_AF_LRN_DIS] = {
1057 .type = VCAP_FIELD_BIT,
1058 .offset = 14,
1059 .width = 1,
1060 },
1061 [VCAP_AF_RT_DIS] = {
1062 .type = VCAP_FIELD_BIT,
1063 .offset = 15,
1064 .width = 1,
1065 },
1066 [VCAP_AF_POLICE_ENA] = {
1067 .type = VCAP_FIELD_BIT,
1068 .offset = 16,
1069 .width = 1,
1070 },
1071 [VCAP_AF_POLICE_IDX] = {
1072 .type = VCAP_FIELD_U32,
1073 .offset = 17,
1074 .width = 6,
1075 },
1076 [VCAP_AF_IGNORE_PIPELINE_CTRL] = {
1077 .type = VCAP_FIELD_BIT,
1078 .offset = 23,
1079 .width = 1,
1080 },
1081 [VCAP_AF_MASK_MODE] = {
1082 .type = VCAP_FIELD_U32,
1083 .offset = 27,
1084 .width = 3,
1085 },
1086 [VCAP_AF_PORT_MASK] = {
1087 .type = VCAP_FIELD_U72,
1088 .offset = 30,
1089 .width = 68,
1090 },
1091 [VCAP_AF_MIRROR_PROBE] = {
1092 .type = VCAP_FIELD_U32,
1093 .offset = 111,
1094 .width = 2,
1095 },
1096 [VCAP_AF_MATCH_ID] = {
1097 .type = VCAP_FIELD_U32,
1098 .offset = 159,
1099 .width = 16,
1100 },
1101 [VCAP_AF_MATCH_ID_MASK] = {
1102 .type = VCAP_FIELD_U32,
1103 .offset = 175,
1104 .width = 16,
1105 },
1106 [VCAP_AF_CNT_ID] = {
1107 .type = VCAP_FIELD_U32,
1108 .offset = 191,
1109 .width = 12,
1110 },
1111};
1112
1113/* actionfield_set */
1114static const struct vcap_set is2_actionfield_set[] = {
1115 [VCAP_AFS_BASE_TYPE] = {
1116 .type_id = -1,
1117 .sw_per_item = 3,
1118 .sw_cnt = 4,
1119 },
1120};
1121
1122/* actionfield_set map */
1123static const struct vcap_field *is2_actionfield_set_map[] = {
1124 [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,
1125};
1126
1127/* actionfield_set map size */
1128static int is2_actionfield_set_map_size[] = {
1129 [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),
1130};
1131
1132/* Type Groups */
1133static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = {
1134 {
1135 .offset = 0,
1136 .width = 3,
1137 .value = 4,
1138 },
1139 {
1140 .offset = 156,
1141 .width = 1,
1142 .value = 0,
1143 },
1144 {
1145 .offset = 312,
1146 .width = 2,
1147 .value = 0,
1148 },
1149 {
1150 .offset = 468,
1151 .width = 1,
1152 .value = 0,
1153 },
1154 {}
1155};
1156
1157static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = {
1158 {
1159 .offset = 0,
1160 .width = 2,
1161 .value = 2,
1162 },
1163 {
1164 .offset = 156,
1165 .width = 1,
1166 .value = 0,
1167 },
1168 {}
1169};
1170
1171static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = {
1172 {}
1173};
1174
1175static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {
1176 {}
1177};
1178
1179static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {
1180 [12] = is2_x12_keyfield_set_typegroups,
1181 [6] = is2_x6_keyfield_set_typegroups,
1182 [3] = is2_x3_keyfield_set_typegroups,
1183 [1] = is2_x1_keyfield_set_typegroups,
1184 [13] = NULL,
1185};
1186
1187static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = {
1188 {
1189 .offset = 0,
1190 .width = 2,
1191 .value = 2,
1192 },
1193 {
1194 .offset = 110,
1195 .width = 1,
1196 .value = 0,
1197 },
1198 {
1199 .offset = 220,
1200 .width = 1,
1201 .value = 0,
1202 },
1203 {}
1204};
1205
1206static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {
1207 {}
1208};
1209
1210static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {
1211 [3] = is2_x3_actionfield_set_typegroups,
1212 [1] = is2_x1_actionfield_set_typegroups,
1213 [13] = NULL,
1214};
1215
1216/* Keyfieldset names */
1217static const char * const vcap_keyfield_set_names[] = {
1218 [VCAP_KFS_NO_VALUE] = "(None)",
1219 [VCAP_KFS_ARP] = "VCAP_KFS_ARP",
1220 [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER",
1221 [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP",
1222 [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD",
1223 [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE",
1224 [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE",
1225};
1226
1227/* Actionfieldset names */
1228static const char * const vcap_actionfield_set_names[] = {
1229 [VCAP_AFS_NO_VALUE] = "(None)",
1230 [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE",
1231};
1232
1233/* Keyfield names */
1234static const char * const vcap_keyfield_names[] = {
1235 [VCAP_KF_NO_VALUE] = "(None)",
1236 [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS",
1237 [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS",
1238 [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS",
1239 [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS",
1240 [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS",
1241 [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS",
1242 [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE",
1243 [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS",
1244 [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS",
1245 [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS",
1246 [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS",
1247 [VCAP_KF_ETYPE] = "ETYPE",
1248 [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS",
1249 [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK",
1250 [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3",
1251 [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG",
1252 [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL",
1253 [VCAP_KF_IP4_IS] = "IP4_IS",
1254 [VCAP_KF_ISDX_CLS] = "ISDX_CLS",
1255 [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS",
1256 [VCAP_KF_L2_BC_IS] = "L2_BC_IS",
1257 [VCAP_KF_L2_DMAC] = "L2_DMAC",
1258 [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS",
1259 [VCAP_KF_L2_MC_IS] = "L2_MC_IS",
1260 [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE",
1261 [VCAP_KF_L2_SMAC] = "L2_SMAC",
1262 [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS",
1263 [VCAP_KF_L3_DST_IS] = "L3_DST_IS",
1264 [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE",
1265 [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN",
1266 [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP",
1267 [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP",
1268 [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP",
1269 [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP",
1270 [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO",
1271 [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS",
1272 [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD",
1273 [VCAP_KF_L3_RT_IS] = "L3_RT_IS",
1274 [VCAP_KF_L3_TOS] = "L3_TOS",
1275 [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0",
1276 [VCAP_KF_L4_ACK] = "L4_ACK",
1277 [VCAP_KF_L4_DPORT] = "L4_DPORT",
1278 [VCAP_KF_L4_FIN] = "L4_FIN",
1279 [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD",
1280 [VCAP_KF_L4_PSH] = "L4_PSH",
1281 [VCAP_KF_L4_RNG] = "L4_RNG",
1282 [VCAP_KF_L4_RST] = "L4_RST",
1283 [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS",
1284 [VCAP_KF_L4_SPORT] = "L4_SPORT",
1285 [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS",
1286 [VCAP_KF_L4_SYN] = "L4_SYN",
1287 [VCAP_KF_L4_URG] = "L4_URG",
1288 [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS",
1289 [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG",
1290 [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0",
1291 [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS",
1292 [VCAP_KF_TCP_IS] = "TCP_IS",
1293 [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS",
1294 [VCAP_KF_TYPE] = "TYPE",
1295};
1296
1297/* Actionfield names */
1298static const char * const vcap_actionfield_names[] = {
1299 [VCAP_AF_NO_VALUE] = "(None)",
1300 [VCAP_AF_CNT_ID] = "CNT_ID",
1301 [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA",
1302 [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM",
1303 [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE",
1304 [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL",
1305 [VCAP_AF_INTR_ENA] = "INTR_ENA",
1306 [VCAP_AF_LRN_DIS] = "LRN_DIS",
1307 [VCAP_AF_MASK_MODE] = "MASK_MODE",
1308 [VCAP_AF_MATCH_ID] = "MATCH_ID",
1309 [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK",
1310 [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE",
1311 [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA",
1312 [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT",
1313 [VCAP_AF_POLICE_ENA] = "POLICE_ENA",
1314 [VCAP_AF_POLICE_IDX] = "POLICE_IDX",
1315 [VCAP_AF_PORT_MASK] = "PORT_MASK",
1316 [VCAP_AF_RT_DIS] = "RT_DIS",
1317};
1318
1319/* VCAPs */
1320const struct vcap_info sparx5_vcaps[] = {
1321 [VCAP_TYPE_IS2] = {
1322 .name = "is2",
1323 .rows = 256,
1324 .sw_count = 12,
1325 .sw_width = 52,
1326 .sticky_width = 1,
1327 .act_width = 110,
1328 .default_cnt = 73,
1329 .require_cnt_dis = 0,
1330 .version = 1,
1331 .keyfield_set = is2_keyfield_set,
1332 .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),
1333 .actionfield_set = is2_actionfield_set,
1334 .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),
1335 .keyfield_set_map = is2_keyfield_set_map,
1336 .keyfield_set_map_size = is2_keyfield_set_map_size,
1337 .actionfield_set_map = is2_actionfield_set_map,
1338 .actionfield_set_map_size = is2_actionfield_set_map_size,
1339 .keyfield_set_typegroups = is2_keyfield_set_typegroups,
1340 .actionfield_set_typegroups = is2_actionfield_set_typegroups,
1341 },
1342};
1343
1344const struct vcap_statistics sparx5_vcap_stats = {
1345 .name = "sparx5",
1346 .count = 1,
1347 .keyfield_set_names = vcap_keyfield_set_names,
1348 .actionfield_set_names = vcap_actionfield_set_names,
1349 .keyfield_names = vcap_keyfield_names,
1350 .actionfield_names = vcap_actionfield_names,
1351};