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1// SPDX-License-Identifier: GPL-2.0-only
2/* linux/drivers/mmc/host/sdhci-s3c.c
3 *
4 * Copyright 2008 Openmoko Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * SDHCI (HSMMC) support for Samsung SoC
10 */
11
12#include <linux/spinlock.h>
13#include <linux/delay.h>
14#include <linux/dma-mapping.h>
15#include <linux/platform_device.h>
16#include <linux/platform_data/mmc-sdhci-s3c.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_gpio.h>
25#include <linux/pm.h>
26#include <linux/pm_runtime.h>
27
28#include <linux/mmc/host.h>
29
30#include "sdhci.h"
31
32#define MAX_BUS_CLK (4)
33
34#define S3C_SDHCI_CONTROL2 (0x80)
35#define S3C_SDHCI_CONTROL3 (0x84)
36#define S3C64XX_SDHCI_CONTROL4 (0x8C)
37
38#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
39#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
40#define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
41#define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
42
43#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
44#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
45#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
46
47#define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
48#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16)
49#define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
50
51#define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
52#define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
53#define S3C_SDHCI_CTRL2_SDCDSEL BIT(13)
54#define S3C_SDHCI_CTRL2_SDSIGPC BIT(12)
55#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART BIT(11)
56
57#define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9)
58#define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9)
59#define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9)
60#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9)
61#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9)
62#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9)
63
64#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
65#define S3C_SDHCI_CTRL2_RWAITMODE BIT(7)
66#define S3C_SDHCI_CTRL2_DISBUFRD BIT(6)
67
68#define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4)
69#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4)
70#define S3C_SDHCI_CTRL2_PWRSYNC BIT(3)
71#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON BIT(1)
72#define S3C_SDHCI_CTRL2_HWINITFIN BIT(0)
73
74#define S3C_SDHCI_CTRL3_FCSEL3 BIT(31)
75#define S3C_SDHCI_CTRL3_FCSEL2 BIT(23)
76#define S3C_SDHCI_CTRL3_FCSEL1 BIT(15)
77#define S3C_SDHCI_CTRL3_FCSEL0 BIT(7)
78
79#define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24)
80#define S3C_SDHCI_CTRL3_FIA3_SHIFT (24)
81#define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24)
82
83#define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16)
84#define S3C_SDHCI_CTRL3_FIA2_SHIFT (16)
85#define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16)
86
87#define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
88#define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
89#define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
90
91#define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0)
92#define S3C_SDHCI_CTRL3_FIA0_SHIFT (0)
93#define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0)
94
95#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16)
96#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16)
97#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16)
98#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16)
99#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16)
100#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16)
101
102#define S3C64XX_SDHCI_CONTROL4_BUSY (1)
103
104/**
105 * struct sdhci_s3c - S3C SDHCI instance
106 * @host: The SDHCI host created
107 * @pdev: The platform device we where created from.
108 * @ioarea: The resource created when we claimed the IO area.
109 * @pdata: The platform data for this controller.
110 * @cur_clk: The index of the current bus clock.
111 * @ext_cd_irq: External card detect interrupt.
112 * @clk_io: The clock for the internal bus interface.
113 * @clk_rates: Clock frequencies.
114 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
115 * @no_divider: No or non-standard internal clock divider.
116 */
117struct sdhci_s3c {
118 struct sdhci_host *host;
119 struct platform_device *pdev;
120 struct resource *ioarea;
121 struct s3c_sdhci_platdata *pdata;
122 int cur_clk;
123 int ext_cd_irq;
124
125 struct clk *clk_io;
126 struct clk *clk_bus[MAX_BUS_CLK];
127 unsigned long clk_rates[MAX_BUS_CLK];
128
129 bool no_divider;
130};
131
132/**
133 * struct sdhci_s3c_drv_data - S3C SDHCI platform specific driver data
134 * @sdhci_quirks: sdhci host specific quirks.
135 * @no_divider: no or non-standard internal clock divider.
136 *
137 * Specifies platform specific configuration of sdhci controller.
138 * Note: A structure for driver specific platform data is used for future
139 * expansion of its usage.
140 */
141struct sdhci_s3c_drv_data {
142 unsigned int sdhci_quirks;
143 bool no_divider;
144};
145
146static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
147{
148 return sdhci_priv(host);
149}
150
151/**
152 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
153 * @host: The SDHCI host instance.
154 *
155 * Callback to return the maximum clock rate acheivable by the controller.
156*/
157static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
158{
159 struct sdhci_s3c *ourhost = to_s3c(host);
160 unsigned long rate, max = 0;
161 int src;
162
163 for (src = 0; src < MAX_BUS_CLK; src++) {
164 rate = ourhost->clk_rates[src];
165 if (rate > max)
166 max = rate;
167 }
168
169 return max;
170}
171
172/**
173 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
174 * @ourhost: Our SDHCI instance.
175 * @src: The source clock index.
176 * @wanted: The clock frequency wanted.
177 */
178static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
179 unsigned int src,
180 unsigned int wanted)
181{
182 unsigned long rate;
183 struct clk *clksrc = ourhost->clk_bus[src];
184 int shift;
185
186 if (IS_ERR(clksrc))
187 return UINT_MAX;
188
189 /*
190 * If controller uses a non-standard clock division, find the best clock
191 * speed possible with selected clock source and skip the division.
192 */
193 if (ourhost->no_divider) {
194 rate = clk_round_rate(clksrc, wanted);
195 return wanted - rate;
196 }
197
198 rate = ourhost->clk_rates[src];
199
200 for (shift = 0; shift <= 8; ++shift) {
201 if ((rate >> shift) <= wanted)
202 break;
203 }
204
205 if (shift > 8) {
206 dev_dbg(&ourhost->pdev->dev,
207 "clk %d: rate %ld, min rate %lu > wanted %u\n",
208 src, rate, rate / 256, wanted);
209 return UINT_MAX;
210 }
211
212 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
213 src, rate, wanted, rate >> shift);
214
215 return wanted - (rate >> shift);
216}
217
218/**
219 * sdhci_s3c_set_clock - callback on clock change
220 * @host: The SDHCI host being changed
221 * @clock: The clock rate being requested.
222 *
223 * When the card's clock is going to be changed, look at the new frequency
224 * and find the best clock source to go with it.
225*/
226static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
227{
228 struct sdhci_s3c *ourhost = to_s3c(host);
229 unsigned int best = UINT_MAX;
230 unsigned int delta;
231 int best_src = 0;
232 int src;
233 u32 ctrl;
234
235 host->mmc->actual_clock = 0;
236
237 /* don't bother if the clock is going off. */
238 if (clock == 0) {
239 sdhci_set_clock(host, clock);
240 return;
241 }
242
243 for (src = 0; src < MAX_BUS_CLK; src++) {
244 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
245 if (delta < best) {
246 best = delta;
247 best_src = src;
248 }
249 }
250
251 dev_dbg(&ourhost->pdev->dev,
252 "selected source %d, clock %d, delta %d\n",
253 best_src, clock, best);
254
255 /* select the new clock source */
256 if (ourhost->cur_clk != best_src) {
257 struct clk *clk = ourhost->clk_bus[best_src];
258
259 clk_prepare_enable(clk);
260 if (ourhost->cur_clk >= 0)
261 clk_disable_unprepare(
262 ourhost->clk_bus[ourhost->cur_clk]);
263
264 ourhost->cur_clk = best_src;
265 host->max_clk = ourhost->clk_rates[best_src];
266 }
267
268 /* turn clock off to card before changing clock source */
269 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
270
271 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
272 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
273 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
274 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
275
276 /* reprogram default hardware configuration */
277 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
278 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
279
280 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
281 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
282 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
283 S3C_SDHCI_CTRL2_ENFBCLKRX |
284 S3C_SDHCI_CTRL2_DFCNT_NONE |
285 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
286 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
287
288 /* reconfigure the controller for new clock rate */
289 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
290 if (clock < 25 * 1000000)
291 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
292 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
293
294 sdhci_set_clock(host, clock);
295}
296
297/**
298 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
299 * @host: The SDHCI host being queried
300 *
301 * To init mmc host properly a minimal clock value is needed. For high system
302 * bus clock's values the standard formula gives values out of allowed range.
303 * The clock still can be set to lower values, if clock source other then
304 * system bus is selected.
305*/
306static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
307{
308 struct sdhci_s3c *ourhost = to_s3c(host);
309 unsigned long rate, min = ULONG_MAX;
310 int src;
311
312 for (src = 0; src < MAX_BUS_CLK; src++) {
313 rate = ourhost->clk_rates[src] / 256;
314 if (!rate)
315 continue;
316 if (rate < min)
317 min = rate;
318 }
319
320 return min;
321}
322
323/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
324static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
325{
326 struct sdhci_s3c *ourhost = to_s3c(host);
327 unsigned long rate, max = 0;
328 int src;
329
330 for (src = 0; src < MAX_BUS_CLK; src++) {
331 struct clk *clk;
332
333 clk = ourhost->clk_bus[src];
334 if (IS_ERR(clk))
335 continue;
336
337 rate = clk_round_rate(clk, ULONG_MAX);
338 if (rate > max)
339 max = rate;
340 }
341
342 return max;
343}
344
345/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
346static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
347{
348 struct sdhci_s3c *ourhost = to_s3c(host);
349 unsigned long rate, min = ULONG_MAX;
350 int src;
351
352 for (src = 0; src < MAX_BUS_CLK; src++) {
353 struct clk *clk;
354
355 clk = ourhost->clk_bus[src];
356 if (IS_ERR(clk))
357 continue;
358
359 rate = clk_round_rate(clk, 0);
360 if (rate < min)
361 min = rate;
362 }
363
364 return min;
365}
366
367/* sdhci_cmu_set_clock - callback on clock change.*/
368static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
369{
370 struct sdhci_s3c *ourhost = to_s3c(host);
371 struct device *dev = &ourhost->pdev->dev;
372 unsigned long timeout;
373 u16 clk = 0;
374 int ret;
375
376 host->mmc->actual_clock = 0;
377
378 /* If the clock is going off, set to 0 at clock control register */
379 if (clock == 0) {
380 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
381 return;
382 }
383
384 sdhci_s3c_set_clock(host, clock);
385
386 /* Reset SD Clock Enable */
387 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
388 clk &= ~SDHCI_CLOCK_CARD_EN;
389 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
390
391 ret = clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
392 if (ret != 0) {
393 dev_err(dev, "%s: failed to set clock rate %uHz\n",
394 mmc_hostname(host->mmc), clock);
395 return;
396 }
397
398 clk = SDHCI_CLOCK_INT_EN;
399 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
400
401 /* Wait max 20 ms */
402 timeout = 20;
403 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
404 & SDHCI_CLOCK_INT_STABLE)) {
405 if (timeout == 0) {
406 dev_err(dev, "%s: Internal clock never stabilised.\n",
407 mmc_hostname(host->mmc));
408 return;
409 }
410 timeout--;
411 mdelay(1);
412 }
413
414 clk |= SDHCI_CLOCK_CARD_EN;
415 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
416}
417
418static struct sdhci_ops sdhci_s3c_ops = {
419 .get_max_clock = sdhci_s3c_get_max_clk,
420 .set_clock = sdhci_s3c_set_clock,
421 .get_min_clock = sdhci_s3c_get_min_clock,
422 .set_bus_width = sdhci_set_bus_width,
423 .reset = sdhci_reset,
424 .set_uhs_signaling = sdhci_set_uhs_signaling,
425};
426
427#ifdef CONFIG_OF
428static int sdhci_s3c_parse_dt(struct device *dev,
429 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
430{
431 struct device_node *node = dev->of_node;
432 u32 max_width;
433
434 /* if the bus-width property is not specified, assume width as 1 */
435 if (of_property_read_u32(node, "bus-width", &max_width))
436 max_width = 1;
437 pdata->max_width = max_width;
438
439 /* get the card detection method */
440 if (of_get_property(node, "broken-cd", NULL)) {
441 pdata->cd_type = S3C_SDHCI_CD_NONE;
442 return 0;
443 }
444
445 if (of_get_property(node, "non-removable", NULL)) {
446 pdata->cd_type = S3C_SDHCI_CD_PERMANENT;
447 return 0;
448 }
449
450 if (of_get_named_gpio(node, "cd-gpios", 0))
451 return 0;
452
453 /* assuming internal card detect that will be configured by pinctrl */
454 pdata->cd_type = S3C_SDHCI_CD_INTERNAL;
455 return 0;
456}
457#else
458static int sdhci_s3c_parse_dt(struct device *dev,
459 struct sdhci_host *host, struct s3c_sdhci_platdata *pdata)
460{
461 return -EINVAL;
462}
463#endif
464
465static inline const struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
466 struct platform_device *pdev)
467{
468#ifdef CONFIG_OF
469 if (pdev->dev.of_node)
470 return of_device_get_match_data(&pdev->dev);
471#endif
472 return (const struct sdhci_s3c_drv_data *)
473 platform_get_device_id(pdev)->driver_data;
474}
475
476static int sdhci_s3c_probe(struct platform_device *pdev)
477{
478 struct s3c_sdhci_platdata *pdata;
479 const struct sdhci_s3c_drv_data *drv_data;
480 struct device *dev = &pdev->dev;
481 struct sdhci_host *host;
482 struct sdhci_s3c *sc;
483 int ret, irq, ptr, clks;
484
485 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
486 dev_err(dev, "no device data specified\n");
487 return -ENOENT;
488 }
489
490 irq = platform_get_irq(pdev, 0);
491 if (irq < 0)
492 return irq;
493
494 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
495 if (IS_ERR(host)) {
496 dev_err(dev, "sdhci_alloc_host() failed\n");
497 return PTR_ERR(host);
498 }
499 sc = sdhci_priv(host);
500
501 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
502 if (!pdata) {
503 ret = -ENOMEM;
504 goto err_pdata_io_clk;
505 }
506
507 if (pdev->dev.of_node) {
508 ret = sdhci_s3c_parse_dt(&pdev->dev, host, pdata);
509 if (ret)
510 goto err_pdata_io_clk;
511 } else {
512 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
513 }
514
515 drv_data = sdhci_s3c_get_driver_data(pdev);
516
517 sc->host = host;
518 sc->pdev = pdev;
519 sc->pdata = pdata;
520 sc->cur_clk = -1;
521
522 platform_set_drvdata(pdev, host);
523
524 sc->clk_io = devm_clk_get(dev, "hsmmc");
525 if (IS_ERR(sc->clk_io)) {
526 dev_err(dev, "failed to get io clock\n");
527 ret = PTR_ERR(sc->clk_io);
528 goto err_pdata_io_clk;
529 }
530
531 /* enable the local io clock and keep it running for the moment. */
532 clk_prepare_enable(sc->clk_io);
533
534 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
535 char name[14];
536
537 snprintf(name, 14, "mmc_busclk.%d", ptr);
538 sc->clk_bus[ptr] = devm_clk_get(dev, name);
539 if (IS_ERR(sc->clk_bus[ptr]))
540 continue;
541
542 clks++;
543 sc->clk_rates[ptr] = clk_get_rate(sc->clk_bus[ptr]);
544
545 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
546 ptr, name, sc->clk_rates[ptr]);
547 }
548
549 if (clks == 0) {
550 dev_err(dev, "failed to find any bus clocks\n");
551 ret = -ENOENT;
552 goto err_no_busclks;
553 }
554
555 host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
556 if (IS_ERR(host->ioaddr)) {
557 ret = PTR_ERR(host->ioaddr);
558 goto err_req_regs;
559 }
560
561 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
562 if (pdata->cfg_gpio)
563 pdata->cfg_gpio(pdev, pdata->max_width);
564
565 host->hw_name = "samsung-hsmmc";
566 host->ops = &sdhci_s3c_ops;
567 host->quirks = 0;
568 host->quirks2 = 0;
569 host->irq = irq;
570
571 /* Setup quirks for the controller */
572 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
573 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
574 if (drv_data) {
575 host->quirks |= drv_data->sdhci_quirks;
576 sc->no_divider = drv_data->no_divider;
577 }
578
579#ifndef CONFIG_MMC_SDHCI_S3C_DMA
580
581 /* we currently see overruns on errors, so disable the SDMA
582 * support as well. */
583 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
584
585#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
586
587 /* It seems we do not get an DATA transfer complete on non-busy
588 * transfers, not sure if this is a problem with this specific
589 * SDHCI block, or a missing configuration that needs to be set. */
590 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
591
592 /* This host supports the Auto CMD12 */
593 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
594
595 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
596 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
597
598 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
599 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
600 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
601
602 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
603 host->mmc->caps = MMC_CAP_NONREMOVABLE;
604
605 switch (pdata->max_width) {
606 case 8:
607 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
608 fallthrough;
609 case 4:
610 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
611 break;
612 }
613
614 if (pdata->pm_caps)
615 host->mmc->pm_caps |= pdata->pm_caps;
616
617 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
618 SDHCI_QUIRK_32BIT_DMA_SIZE);
619
620 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
621 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
622
623 /*
624 * If controller does not have internal clock divider,
625 * we can use overriding functions instead of default.
626 */
627 if (sc->no_divider) {
628 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
629 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
630 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
631 }
632
633 /* It supports additional host capabilities if needed */
634 if (pdata->host_caps)
635 host->mmc->caps |= pdata->host_caps;
636
637 if (pdata->host_caps2)
638 host->mmc->caps2 |= pdata->host_caps2;
639
640 pm_runtime_enable(&pdev->dev);
641 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
642 pm_runtime_use_autosuspend(&pdev->dev);
643 pm_suspend_ignore_children(&pdev->dev, 1);
644
645 ret = mmc_of_parse(host->mmc);
646 if (ret)
647 goto err_req_regs;
648
649 ret = sdhci_add_host(host);
650 if (ret)
651 goto err_req_regs;
652
653#ifdef CONFIG_PM
654 if (pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
655 clk_disable_unprepare(sc->clk_io);
656#endif
657 return 0;
658
659 err_req_regs:
660 pm_runtime_disable(&pdev->dev);
661
662 err_no_busclks:
663 clk_disable_unprepare(sc->clk_io);
664
665 err_pdata_io_clk:
666 sdhci_free_host(host);
667
668 return ret;
669}
670
671static int sdhci_s3c_remove(struct platform_device *pdev)
672{
673 struct sdhci_host *host = platform_get_drvdata(pdev);
674 struct sdhci_s3c *sc = sdhci_priv(host);
675
676 if (sc->ext_cd_irq)
677 free_irq(sc->ext_cd_irq, sc);
678
679#ifdef CONFIG_PM
680 if (sc->pdata->cd_type != S3C_SDHCI_CD_INTERNAL)
681 clk_prepare_enable(sc->clk_io);
682#endif
683 sdhci_remove_host(host, 1);
684
685 pm_runtime_dont_use_autosuspend(&pdev->dev);
686 pm_runtime_disable(&pdev->dev);
687
688 clk_disable_unprepare(sc->clk_io);
689
690 sdhci_free_host(host);
691
692 return 0;
693}
694
695#ifdef CONFIG_PM_SLEEP
696static int sdhci_s3c_suspend(struct device *dev)
697{
698 struct sdhci_host *host = dev_get_drvdata(dev);
699
700 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
701 mmc_retune_needed(host->mmc);
702
703 return sdhci_suspend_host(host);
704}
705
706static int sdhci_s3c_resume(struct device *dev)
707{
708 struct sdhci_host *host = dev_get_drvdata(dev);
709
710 return sdhci_resume_host(host);
711}
712#endif
713
714#ifdef CONFIG_PM
715static int sdhci_s3c_runtime_suspend(struct device *dev)
716{
717 struct sdhci_host *host = dev_get_drvdata(dev);
718 struct sdhci_s3c *ourhost = to_s3c(host);
719 struct clk *busclk = ourhost->clk_io;
720 int ret;
721
722 ret = sdhci_runtime_suspend_host(host);
723
724 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
725 mmc_retune_needed(host->mmc);
726
727 if (ourhost->cur_clk >= 0)
728 clk_disable_unprepare(ourhost->clk_bus[ourhost->cur_clk]);
729 clk_disable_unprepare(busclk);
730 return ret;
731}
732
733static int sdhci_s3c_runtime_resume(struct device *dev)
734{
735 struct sdhci_host *host = dev_get_drvdata(dev);
736 struct sdhci_s3c *ourhost = to_s3c(host);
737 struct clk *busclk = ourhost->clk_io;
738 int ret;
739
740 clk_prepare_enable(busclk);
741 if (ourhost->cur_clk >= 0)
742 clk_prepare_enable(ourhost->clk_bus[ourhost->cur_clk]);
743 ret = sdhci_runtime_resume_host(host, 0);
744 return ret;
745}
746#endif
747
748static const struct dev_pm_ops sdhci_s3c_pmops = {
749 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
750 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
751 NULL)
752};
753
754static const struct platform_device_id sdhci_s3c_driver_ids[] = {
755 {
756 .name = "s3c-sdhci",
757 .driver_data = (kernel_ulong_t)NULL,
758 },
759 { }
760};
761MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
762
763#ifdef CONFIG_OF
764static const struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
765 .no_divider = true,
766};
767
768static const struct of_device_id sdhci_s3c_dt_match[] = {
769 { .compatible = "samsung,s3c6410-sdhci", },
770 { .compatible = "samsung,exynos4210-sdhci",
771 .data = &exynos4_sdhci_drv_data },
772 {},
773};
774MODULE_DEVICE_TABLE(of, sdhci_s3c_dt_match);
775#endif
776
777static struct platform_driver sdhci_s3c_driver = {
778 .probe = sdhci_s3c_probe,
779 .remove = sdhci_s3c_remove,
780 .id_table = sdhci_s3c_driver_ids,
781 .driver = {
782 .name = "s3c-sdhci",
783 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
784 .of_match_table = of_match_ptr(sdhci_s3c_dt_match),
785 .pm = &sdhci_s3c_pmops,
786 },
787};
788
789module_platform_driver(sdhci_s3c_driver);
790
791MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
792MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
793MODULE_LICENSE("GPL v2");
1/* linux/drivers/mmc/host/sdhci-s3c.c
2 *
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * SDHCI (HSMMC) support for Samsung SoC
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/delay.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_gpio.h>
25#include <linux/pm.h>
26#include <linux/pm_runtime.h>
27
28#include <linux/mmc/host.h>
29
30#include <plat/sdhci.h>
31#include <plat/regs-sdhci.h>
32
33#include "sdhci.h"
34
35#define MAX_BUS_CLK (4)
36
37/**
38 * struct sdhci_s3c - S3C SDHCI instance
39 * @host: The SDHCI host created
40 * @pdev: The platform device we where created from.
41 * @ioarea: The resource created when we claimed the IO area.
42 * @pdata: The platform data for this controller.
43 * @cur_clk: The index of the current bus clock.
44 * @clk_io: The clock for the internal bus interface.
45 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
46 */
47struct sdhci_s3c {
48 struct sdhci_host *host;
49 struct platform_device *pdev;
50 struct resource *ioarea;
51 struct s3c_sdhci_platdata *pdata;
52 unsigned int cur_clk;
53 int ext_cd_irq;
54 int ext_cd_gpio;
55
56 struct clk *clk_io;
57 struct clk *clk_bus[MAX_BUS_CLK];
58};
59
60/**
61 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
62 * @sdhci_quirks: sdhci host specific quirks.
63 *
64 * Specifies platform specific configuration of sdhci controller.
65 * Note: A structure for driver specific platform data is used for future
66 * expansion of its usage.
67 */
68struct sdhci_s3c_drv_data {
69 unsigned int sdhci_quirks;
70};
71
72static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
73{
74 return sdhci_priv(host);
75}
76
77/**
78 * get_curclk - convert ctrl2 register to clock source number
79 * @ctrl2: Control2 register value.
80 */
81static u32 get_curclk(u32 ctrl2)
82{
83 ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
84 ctrl2 >>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
85
86 return ctrl2;
87}
88
89static void sdhci_s3c_check_sclk(struct sdhci_host *host)
90{
91 struct sdhci_s3c *ourhost = to_s3c(host);
92 u32 tmp = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
93
94 if (get_curclk(tmp) != ourhost->cur_clk) {
95 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
96
97 tmp &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
98 tmp |= ourhost->cur_clk << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
99 writel(tmp, host->ioaddr + S3C_SDHCI_CONTROL2);
100 }
101}
102
103/**
104 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
105 * @host: The SDHCI host instance.
106 *
107 * Callback to return the maximum clock rate acheivable by the controller.
108*/
109static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
110{
111 struct sdhci_s3c *ourhost = to_s3c(host);
112 struct clk *busclk;
113 unsigned int rate, max;
114 int clk;
115
116 /* note, a reset will reset the clock source */
117
118 sdhci_s3c_check_sclk(host);
119
120 for (max = 0, clk = 0; clk < MAX_BUS_CLK; clk++) {
121 busclk = ourhost->clk_bus[clk];
122 if (!busclk)
123 continue;
124
125 rate = clk_get_rate(busclk);
126 if (rate > max)
127 max = rate;
128 }
129
130 return max;
131}
132
133/**
134 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
135 * @ourhost: Our SDHCI instance.
136 * @src: The source clock index.
137 * @wanted: The clock frequency wanted.
138 */
139static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c *ourhost,
140 unsigned int src,
141 unsigned int wanted)
142{
143 unsigned long rate;
144 struct clk *clksrc = ourhost->clk_bus[src];
145 int div;
146
147 if (!clksrc)
148 return UINT_MAX;
149
150 /*
151 * If controller uses a non-standard clock division, find the best clock
152 * speed possible with selected clock source and skip the division.
153 */
154 if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
155 rate = clk_round_rate(clksrc, wanted);
156 return wanted - rate;
157 }
158
159 rate = clk_get_rate(clksrc);
160
161 for (div = 1; div < 256; div *= 2) {
162 if ((rate / div) <= wanted)
163 break;
164 }
165
166 dev_dbg(&ourhost->pdev->dev, "clk %d: rate %ld, want %d, got %ld\n",
167 src, rate, wanted, rate / div);
168
169 return (wanted - (rate / div));
170}
171
172/**
173 * sdhci_s3c_set_clock - callback on clock change
174 * @host: The SDHCI host being changed
175 * @clock: The clock rate being requested.
176 *
177 * When the card's clock is going to be changed, look at the new frequency
178 * and find the best clock source to go with it.
179*/
180static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
181{
182 struct sdhci_s3c *ourhost = to_s3c(host);
183 unsigned int best = UINT_MAX;
184 unsigned int delta;
185 int best_src = 0;
186 int src;
187 u32 ctrl;
188
189 /* don't bother if the clock is going off. */
190 if (clock == 0)
191 return;
192
193 for (src = 0; src < MAX_BUS_CLK; src++) {
194 delta = sdhci_s3c_consider_clock(ourhost, src, clock);
195 if (delta < best) {
196 best = delta;
197 best_src = src;
198 }
199 }
200
201 dev_dbg(&ourhost->pdev->dev,
202 "selected source %d, clock %d, delta %d\n",
203 best_src, clock, best);
204
205 /* select the new clock source */
206
207 if (ourhost->cur_clk != best_src) {
208 struct clk *clk = ourhost->clk_bus[best_src];
209
210 /* turn clock off to card before changing clock source */
211 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
212
213 ourhost->cur_clk = best_src;
214 host->max_clk = clk_get_rate(clk);
215
216 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
217 ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
218 ctrl |= best_src << S3C_SDHCI_CTRL2_SELBASECLK_SHIFT;
219 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
220 }
221
222 /* reprogram default hardware configuration */
223 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA,
224 host->ioaddr + S3C64XX_SDHCI_CONTROL4);
225
226 ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
227 ctrl |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
228 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
229 S3C_SDHCI_CTRL2_ENFBCLKRX |
230 S3C_SDHCI_CTRL2_DFCNT_NONE |
231 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
232 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL2);
233
234 /* reconfigure the controller for new clock rate */
235 ctrl = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
236 if (clock < 25 * 1000000)
237 ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
238 writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
239}
240
241/**
242 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
243 * @host: The SDHCI host being queried
244 *
245 * To init mmc host properly a minimal clock value is needed. For high system
246 * bus clock's values the standard formula gives values out of allowed range.
247 * The clock still can be set to lower values, if clock source other then
248 * system bus is selected.
249*/
250static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
251{
252 struct sdhci_s3c *ourhost = to_s3c(host);
253 unsigned int delta, min = UINT_MAX;
254 int src;
255
256 for (src = 0; src < MAX_BUS_CLK; src++) {
257 delta = sdhci_s3c_consider_clock(ourhost, src, 0);
258 if (delta == UINT_MAX)
259 continue;
260 /* delta is a negative value in this case */
261 if (-delta < min)
262 min = -delta;
263 }
264 return min;
265}
266
267/* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
268static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host *host)
269{
270 struct sdhci_s3c *ourhost = to_s3c(host);
271
272 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], UINT_MAX);
273}
274
275/* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
276static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host *host)
277{
278 struct sdhci_s3c *ourhost = to_s3c(host);
279
280 /*
281 * initial clock can be in the frequency range of
282 * 100KHz-400KHz, so we set it as max value.
283 */
284 return clk_round_rate(ourhost->clk_bus[ourhost->cur_clk], 400000);
285}
286
287/* sdhci_cmu_set_clock - callback on clock change.*/
288static void sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock)
289{
290 struct sdhci_s3c *ourhost = to_s3c(host);
291 unsigned long timeout;
292 u16 clk = 0;
293
294 /* don't bother if the clock is going off */
295 if (clock == 0)
296 return;
297
298 sdhci_s3c_set_clock(host, clock);
299
300 clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
301
302 host->clock = clock;
303
304 clk = SDHCI_CLOCK_INT_EN;
305 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
306
307 /* Wait max 20 ms */
308 timeout = 20;
309 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
310 & SDHCI_CLOCK_INT_STABLE)) {
311 if (timeout == 0) {
312 printk(KERN_ERR "%s: Internal clock never "
313 "stabilised.\n", mmc_hostname(host->mmc));
314 return;
315 }
316 timeout--;
317 mdelay(1);
318 }
319
320 clk |= SDHCI_CLOCK_CARD_EN;
321 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
322}
323
324/**
325 * sdhci_s3c_platform_8bit_width - support 8bit buswidth
326 * @host: The SDHCI host being queried
327 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
328 *
329 * We have 8-bit width support but is not a v3 controller.
330 * So we add platform_8bit_width() and support 8bit width.
331 */
332static int sdhci_s3c_platform_8bit_width(struct sdhci_host *host, int width)
333{
334 u8 ctrl;
335
336 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
337
338 switch (width) {
339 case MMC_BUS_WIDTH_8:
340 ctrl |= SDHCI_CTRL_8BITBUS;
341 ctrl &= ~SDHCI_CTRL_4BITBUS;
342 break;
343 case MMC_BUS_WIDTH_4:
344 ctrl |= SDHCI_CTRL_4BITBUS;
345 ctrl &= ~SDHCI_CTRL_8BITBUS;
346 break;
347 default:
348 ctrl &= ~SDHCI_CTRL_4BITBUS;
349 ctrl &= ~SDHCI_CTRL_8BITBUS;
350 break;
351 }
352
353 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
354
355 return 0;
356}
357
358static struct sdhci_ops sdhci_s3c_ops = {
359 .get_max_clock = sdhci_s3c_get_max_clk,
360 .set_clock = sdhci_s3c_set_clock,
361 .get_min_clock = sdhci_s3c_get_min_clock,
362 .platform_8bit_width = sdhci_s3c_platform_8bit_width,
363};
364
365static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
366{
367 struct sdhci_host *host = platform_get_drvdata(dev);
368 unsigned long flags;
369
370 if (host) {
371 spin_lock_irqsave(&host->lock, flags);
372 if (state) {
373 dev_dbg(&dev->dev, "card inserted.\n");
374 host->flags &= ~SDHCI_DEVICE_DEAD;
375 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
376 } else {
377 dev_dbg(&dev->dev, "card removed.\n");
378 host->flags |= SDHCI_DEVICE_DEAD;
379 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
380 }
381 tasklet_schedule(&host->card_tasklet);
382 spin_unlock_irqrestore(&host->lock, flags);
383 }
384}
385
386static irqreturn_t sdhci_s3c_gpio_card_detect_thread(int irq, void *dev_id)
387{
388 struct sdhci_s3c *sc = dev_id;
389 int status = gpio_get_value(sc->ext_cd_gpio);
390 if (sc->pdata->ext_cd_gpio_invert)
391 status = !status;
392 sdhci_s3c_notify_change(sc->pdev, status);
393 return IRQ_HANDLED;
394}
395
396static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c *sc)
397{
398 struct s3c_sdhci_platdata *pdata = sc->pdata;
399 struct device *dev = &sc->pdev->dev;
400
401 if (gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD") == 0) {
402 sc->ext_cd_gpio = pdata->ext_cd_gpio;
403 sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
404 if (sc->ext_cd_irq &&
405 request_threaded_irq(sc->ext_cd_irq, NULL,
406 sdhci_s3c_gpio_card_detect_thread,
407 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
408 dev_name(dev), sc) == 0) {
409 int status = gpio_get_value(sc->ext_cd_gpio);
410 if (pdata->ext_cd_gpio_invert)
411 status = !status;
412 sdhci_s3c_notify_change(sc->pdev, status);
413 } else {
414 dev_warn(dev, "cannot request irq for card detect\n");
415 sc->ext_cd_irq = 0;
416 }
417 } else {
418 dev_err(dev, "cannot request gpio for card detect\n");
419 }
420}
421
422static inline struct sdhci_s3c_drv_data *sdhci_s3c_get_driver_data(
423 struct platform_device *pdev)
424{
425 return (struct sdhci_s3c_drv_data *)
426 platform_get_device_id(pdev)->driver_data;
427}
428
429static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
430{
431 struct s3c_sdhci_platdata *pdata;
432 struct sdhci_s3c_drv_data *drv_data;
433 struct device *dev = &pdev->dev;
434 struct sdhci_host *host;
435 struct sdhci_s3c *sc;
436 struct resource *res;
437 int ret, irq, ptr, clks;
438
439 if (!pdev->dev.platform_data) {
440 dev_err(dev, "no device data specified\n");
441 return -ENOENT;
442 }
443
444 irq = platform_get_irq(pdev, 0);
445 if (irq < 0) {
446 dev_err(dev, "no irq specified\n");
447 return irq;
448 }
449
450 host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c));
451 if (IS_ERR(host)) {
452 dev_err(dev, "sdhci_alloc_host() failed\n");
453 return PTR_ERR(host);
454 }
455
456 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
457 if (!pdata) {
458 ret = -ENOMEM;
459 goto err_io_clk;
460 }
461 memcpy(pdata, pdev->dev.platform_data, sizeof(*pdata));
462
463 drv_data = sdhci_s3c_get_driver_data(pdev);
464 sc = sdhci_priv(host);
465
466 sc->host = host;
467 sc->pdev = pdev;
468 sc->pdata = pdata;
469 sc->ext_cd_gpio = -1; /* invalid gpio number */
470
471 platform_set_drvdata(pdev, host);
472
473 sc->clk_io = clk_get(dev, "hsmmc");
474 if (IS_ERR(sc->clk_io)) {
475 dev_err(dev, "failed to get io clock\n");
476 ret = PTR_ERR(sc->clk_io);
477 goto err_io_clk;
478 }
479
480 /* enable the local io clock and keep it running for the moment. */
481 clk_enable(sc->clk_io);
482
483 for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
484 struct clk *clk;
485 char name[14];
486
487 snprintf(name, 14, "mmc_busclk.%d", ptr);
488 clk = clk_get(dev, name);
489 if (IS_ERR(clk)) {
490 continue;
491 }
492
493 clks++;
494 sc->clk_bus[ptr] = clk;
495
496 /*
497 * save current clock index to know which clock bus
498 * is used later in overriding functions.
499 */
500 sc->cur_clk = ptr;
501
502 clk_enable(clk);
503
504 dev_info(dev, "clock source %d: %s (%ld Hz)\n",
505 ptr, name, clk_get_rate(clk));
506 }
507
508 if (clks == 0) {
509 dev_err(dev, "failed to find any bus clocks\n");
510 ret = -ENOENT;
511 goto err_no_busclks;
512 }
513
514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
515 host->ioaddr = devm_request_and_ioremap(&pdev->dev, res);
516 if (!host->ioaddr) {
517 dev_err(dev, "failed to map registers\n");
518 ret = -ENXIO;
519 goto err_req_regs;
520 }
521
522 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
523 if (pdata->cfg_gpio)
524 pdata->cfg_gpio(pdev, pdata->max_width);
525
526 host->hw_name = "samsung-hsmmc";
527 host->ops = &sdhci_s3c_ops;
528 host->quirks = 0;
529 host->irq = irq;
530
531 /* Setup quirks for the controller */
532 host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
533 host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
534 if (drv_data)
535 host->quirks |= drv_data->sdhci_quirks;
536
537#ifndef CONFIG_MMC_SDHCI_S3C_DMA
538
539 /* we currently see overruns on errors, so disable the SDMA
540 * support as well. */
541 host->quirks |= SDHCI_QUIRK_BROKEN_DMA;
542
543#endif /* CONFIG_MMC_SDHCI_S3C_DMA */
544
545 /* It seems we do not get an DATA transfer complete on non-busy
546 * transfers, not sure if this is a problem with this specific
547 * SDHCI block, or a missing configuration that needs to be set. */
548 host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
549
550 /* This host supports the Auto CMD12 */
551 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
552
553 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
554 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
555
556 if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
557 pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
558 host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
559
560 if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
561 host->mmc->caps = MMC_CAP_NONREMOVABLE;
562
563 switch (pdata->max_width) {
564 case 8:
565 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
566 case 4:
567 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
568 break;
569 }
570
571 if (pdata->pm_caps)
572 host->mmc->pm_caps |= pdata->pm_caps;
573
574 host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
575 SDHCI_QUIRK_32BIT_DMA_SIZE);
576
577 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
578 host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
579
580 /*
581 * If controller does not have internal clock divider,
582 * we can use overriding functions instead of default.
583 */
584 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
585 sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
586 sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
587 sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
588 }
589
590 /* It supports additional host capabilities if needed */
591 if (pdata->host_caps)
592 host->mmc->caps |= pdata->host_caps;
593
594 if (pdata->host_caps2)
595 host->mmc->caps2 |= pdata->host_caps2;
596
597 pm_runtime_enable(&pdev->dev);
598 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
599 pm_runtime_use_autosuspend(&pdev->dev);
600 pm_suspend_ignore_children(&pdev->dev, 1);
601
602 ret = sdhci_add_host(host);
603 if (ret) {
604 dev_err(dev, "sdhci_add_host() failed\n");
605 pm_runtime_forbid(&pdev->dev);
606 pm_runtime_get_noresume(&pdev->dev);
607 goto err_req_regs;
608 }
609
610 /* The following two methods of card detection might call
611 sdhci_s3c_notify_change() immediately, so they can be called
612 only after sdhci_add_host(). Setup errors are ignored. */
613 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
614 pdata->ext_cd_init(&sdhci_s3c_notify_change);
615 if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
616 gpio_is_valid(pdata->ext_cd_gpio))
617 sdhci_s3c_setup_card_detect_gpio(sc);
618
619 return 0;
620
621 err_req_regs:
622 for (ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
623 if (sc->clk_bus[ptr]) {
624 clk_disable(sc->clk_bus[ptr]);
625 clk_put(sc->clk_bus[ptr]);
626 }
627 }
628
629 err_no_busclks:
630 clk_disable(sc->clk_io);
631 clk_put(sc->clk_io);
632
633 err_io_clk:
634 sdhci_free_host(host);
635
636 return ret;
637}
638
639static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
640{
641 struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
642 struct sdhci_host *host = platform_get_drvdata(pdev);
643 struct sdhci_s3c *sc = sdhci_priv(host);
644 int ptr;
645
646 if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
647 pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
648
649 if (sc->ext_cd_irq)
650 free_irq(sc->ext_cd_irq, sc);
651
652 if (gpio_is_valid(sc->ext_cd_gpio))
653 gpio_free(sc->ext_cd_gpio);
654
655 sdhci_remove_host(host, 1);
656
657 pm_runtime_disable(&pdev->dev);
658
659 for (ptr = 0; ptr < 3; ptr++) {
660 if (sc->clk_bus[ptr]) {
661 clk_disable(sc->clk_bus[ptr]);
662 clk_put(sc->clk_bus[ptr]);
663 }
664 }
665 clk_disable(sc->clk_io);
666 clk_put(sc->clk_io);
667
668 sdhci_free_host(host);
669 platform_set_drvdata(pdev, NULL);
670
671 return 0;
672}
673
674#ifdef CONFIG_PM_SLEEP
675static int sdhci_s3c_suspend(struct device *dev)
676{
677 struct sdhci_host *host = dev_get_drvdata(dev);
678
679 return sdhci_suspend_host(host);
680}
681
682static int sdhci_s3c_resume(struct device *dev)
683{
684 struct sdhci_host *host = dev_get_drvdata(dev);
685
686 return sdhci_resume_host(host);
687}
688#endif
689
690#ifdef CONFIG_PM_RUNTIME
691static int sdhci_s3c_runtime_suspend(struct device *dev)
692{
693 struct sdhci_host *host = dev_get_drvdata(dev);
694
695 return sdhci_runtime_suspend_host(host);
696}
697
698static int sdhci_s3c_runtime_resume(struct device *dev)
699{
700 struct sdhci_host *host = dev_get_drvdata(dev);
701
702 return sdhci_runtime_resume_host(host);
703}
704#endif
705
706#ifdef CONFIG_PM
707static const struct dev_pm_ops sdhci_s3c_pmops = {
708 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend, sdhci_s3c_resume)
709 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend, sdhci_s3c_runtime_resume,
710 NULL)
711};
712
713#define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
714
715#else
716#define SDHCI_S3C_PMOPS NULL
717#endif
718
719#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
720static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
721 .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
722};
723#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
724#else
725#define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
726#endif
727
728static struct platform_device_id sdhci_s3c_driver_ids[] = {
729 {
730 .name = "s3c-sdhci",
731 .driver_data = (kernel_ulong_t)NULL,
732 }, {
733 .name = "exynos4-sdhci",
734 .driver_data = EXYNOS4_SDHCI_DRV_DATA,
735 },
736 { }
737};
738MODULE_DEVICE_TABLE(platform, sdhci_s3c_driver_ids);
739
740static struct platform_driver sdhci_s3c_driver = {
741 .probe = sdhci_s3c_probe,
742 .remove = __devexit_p(sdhci_s3c_remove),
743 .id_table = sdhci_s3c_driver_ids,
744 .driver = {
745 .owner = THIS_MODULE,
746 .name = "s3c-sdhci",
747 .pm = SDHCI_S3C_PMOPS,
748 },
749};
750
751module_platform_driver(sdhci_s3c_driver);
752
753MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
754MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
755MODULE_LICENSE("GPL v2");
756MODULE_ALIAS("platform:s3c-sdhci");