1/*
 2 * Copyright 2019 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "smu7_baco.h"
25#include "tonga_baco.h"
26#include "fiji_baco.h"
27#include "polaris_baco.h"
28#include "ci_baco.h"
29
30#include "bif/bif_5_0_d.h"
31#include "bif/bif_5_0_sh_mask.h"
32
33#include "smu/smu_7_1_2_d.h"
34#include "smu/smu_7_1_2_sh_mask.h"
35
36int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
37{
38	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
39	uint32_t reg;
40
41	*cap = false;
42	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
43		return 0;
44
45	reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
46
47	if (reg & CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK)
48		*cap = true;
49
50	return 0;
51}
52
53int smu7_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
54{
55	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
56	uint32_t reg;
57
58	reg = RREG32(mmBACO_CNTL);
59
60	if (reg & BACO_CNTL__BACO_MODE_MASK)
61		/* gfx has already entered BACO state */
62		*state = BACO_STATE_IN;
63	else
64		*state = BACO_STATE_OUT;
65	return 0;
66}
67
68int smu7_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
69{
70	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
71
72	switch (adev->asic_type) {
73	case CHIP_TOPAZ:
74	case CHIP_TONGA:
75		return tonga_baco_set_state(hwmgr, state);
76	case CHIP_FIJI:
77		return fiji_baco_set_state(hwmgr, state);
78	case CHIP_POLARIS10:
79	case CHIP_POLARIS11:
80	case CHIP_POLARIS12:
81	case CHIP_VEGAM:
82		return polaris_baco_set_state(hwmgr, state);
83#ifdef CONFIG_DRM_AMDGPU_CIK
84	case CHIP_BONAIRE:
85	case CHIP_HAWAII:
86		return ci_baco_set_state(hwmgr, state);
87#endif
88	default:
89		return -EINVAL;
90	}
91}