1/*
  2 *    Copyright IBM Corp 2000,2011
  3 *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
  4 *		 Denis Joseph Barrow,
  5 */
  6
  7#include <linux/linkage.h>
  8#include <asm/asm-offsets.h>
  9
 10#
 11# store_status
 12#
 13# Prerequisites to run this function:
 14# - Prefix register is set to zero
 15# - Original prefix register is stored in "dump_prefix_page"
 16# - Lowcore protection is off
 17#
 18ENTRY(store_status)
 19	/* Save register one and load save area base */
 20	stg	%r1,__LC_SAVE_AREA_RESTART
 21	lghi	%r1,SAVE_AREA_BASE
 22	/* General purpose registers */
 23	stmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 24	lg	%r2,__LC_SAVE_AREA_RESTART
 25	stg	%r2,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE+8(%r1)
 26	/* Control registers */
 27	stctg	%c0,%c15,__LC_CREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 28	/* Access registers */
 29	stam	%a0,%a15,__LC_AREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 30	/* Floating point registers */
 31	std	%f0, 0x00 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 32	std	%f1, 0x08 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 33	std	%f2, 0x10 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 34	std	%f3, 0x18 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 35	std	%f4, 0x20 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 36	std	%f5, 0x28 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 37	std	%f6, 0x30 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 38	std	%f7, 0x38 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 39	std	%f8, 0x40 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 40	std	%f9, 0x48 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 41	std	%f10,0x50 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 42	std	%f11,0x58 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 43	std	%f12,0x60 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 44	std	%f13,0x68 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 45	std	%f14,0x70 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 46	std	%f15,0x78 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
 47	/* Floating point control register */
 48	stfpc	__LC_FP_CREG_SAVE_AREA-SAVE_AREA_BASE(%r1)
 49	/* CPU timer */
 50	stpt	__LC_CPU_TIMER_SAVE_AREA-SAVE_AREA_BASE(%r1)
 51	/* Saved prefix register */
 52	larl	%r2,dump_prefix_page
 53	mvc	__LC_PREFIX_SAVE_AREA-SAVE_AREA_BASE(4,%r1),0(%r2)
 54	/* Clock comparator - seven bytes */
 55	larl	%r2,.Lclkcmp
 56	stckc	0(%r2)
 57	mvc	__LC_CLOCK_COMP_SAVE_AREA-SAVE_AREA_BASE + 1(7,%r1),1(%r2)
 58	/* Program status word */
 59	epsw	%r2,%r3
 60	st	%r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 0(%r1)
 61	st	%r3,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 4(%r1)
 62	larl	%r2,store_status
 63	stg	%r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 8(%r1)
 64	br	%r14
 65
 66	.section .bss
 67	.align	8
 68.Lclkcmp:	.quad	0x0000000000000000
 69	.previous
 70
 71#
 72# do_reipl_asm
 73# Parameter: r2 = schid of reipl device
 74#
 75
 76ENTRY(do_reipl_asm)
 77		basr	%r13,0
 78.Lpg0:		lpswe	.Lnewpsw-.Lpg0(%r13)
 79.Lpg1:		brasl	%r14,store_status
 80
 81		lctlg	%c6,%c6,.Lall-.Lpg0(%r13)
 82		lgr	%r1,%r2
 83		mvc	__LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
 84		stsch	.Lschib-.Lpg0(%r13)
 85		oi	.Lschib+5-.Lpg0(%r13),0x84
 86.Lecs:  	xi	.Lschib+27-.Lpg0(%r13),0x01
 87		msch	.Lschib-.Lpg0(%r13)
 88		lghi	%r0,5
 89.Lssch:		ssch	.Liplorb-.Lpg0(%r13)
 90		jz	.L001
 91		brct	%r0,.Lssch
 92		bas	%r14,.Ldisab-.Lpg0(%r13)
 93.L001:		mvc	__LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
 94.Ltpi:		lpswe	.Lwaitpsw-.Lpg0(%r13)
 95.Lcont:		c	%r1,__LC_SUBCHANNEL_ID
 96		jnz	.Ltpi
 97		clc	__LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
 98		jnz	.Ltpi
 99		tsch	.Liplirb-.Lpg0(%r13)
100		tm	.Liplirb+9-.Lpg0(%r13),0xbf
101		jz	.L002
102		bas	%r14,.Ldisab-.Lpg0(%r13)
103.L002:		tm	.Liplirb+8-.Lpg0(%r13),0xf3
104		jz	.L003
105		bas	%r14,.Ldisab-.Lpg0(%r13)
106.L003:		st	%r1,__LC_SUBCHANNEL_ID
107		lhi	%r1,0		 # mode 0 = esa
108		slr	%r0,%r0 	 # set cpuid to zero
109		sigp	%r1,%r0,0x12	 # switch to esa mode
110		lpsw	0
111.Ldisab:	sll	%r14,1
112		srl	%r14,1		 # need to kill hi bit to avoid specification exceptions.
113		st	%r14,.Ldispsw+12-.Lpg0(%r13)
114		lpswe	.Ldispsw-.Lpg0(%r13)
115		.align	8
116.Lall:		.quad	0x00000000ff000000
117		.align	16
118/*
119 * These addresses have to be 31 bit otherwise
120 * the sigp will throw a specifcation exception
121 * when switching to ESA mode as bit 31 be set
122 * in the ESA psw.
123 * Bit 31 of the addresses has to be 0 for the
124 * 31bit lpswe instruction a fact they appear to have
125 * omitted from the pop.
126 */
127.Lnewpsw:	.quad	0x0000000080000000
128		.quad	.Lpg1
129.Lpcnew:	.quad	0x0000000080000000
130		.quad	.Lecs
131.Lionew:	.quad	0x0000000080000000
132		.quad	.Lcont
133.Lwaitpsw:	.quad	0x0202000080000000
134		.quad	.Ltpi
135.Ldispsw:	.quad	0x0002000080000000
136		.quad	0x0000000000000000
137.Liplccws:	.long	0x02000000,0x60000018
138		.long	0x08000008,0x20000001
139.Liplorb:	.long	0x0049504c,0x0040ff80
140		.long	0x00000000+.Liplccws
141.Lschib:	.long	0x00000000,0x00000000
142		.long	0x00000000,0x00000000
143		.long	0x00000000,0x00000000
144		.long	0x00000000,0x00000000
145		.long	0x00000000,0x00000000
146		.long	0x00000000,0x00000000
147.Liplirb:	.long	0x00000000,0x00000000
148		.long	0x00000000,0x00000000
149		.long	0x00000000,0x00000000
150		.long	0x00000000,0x00000000
151		.long	0x00000000,0x00000000
152		.long	0x00000000,0x00000000
153		.long	0x00000000,0x00000000
154		.long	0x00000000,0x00000000