1/*
  2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
  3 * reserved.
  4 *
  5 * This software is available to you under a choice of one of two
  6 * licenses.  You may choose to be licensed under the terms of the GNU
  7 * General Public License (GPL) Version 2, available from the file
  8 * COPYING in the main directory of this source tree, or the NetLogic
  9 * license below:
 10 *
 11 * Redistribution and use in source and binary forms, with or without
 12 * modification, are permitted provided that the following conditions
 13 * are met:
 14 *
 15 * 1. Redistributions of source code must retain the above copyright
 16 *    notice, this list of conditions and the following disclaimer.
 17 * 2. Redistributions in binary form must reproduce the above copyright
 18 *    notice, this list of conditions and the following disclaimer in
 19 *    the documentation and/or other materials provided with the
 20 *    distribution.
 21 *
 22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 33 */
 34
 35#ifndef __NLM_HAL_SYS_H__
 36#define __NLM_HAL_SYS_H__
 37
 38/**
 39* @file_name sys.h
 40* @author Netlogic Microsystems
 41* @brief HAL for System configuration registers
 42*/
 43#define	SYS_CHIP_RESET				0x00
 44#define	SYS_POWER_ON_RESET_CFG			0x01
 45#define	SYS_EFUSE_DEVICE_CFG_STATUS0		0x02
 46#define	SYS_EFUSE_DEVICE_CFG_STATUS1		0x03
 47#define	SYS_EFUSE_DEVICE_CFG_STATUS2		0x04
 48#define	SYS_EFUSE_DEVICE_CFG3			0x05
 49#define	SYS_EFUSE_DEVICE_CFG4			0x06
 50#define	SYS_EFUSE_DEVICE_CFG5			0x07
 51#define	SYS_EFUSE_DEVICE_CFG6			0x08
 52#define	SYS_EFUSE_DEVICE_CFG7			0x09
 53#define	SYS_PLL_CTRL				0x0a
 54#define	SYS_CPU_RESET				0x0b
 55#define	SYS_CPU_NONCOHERENT_MODE		0x0d
 56#define	SYS_CORE_DFS_DIS_CTRL			0x0e
 57#define	SYS_CORE_DFS_RST_CTRL			0x0f
 58#define	SYS_CORE_DFS_BYP_CTRL			0x10
 59#define	SYS_CORE_DFS_PHA_CTRL			0x11
 60#define	SYS_CORE_DFS_DIV_INC_CTRL		0x12
 61#define	SYS_CORE_DFS_DIV_DEC_CTRL		0x13
 62#define	SYS_CORE_DFS_DIV_VALUE			0x14
 63#define	SYS_RESET				0x15
 64#define	SYS_DFS_DIS_CTRL			0x16
 65#define	SYS_DFS_RST_CTRL			0x17
 66#define	SYS_DFS_BYP_CTRL			0x18
 67#define	SYS_DFS_DIV_INC_CTRL			0x19
 68#define	SYS_DFS_DIV_DEC_CTRL			0x1a
 69#define	SYS_DFS_DIV_VALUE0			0x1b
 70#define	SYS_DFS_DIV_VALUE1			0x1c
 71#define	SYS_SENSE_AMP_DLY			0x1d
 72#define	SYS_SOC_SENSE_AMP_DLY			0x1e
 73#define	SYS_CTRL0				0x1f
 74#define	SYS_CTRL1				0x20
 75#define	SYS_TIMEOUT_BS1				0x21
 76#define	SYS_BYTE_SWAP				0x22
 77#define	SYS_VRM_VID				0x23
 78#define	SYS_PWR_RAM_CMD				0x24
 79#define	SYS_PWR_RAM_ADDR			0x25
 80#define	SYS_PWR_RAM_DATA0			0x26
 81#define	SYS_PWR_RAM_DATA1			0x27
 82#define	SYS_PWR_RAM_DATA2			0x28
 83#define	SYS_PWR_UCODE				0x29
 84#define	SYS_CPU0_PWR_STATUS			0x2a
 85#define	SYS_CPU1_PWR_STATUS			0x2b
 86#define	SYS_CPU2_PWR_STATUS			0x2c
 87#define	SYS_CPU3_PWR_STATUS			0x2d
 88#define	SYS_CPU4_PWR_STATUS			0x2e
 89#define	SYS_CPU5_PWR_STATUS			0x2f
 90#define	SYS_CPU6_PWR_STATUS			0x30
 91#define	SYS_CPU7_PWR_STATUS			0x31
 92#define	SYS_STATUS				0x32
 93#define	SYS_INT_POL				0x33
 94#define	SYS_INT_TYPE				0x34
 95#define	SYS_INT_STATUS				0x35
 96#define	SYS_INT_MASK0				0x36
 97#define	SYS_INT_MASK1				0x37
 98#define	SYS_UCO_S_ECC				0x38
 99#define	SYS_UCO_M_ECC				0x39
100#define	SYS_UCO_ADDR				0x3a
101#define	SYS_UCO_INSTR				0x3b
102#define	SYS_MEM_BIST0				0x3c
103#define	SYS_MEM_BIST1				0x3d
104#define	SYS_MEM_BIST2				0x3e
105#define	SYS_MEM_BIST3				0x3f
106#define	SYS_MEM_BIST4				0x40
107#define	SYS_MEM_BIST5				0x41
108#define	SYS_MEM_BIST6				0x42
109#define	SYS_MEM_BIST7				0x43
110#define	SYS_MEM_BIST8				0x44
111#define	SYS_MEM_BIST9				0x45
112#define	SYS_MEM_BIST10				0x46
113#define	SYS_MEM_BIST11				0x47
114#define	SYS_MEM_BIST12				0x48
115#define	SYS_SCRTCH0				0x49
116#define	SYS_SCRTCH1				0x4a
117#define	SYS_SCRTCH2				0x4b
118#define	SYS_SCRTCH3				0x4c
119
120#ifndef __ASSEMBLY__
121
122#define	nlm_read_sys_reg(b, r)		nlm_read_reg(b, r)
123#define	nlm_write_sys_reg(b, r, v)	nlm_write_reg(b, r, v)
124#define	nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
125#define	nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
126
127extern uint64_t nlm_sys_base;
128#endif
129#endif