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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mm/dma-mapping.c
4 *
5 * Copyright (C) 2000-2004 Russell King
6 *
7 * DMA uncached mapping support.
8 */
9#include <linux/module.h>
10#include <linux/mm.h>
11#include <linux/genalloc.h>
12#include <linux/gfp.h>
13#include <linux/errno.h>
14#include <linux/list.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/dma-direct.h>
18#include <linux/dma-map-ops.h>
19#include <linux/highmem.h>
20#include <linux/memblock.h>
21#include <linux/slab.h>
22#include <linux/iommu.h>
23#include <linux/io.h>
24#include <linux/vmalloc.h>
25#include <linux/sizes.h>
26#include <linux/cma.h>
27
28#include <asm/memory.h>
29#include <asm/highmem.h>
30#include <asm/cacheflush.h>
31#include <asm/tlbflush.h>
32#include <asm/mach/arch.h>
33#include <asm/dma-iommu.h>
34#include <asm/mach/map.h>
35#include <asm/system_info.h>
36#include <asm/xen/xen-ops.h>
37
38#include "dma.h"
39#include "mm.h"
40
41struct arm_dma_alloc_args {
42 struct device *dev;
43 size_t size;
44 gfp_t gfp;
45 pgprot_t prot;
46 const void *caller;
47 bool want_vaddr;
48 int coherent_flag;
49};
50
51struct arm_dma_free_args {
52 struct device *dev;
53 size_t size;
54 void *cpu_addr;
55 struct page *page;
56 bool want_vaddr;
57};
58
59#define NORMAL 0
60#define COHERENT 1
61
62struct arm_dma_allocator {
63 void *(*alloc)(struct arm_dma_alloc_args *args,
64 struct page **ret_page);
65 void (*free)(struct arm_dma_free_args *args);
66};
67
68struct arm_dma_buffer {
69 struct list_head list;
70 void *virt;
71 struct arm_dma_allocator *allocator;
72};
73
74static LIST_HEAD(arm_dma_bufs);
75static DEFINE_SPINLOCK(arm_dma_bufs_lock);
76
77static struct arm_dma_buffer *arm_dma_buffer_find(void *virt)
78{
79 struct arm_dma_buffer *buf, *found = NULL;
80 unsigned long flags;
81
82 spin_lock_irqsave(&arm_dma_bufs_lock, flags);
83 list_for_each_entry(buf, &arm_dma_bufs, list) {
84 if (buf->virt == virt) {
85 list_del(&buf->list);
86 found = buf;
87 break;
88 }
89 }
90 spin_unlock_irqrestore(&arm_dma_bufs_lock, flags);
91 return found;
92}
93
94/*
95 * The DMA API is built upon the notion of "buffer ownership". A buffer
96 * is either exclusively owned by the CPU (and therefore may be accessed
97 * by it) or exclusively owned by the DMA device. These helper functions
98 * represent the transitions between these two ownership states.
99 *
100 * Note, however, that on later ARMs, this notion does not work due to
101 * speculative prefetches. We model our approach on the assumption that
102 * the CPU does do speculative prefetches, which means we clean caches
103 * before transfers and delay cache invalidation until transfer completion.
104 *
105 */
106
107static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag)
108{
109 /*
110 * Ensure that the allocated pages are zeroed, and that any data
111 * lurking in the kernel direct-mapped region is invalidated.
112 */
113 if (PageHighMem(page)) {
114 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
115 phys_addr_t end = base + size;
116 while (size > 0) {
117 void *ptr = kmap_atomic(page);
118 memset(ptr, 0, PAGE_SIZE);
119 if (coherent_flag != COHERENT)
120 dmac_flush_range(ptr, ptr + PAGE_SIZE);
121 kunmap_atomic(ptr);
122 page++;
123 size -= PAGE_SIZE;
124 }
125 if (coherent_flag != COHERENT)
126 outer_flush_range(base, end);
127 } else {
128 void *ptr = page_address(page);
129 memset(ptr, 0, size);
130 if (coherent_flag != COHERENT) {
131 dmac_flush_range(ptr, ptr + size);
132 outer_flush_range(__pa(ptr), __pa(ptr) + size);
133 }
134 }
135}
136
137/*
138 * Allocate a DMA buffer for 'dev' of size 'size' using the
139 * specified gfp mask. Note that 'size' must be page aligned.
140 */
141static struct page *__dma_alloc_buffer(struct device *dev, size_t size,
142 gfp_t gfp, int coherent_flag)
143{
144 unsigned long order = get_order(size);
145 struct page *page, *p, *e;
146
147 page = alloc_pages(gfp, order);
148 if (!page)
149 return NULL;
150
151 /*
152 * Now split the huge page and free the excess pages
153 */
154 split_page(page, order);
155 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
156 __free_page(p);
157
158 __dma_clear_buffer(page, size, coherent_flag);
159
160 return page;
161}
162
163/*
164 * Free a DMA buffer. 'size' must be page aligned.
165 */
166static void __dma_free_buffer(struct page *page, size_t size)
167{
168 struct page *e = page + (size >> PAGE_SHIFT);
169
170 while (page < e) {
171 __free_page(page);
172 page++;
173 }
174}
175
176static void *__alloc_from_contiguous(struct device *dev, size_t size,
177 pgprot_t prot, struct page **ret_page,
178 const void *caller, bool want_vaddr,
179 int coherent_flag, gfp_t gfp);
180
181static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
182 pgprot_t prot, struct page **ret_page,
183 const void *caller, bool want_vaddr);
184
185#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
186static struct gen_pool *atomic_pool __ro_after_init;
187
188static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE;
189
190static int __init early_coherent_pool(char *p)
191{
192 atomic_pool_size = memparse(p, &p);
193 return 0;
194}
195early_param("coherent_pool", early_coherent_pool);
196
197/*
198 * Initialise the coherent pool for atomic allocations.
199 */
200static int __init atomic_pool_init(void)
201{
202 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
203 gfp_t gfp = GFP_KERNEL | GFP_DMA;
204 struct page *page;
205 void *ptr;
206
207 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
208 if (!atomic_pool)
209 goto out;
210 /*
211 * The atomic pool is only used for non-coherent allocations
212 * so we must pass NORMAL for coherent_flag.
213 */
214 if (dev_get_cma_area(NULL))
215 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
216 &page, atomic_pool_init, true, NORMAL,
217 GFP_KERNEL);
218 else
219 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
220 &page, atomic_pool_init, true);
221 if (ptr) {
222 int ret;
223
224 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
225 page_to_phys(page),
226 atomic_pool_size, -1);
227 if (ret)
228 goto destroy_genpool;
229
230 gen_pool_set_algo(atomic_pool,
231 gen_pool_first_fit_order_align,
232 NULL);
233 pr_info("DMA: preallocated %zu KiB pool for atomic coherent allocations\n",
234 atomic_pool_size / 1024);
235 return 0;
236 }
237
238destroy_genpool:
239 gen_pool_destroy(atomic_pool);
240 atomic_pool = NULL;
241out:
242 pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n",
243 atomic_pool_size / 1024);
244 return -ENOMEM;
245}
246/*
247 * CMA is activated by core_initcall, so we must be called after it.
248 */
249postcore_initcall(atomic_pool_init);
250
251#ifdef CONFIG_CMA_AREAS
252struct dma_contig_early_reserve {
253 phys_addr_t base;
254 unsigned long size;
255};
256
257static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
258
259static int dma_mmu_remap_num __initdata;
260
261void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
262{
263 dma_mmu_remap[dma_mmu_remap_num].base = base;
264 dma_mmu_remap[dma_mmu_remap_num].size = size;
265 dma_mmu_remap_num++;
266}
267
268void __init dma_contiguous_remap(void)
269{
270 int i;
271 for (i = 0; i < dma_mmu_remap_num; i++) {
272 phys_addr_t start = dma_mmu_remap[i].base;
273 phys_addr_t end = start + dma_mmu_remap[i].size;
274 struct map_desc map;
275 unsigned long addr;
276
277 if (end > arm_lowmem_limit)
278 end = arm_lowmem_limit;
279 if (start >= end)
280 continue;
281
282 map.pfn = __phys_to_pfn(start);
283 map.virtual = __phys_to_virt(start);
284 map.length = end - start;
285 map.type = MT_MEMORY_DMA_READY;
286
287 /*
288 * Clear previous low-memory mapping to ensure that the
289 * TLB does not see any conflicting entries, then flush
290 * the TLB of the old entries before creating new mappings.
291 *
292 * This ensures that any speculatively loaded TLB entries
293 * (even though they may be rare) can not cause any problems,
294 * and ensures that this code is architecturally compliant.
295 */
296 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
297 addr += PMD_SIZE)
298 pmd_clear(pmd_off_k(addr));
299
300 flush_tlb_kernel_range(__phys_to_virt(start),
301 __phys_to_virt(end));
302
303 iotable_init(&map, 1);
304 }
305}
306#endif
307
308static int __dma_update_pte(pte_t *pte, unsigned long addr, void *data)
309{
310 struct page *page = virt_to_page((void *)addr);
311 pgprot_t prot = *(pgprot_t *)data;
312
313 set_pte_ext(pte, mk_pte(page, prot), 0);
314 return 0;
315}
316
317static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
318{
319 unsigned long start = (unsigned long) page_address(page);
320 unsigned end = start + size;
321
322 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
323 flush_tlb_kernel_range(start, end);
324}
325
326static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
327 pgprot_t prot, struct page **ret_page,
328 const void *caller, bool want_vaddr)
329{
330 struct page *page;
331 void *ptr = NULL;
332 /*
333 * __alloc_remap_buffer is only called when the device is
334 * non-coherent
335 */
336 page = __dma_alloc_buffer(dev, size, gfp, NORMAL);
337 if (!page)
338 return NULL;
339 if (!want_vaddr)
340 goto out;
341
342 ptr = dma_common_contiguous_remap(page, size, prot, caller);
343 if (!ptr) {
344 __dma_free_buffer(page, size);
345 return NULL;
346 }
347
348 out:
349 *ret_page = page;
350 return ptr;
351}
352
353static void *__alloc_from_pool(size_t size, struct page **ret_page)
354{
355 unsigned long val;
356 void *ptr = NULL;
357
358 if (!atomic_pool) {
359 WARN(1, "coherent pool not initialised!\n");
360 return NULL;
361 }
362
363 val = gen_pool_alloc(atomic_pool, size);
364 if (val) {
365 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
366
367 *ret_page = phys_to_page(phys);
368 ptr = (void *)val;
369 }
370
371 return ptr;
372}
373
374static bool __in_atomic_pool(void *start, size_t size)
375{
376 return gen_pool_has_addr(atomic_pool, (unsigned long)start, size);
377}
378
379static int __free_from_pool(void *start, size_t size)
380{
381 if (!__in_atomic_pool(start, size))
382 return 0;
383
384 gen_pool_free(atomic_pool, (unsigned long)start, size);
385
386 return 1;
387}
388
389static void *__alloc_from_contiguous(struct device *dev, size_t size,
390 pgprot_t prot, struct page **ret_page,
391 const void *caller, bool want_vaddr,
392 int coherent_flag, gfp_t gfp)
393{
394 unsigned long order = get_order(size);
395 size_t count = size >> PAGE_SHIFT;
396 struct page *page;
397 void *ptr = NULL;
398
399 page = dma_alloc_from_contiguous(dev, count, order, gfp & __GFP_NOWARN);
400 if (!page)
401 return NULL;
402
403 __dma_clear_buffer(page, size, coherent_flag);
404
405 if (!want_vaddr)
406 goto out;
407
408 if (PageHighMem(page)) {
409 ptr = dma_common_contiguous_remap(page, size, prot, caller);
410 if (!ptr) {
411 dma_release_from_contiguous(dev, page, count);
412 return NULL;
413 }
414 } else {
415 __dma_remap(page, size, prot);
416 ptr = page_address(page);
417 }
418
419 out:
420 *ret_page = page;
421 return ptr;
422}
423
424static void __free_from_contiguous(struct device *dev, struct page *page,
425 void *cpu_addr, size_t size, bool want_vaddr)
426{
427 if (want_vaddr) {
428 if (PageHighMem(page))
429 dma_common_free_remap(cpu_addr, size);
430 else
431 __dma_remap(page, size, PAGE_KERNEL);
432 }
433 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
434}
435
436static inline pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot)
437{
438 prot = (attrs & DMA_ATTR_WRITE_COMBINE) ?
439 pgprot_writecombine(prot) :
440 pgprot_dmacoherent(prot);
441 return prot;
442}
443
444static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
445 struct page **ret_page)
446{
447 struct page *page;
448 /* __alloc_simple_buffer is only called when the device is coherent */
449 page = __dma_alloc_buffer(dev, size, gfp, COHERENT);
450 if (!page)
451 return NULL;
452
453 *ret_page = page;
454 return page_address(page);
455}
456
457static void *simple_allocator_alloc(struct arm_dma_alloc_args *args,
458 struct page **ret_page)
459{
460 return __alloc_simple_buffer(args->dev, args->size, args->gfp,
461 ret_page);
462}
463
464static void simple_allocator_free(struct arm_dma_free_args *args)
465{
466 __dma_free_buffer(args->page, args->size);
467}
468
469static struct arm_dma_allocator simple_allocator = {
470 .alloc = simple_allocator_alloc,
471 .free = simple_allocator_free,
472};
473
474static void *cma_allocator_alloc(struct arm_dma_alloc_args *args,
475 struct page **ret_page)
476{
477 return __alloc_from_contiguous(args->dev, args->size, args->prot,
478 ret_page, args->caller,
479 args->want_vaddr, args->coherent_flag,
480 args->gfp);
481}
482
483static void cma_allocator_free(struct arm_dma_free_args *args)
484{
485 __free_from_contiguous(args->dev, args->page, args->cpu_addr,
486 args->size, args->want_vaddr);
487}
488
489static struct arm_dma_allocator cma_allocator = {
490 .alloc = cma_allocator_alloc,
491 .free = cma_allocator_free,
492};
493
494static void *pool_allocator_alloc(struct arm_dma_alloc_args *args,
495 struct page **ret_page)
496{
497 return __alloc_from_pool(args->size, ret_page);
498}
499
500static void pool_allocator_free(struct arm_dma_free_args *args)
501{
502 __free_from_pool(args->cpu_addr, args->size);
503}
504
505static struct arm_dma_allocator pool_allocator = {
506 .alloc = pool_allocator_alloc,
507 .free = pool_allocator_free,
508};
509
510static void *remap_allocator_alloc(struct arm_dma_alloc_args *args,
511 struct page **ret_page)
512{
513 return __alloc_remap_buffer(args->dev, args->size, args->gfp,
514 args->prot, ret_page, args->caller,
515 args->want_vaddr);
516}
517
518static void remap_allocator_free(struct arm_dma_free_args *args)
519{
520 if (args->want_vaddr)
521 dma_common_free_remap(args->cpu_addr, args->size);
522
523 __dma_free_buffer(args->page, args->size);
524}
525
526static struct arm_dma_allocator remap_allocator = {
527 .alloc = remap_allocator_alloc,
528 .free = remap_allocator_free,
529};
530
531static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
532 gfp_t gfp, pgprot_t prot, bool is_coherent,
533 unsigned long attrs, const void *caller)
534{
535 u64 mask = min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
536 struct page *page = NULL;
537 void *addr;
538 bool allowblock, cma;
539 struct arm_dma_buffer *buf;
540 struct arm_dma_alloc_args args = {
541 .dev = dev,
542 .size = PAGE_ALIGN(size),
543 .gfp = gfp,
544 .prot = prot,
545 .caller = caller,
546 .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0),
547 .coherent_flag = is_coherent ? COHERENT : NORMAL,
548 };
549
550#ifdef CONFIG_DMA_API_DEBUG
551 u64 limit = (mask + 1) & ~mask;
552 if (limit && size >= limit) {
553 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
554 size, mask);
555 return NULL;
556 }
557#endif
558
559 buf = kzalloc(sizeof(*buf),
560 gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM));
561 if (!buf)
562 return NULL;
563
564 if (mask < 0xffffffffULL)
565 gfp |= GFP_DMA;
566
567 args.gfp = gfp;
568
569 *handle = DMA_MAPPING_ERROR;
570 allowblock = gfpflags_allow_blocking(gfp);
571 cma = allowblock ? dev_get_cma_area(dev) : NULL;
572
573 if (cma)
574 buf->allocator = &cma_allocator;
575 else if (is_coherent)
576 buf->allocator = &simple_allocator;
577 else if (allowblock)
578 buf->allocator = &remap_allocator;
579 else
580 buf->allocator = &pool_allocator;
581
582 addr = buf->allocator->alloc(&args, &page);
583
584 if (page) {
585 unsigned long flags;
586
587 *handle = phys_to_dma(dev, page_to_phys(page));
588 buf->virt = args.want_vaddr ? addr : page;
589
590 spin_lock_irqsave(&arm_dma_bufs_lock, flags);
591 list_add(&buf->list, &arm_dma_bufs);
592 spin_unlock_irqrestore(&arm_dma_bufs_lock, flags);
593 } else {
594 kfree(buf);
595 }
596
597 return args.want_vaddr ? addr : page;
598}
599
600/*
601 * Free a buffer as defined by the above mapping.
602 */
603static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
604 dma_addr_t handle, unsigned long attrs,
605 bool is_coherent)
606{
607 struct page *page = phys_to_page(dma_to_phys(dev, handle));
608 struct arm_dma_buffer *buf;
609 struct arm_dma_free_args args = {
610 .dev = dev,
611 .size = PAGE_ALIGN(size),
612 .cpu_addr = cpu_addr,
613 .page = page,
614 .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0),
615 };
616
617 buf = arm_dma_buffer_find(cpu_addr);
618 if (WARN(!buf, "Freeing invalid buffer %p\n", cpu_addr))
619 return;
620
621 buf->allocator->free(&args);
622 kfree(buf);
623}
624
625static void dma_cache_maint_page(struct page *page, unsigned long offset,
626 size_t size, enum dma_data_direction dir,
627 void (*op)(const void *, size_t, int))
628{
629 unsigned long pfn;
630 size_t left = size;
631
632 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
633 offset %= PAGE_SIZE;
634
635 /*
636 * A single sg entry may refer to multiple physically contiguous
637 * pages. But we still need to process highmem pages individually.
638 * If highmem is not configured then the bulk of this loop gets
639 * optimized out.
640 */
641 do {
642 size_t len = left;
643 void *vaddr;
644
645 page = pfn_to_page(pfn);
646
647 if (PageHighMem(page)) {
648 if (len + offset > PAGE_SIZE)
649 len = PAGE_SIZE - offset;
650
651 if (cache_is_vipt_nonaliasing()) {
652 vaddr = kmap_atomic(page);
653 op(vaddr + offset, len, dir);
654 kunmap_atomic(vaddr);
655 } else {
656 vaddr = kmap_high_get(page);
657 if (vaddr) {
658 op(vaddr + offset, len, dir);
659 kunmap_high(page);
660 }
661 }
662 } else {
663 vaddr = page_address(page) + offset;
664 op(vaddr, len, dir);
665 }
666 offset = 0;
667 pfn++;
668 left -= len;
669 } while (left);
670}
671
672/*
673 * Make an area consistent for devices.
674 * Note: Drivers should NOT use this function directly.
675 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
676 */
677static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
678 size_t size, enum dma_data_direction dir)
679{
680 phys_addr_t paddr;
681
682 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
683
684 paddr = page_to_phys(page) + off;
685 if (dir == DMA_FROM_DEVICE) {
686 outer_inv_range(paddr, paddr + size);
687 } else {
688 outer_clean_range(paddr, paddr + size);
689 }
690 /* FIXME: non-speculating: flush on bidirectional mappings? */
691}
692
693static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
694 size_t size, enum dma_data_direction dir)
695{
696 phys_addr_t paddr = page_to_phys(page) + off;
697
698 /* FIXME: non-speculating: not required */
699 /* in any case, don't bother invalidating if DMA to device */
700 if (dir != DMA_TO_DEVICE) {
701 outer_inv_range(paddr, paddr + size);
702
703 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
704 }
705
706 /*
707 * Mark the D-cache clean for these pages to avoid extra flushing.
708 */
709 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
710 unsigned long pfn;
711 size_t left = size;
712
713 pfn = page_to_pfn(page) + off / PAGE_SIZE;
714 off %= PAGE_SIZE;
715 if (off) {
716 pfn++;
717 left -= PAGE_SIZE - off;
718 }
719 while (left >= PAGE_SIZE) {
720 page = pfn_to_page(pfn++);
721 set_bit(PG_dcache_clean, &page->flags);
722 left -= PAGE_SIZE;
723 }
724 }
725}
726
727#ifdef CONFIG_ARM_DMA_USE_IOMMU
728
729static int __dma_info_to_prot(enum dma_data_direction dir, unsigned long attrs)
730{
731 int prot = 0;
732
733 if (attrs & DMA_ATTR_PRIVILEGED)
734 prot |= IOMMU_PRIV;
735
736 switch (dir) {
737 case DMA_BIDIRECTIONAL:
738 return prot | IOMMU_READ | IOMMU_WRITE;
739 case DMA_TO_DEVICE:
740 return prot | IOMMU_READ;
741 case DMA_FROM_DEVICE:
742 return prot | IOMMU_WRITE;
743 default:
744 return prot;
745 }
746}
747
748/* IOMMU */
749
750static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
751
752static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
753 size_t size)
754{
755 unsigned int order = get_order(size);
756 unsigned int align = 0;
757 unsigned int count, start;
758 size_t mapping_size = mapping->bits << PAGE_SHIFT;
759 unsigned long flags;
760 dma_addr_t iova;
761 int i;
762
763 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
764 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
765
766 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
767 align = (1 << order) - 1;
768
769 spin_lock_irqsave(&mapping->lock, flags);
770 for (i = 0; i < mapping->nr_bitmaps; i++) {
771 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
772 mapping->bits, 0, count, align);
773
774 if (start > mapping->bits)
775 continue;
776
777 bitmap_set(mapping->bitmaps[i], start, count);
778 break;
779 }
780
781 /*
782 * No unused range found. Try to extend the existing mapping
783 * and perform a second attempt to reserve an IO virtual
784 * address range of size bytes.
785 */
786 if (i == mapping->nr_bitmaps) {
787 if (extend_iommu_mapping(mapping)) {
788 spin_unlock_irqrestore(&mapping->lock, flags);
789 return DMA_MAPPING_ERROR;
790 }
791
792 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
793 mapping->bits, 0, count, align);
794
795 if (start > mapping->bits) {
796 spin_unlock_irqrestore(&mapping->lock, flags);
797 return DMA_MAPPING_ERROR;
798 }
799
800 bitmap_set(mapping->bitmaps[i], start, count);
801 }
802 spin_unlock_irqrestore(&mapping->lock, flags);
803
804 iova = mapping->base + (mapping_size * i);
805 iova += start << PAGE_SHIFT;
806
807 return iova;
808}
809
810static inline void __free_iova(struct dma_iommu_mapping *mapping,
811 dma_addr_t addr, size_t size)
812{
813 unsigned int start, count;
814 size_t mapping_size = mapping->bits << PAGE_SHIFT;
815 unsigned long flags;
816 dma_addr_t bitmap_base;
817 u32 bitmap_index;
818
819 if (!size)
820 return;
821
822 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
823 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
824
825 bitmap_base = mapping->base + mapping_size * bitmap_index;
826
827 start = (addr - bitmap_base) >> PAGE_SHIFT;
828
829 if (addr + size > bitmap_base + mapping_size) {
830 /*
831 * The address range to be freed reaches into the iova
832 * range of the next bitmap. This should not happen as
833 * we don't allow this in __alloc_iova (at the
834 * moment).
835 */
836 BUG();
837 } else
838 count = size >> PAGE_SHIFT;
839
840 spin_lock_irqsave(&mapping->lock, flags);
841 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
842 spin_unlock_irqrestore(&mapping->lock, flags);
843}
844
845/* We'll try 2M, 1M, 64K, and finally 4K; array must end with 0! */
846static const int iommu_order_array[] = { 9, 8, 4, 0 };
847
848static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
849 gfp_t gfp, unsigned long attrs,
850 int coherent_flag)
851{
852 struct page **pages;
853 int count = size >> PAGE_SHIFT;
854 int array_size = count * sizeof(struct page *);
855 int i = 0;
856 int order_idx = 0;
857
858 if (array_size <= PAGE_SIZE)
859 pages = kzalloc(array_size, GFP_KERNEL);
860 else
861 pages = vzalloc(array_size);
862 if (!pages)
863 return NULL;
864
865 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS)
866 {
867 unsigned long order = get_order(size);
868 struct page *page;
869
870 page = dma_alloc_from_contiguous(dev, count, order,
871 gfp & __GFP_NOWARN);
872 if (!page)
873 goto error;
874
875 __dma_clear_buffer(page, size, coherent_flag);
876
877 for (i = 0; i < count; i++)
878 pages[i] = page + i;
879
880 return pages;
881 }
882
883 /* Go straight to 4K chunks if caller says it's OK. */
884 if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
885 order_idx = ARRAY_SIZE(iommu_order_array) - 1;
886
887 /*
888 * IOMMU can map any pages, so himem can also be used here
889 */
890 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
891
892 while (count) {
893 int j, order;
894
895 order = iommu_order_array[order_idx];
896
897 /* Drop down when we get small */
898 if (__fls(count) < order) {
899 order_idx++;
900 continue;
901 }
902
903 if (order) {
904 /* See if it's easy to allocate a high-order chunk */
905 pages[i] = alloc_pages(gfp | __GFP_NORETRY, order);
906
907 /* Go down a notch at first sign of pressure */
908 if (!pages[i]) {
909 order_idx++;
910 continue;
911 }
912 } else {
913 pages[i] = alloc_pages(gfp, 0);
914 if (!pages[i])
915 goto error;
916 }
917
918 if (order) {
919 split_page(pages[i], order);
920 j = 1 << order;
921 while (--j)
922 pages[i + j] = pages[i] + j;
923 }
924
925 __dma_clear_buffer(pages[i], PAGE_SIZE << order, coherent_flag);
926 i += 1 << order;
927 count -= 1 << order;
928 }
929
930 return pages;
931error:
932 while (i--)
933 if (pages[i])
934 __free_pages(pages[i], 0);
935 kvfree(pages);
936 return NULL;
937}
938
939static int __iommu_free_buffer(struct device *dev, struct page **pages,
940 size_t size, unsigned long attrs)
941{
942 int count = size >> PAGE_SHIFT;
943 int i;
944
945 if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
946 dma_release_from_contiguous(dev, pages[0], count);
947 } else {
948 for (i = 0; i < count; i++)
949 if (pages[i])
950 __free_pages(pages[i], 0);
951 }
952
953 kvfree(pages);
954 return 0;
955}
956
957/*
958 * Create a mapping in device IO address space for specified pages
959 */
960static dma_addr_t
961__iommu_create_mapping(struct device *dev, struct page **pages, size_t size,
962 unsigned long attrs)
963{
964 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
965 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
966 dma_addr_t dma_addr, iova;
967 int i;
968
969 dma_addr = __alloc_iova(mapping, size);
970 if (dma_addr == DMA_MAPPING_ERROR)
971 return dma_addr;
972
973 iova = dma_addr;
974 for (i = 0; i < count; ) {
975 int ret;
976
977 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
978 phys_addr_t phys = page_to_phys(pages[i]);
979 unsigned int len, j;
980
981 for (j = i + 1; j < count; j++, next_pfn++)
982 if (page_to_pfn(pages[j]) != next_pfn)
983 break;
984
985 len = (j - i) << PAGE_SHIFT;
986 ret = iommu_map(mapping->domain, iova, phys, len,
987 __dma_info_to_prot(DMA_BIDIRECTIONAL, attrs));
988 if (ret < 0)
989 goto fail;
990 iova += len;
991 i = j;
992 }
993 return dma_addr;
994fail:
995 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
996 __free_iova(mapping, dma_addr, size);
997 return DMA_MAPPING_ERROR;
998}
999
1000static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1001{
1002 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1003
1004 /*
1005 * add optional in-page offset from iova to size and align
1006 * result to page size
1007 */
1008 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1009 iova &= PAGE_MASK;
1010
1011 iommu_unmap(mapping->domain, iova, size);
1012 __free_iova(mapping, iova, size);
1013 return 0;
1014}
1015
1016static struct page **__atomic_get_pages(void *addr)
1017{
1018 struct page *page;
1019 phys_addr_t phys;
1020
1021 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1022 page = phys_to_page(phys);
1023
1024 return (struct page **)page;
1025}
1026
1027static struct page **__iommu_get_pages(void *cpu_addr, unsigned long attrs)
1028{
1029 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1030 return __atomic_get_pages(cpu_addr);
1031
1032 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING)
1033 return cpu_addr;
1034
1035 return dma_common_find_pages(cpu_addr);
1036}
1037
1038static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp,
1039 dma_addr_t *handle, int coherent_flag,
1040 unsigned long attrs)
1041{
1042 struct page *page;
1043 void *addr;
1044
1045 if (coherent_flag == COHERENT)
1046 addr = __alloc_simple_buffer(dev, size, gfp, &page);
1047 else
1048 addr = __alloc_from_pool(size, &page);
1049 if (!addr)
1050 return NULL;
1051
1052 *handle = __iommu_create_mapping(dev, &page, size, attrs);
1053 if (*handle == DMA_MAPPING_ERROR)
1054 goto err_mapping;
1055
1056 return addr;
1057
1058err_mapping:
1059 __free_from_pool(addr, size);
1060 return NULL;
1061}
1062
1063static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1064 dma_addr_t handle, size_t size, int coherent_flag)
1065{
1066 __iommu_remove_mapping(dev, handle, size);
1067 if (coherent_flag == COHERENT)
1068 __dma_free_buffer(virt_to_page(cpu_addr), size);
1069 else
1070 __free_from_pool(cpu_addr, size);
1071}
1072
1073static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1074 dma_addr_t *handle, gfp_t gfp, unsigned long attrs)
1075{
1076 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1077 struct page **pages;
1078 void *addr = NULL;
1079 int coherent_flag = dev->dma_coherent ? COHERENT : NORMAL;
1080
1081 *handle = DMA_MAPPING_ERROR;
1082 size = PAGE_ALIGN(size);
1083
1084 if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp))
1085 return __iommu_alloc_simple(dev, size, gfp, handle,
1086 coherent_flag, attrs);
1087
1088 pages = __iommu_alloc_buffer(dev, size, gfp, attrs, coherent_flag);
1089 if (!pages)
1090 return NULL;
1091
1092 *handle = __iommu_create_mapping(dev, pages, size, attrs);
1093 if (*handle == DMA_MAPPING_ERROR)
1094 goto err_buffer;
1095
1096 if (attrs & DMA_ATTR_NO_KERNEL_MAPPING)
1097 return pages;
1098
1099 addr = dma_common_pages_remap(pages, size, prot,
1100 __builtin_return_address(0));
1101 if (!addr)
1102 goto err_mapping;
1103
1104 return addr;
1105
1106err_mapping:
1107 __iommu_remove_mapping(dev, *handle, size);
1108err_buffer:
1109 __iommu_free_buffer(dev, pages, size, attrs);
1110 return NULL;
1111}
1112
1113static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1114 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1115 unsigned long attrs)
1116{
1117 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1118 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1119 int err;
1120
1121 if (!pages)
1122 return -ENXIO;
1123
1124 if (vma->vm_pgoff >= nr_pages)
1125 return -ENXIO;
1126
1127 if (!dev->dma_coherent)
1128 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1129
1130 err = vm_map_pages(vma, pages, nr_pages);
1131 if (err)
1132 pr_err("Remapping memory failed: %d\n", err);
1133
1134 return err;
1135}
1136
1137/*
1138 * free a page as defined by the above mapping.
1139 * Must not be called with IRQs disabled.
1140 */
1141static void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1142 dma_addr_t handle, unsigned long attrs)
1143{
1144 int coherent_flag = dev->dma_coherent ? COHERENT : NORMAL;
1145 struct page **pages;
1146 size = PAGE_ALIGN(size);
1147
1148 if (coherent_flag == COHERENT || __in_atomic_pool(cpu_addr, size)) {
1149 __iommu_free_atomic(dev, cpu_addr, handle, size, coherent_flag);
1150 return;
1151 }
1152
1153 pages = __iommu_get_pages(cpu_addr, attrs);
1154 if (!pages) {
1155 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1156 return;
1157 }
1158
1159 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0)
1160 dma_common_free_remap(cpu_addr, size);
1161
1162 __iommu_remove_mapping(dev, handle, size);
1163 __iommu_free_buffer(dev, pages, size, attrs);
1164}
1165
1166static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1167 void *cpu_addr, dma_addr_t dma_addr,
1168 size_t size, unsigned long attrs)
1169{
1170 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1171 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1172
1173 if (!pages)
1174 return -ENXIO;
1175
1176 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1177 GFP_KERNEL);
1178}
1179
1180/*
1181 * Map a part of the scatter-gather list into contiguous io address space
1182 */
1183static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1184 size_t size, dma_addr_t *handle,
1185 enum dma_data_direction dir, unsigned long attrs)
1186{
1187 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1188 dma_addr_t iova, iova_base;
1189 int ret = 0;
1190 unsigned int count;
1191 struct scatterlist *s;
1192 int prot;
1193
1194 size = PAGE_ALIGN(size);
1195 *handle = DMA_MAPPING_ERROR;
1196
1197 iova_base = iova = __alloc_iova(mapping, size);
1198 if (iova == DMA_MAPPING_ERROR)
1199 return -ENOMEM;
1200
1201 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1202 phys_addr_t phys = page_to_phys(sg_page(s));
1203 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1204
1205 if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1206 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1207
1208 prot = __dma_info_to_prot(dir, attrs);
1209
1210 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1211 if (ret < 0)
1212 goto fail;
1213 count += len >> PAGE_SHIFT;
1214 iova += len;
1215 }
1216 *handle = iova_base;
1217
1218 return 0;
1219fail:
1220 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1221 __free_iova(mapping, iova_base, size);
1222 return ret;
1223}
1224
1225/**
1226 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1227 * @dev: valid struct device pointer
1228 * @sg: list of buffers
1229 * @nents: number of buffers to map
1230 * @dir: DMA transfer direction
1231 *
1232 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1233 * The scatter gather list elements are merged together (if possible) and
1234 * tagged with the appropriate dma address and length. They are obtained via
1235 * sg_dma_{address,length}.
1236 */
1237static int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1238 int nents, enum dma_data_direction dir, unsigned long attrs)
1239{
1240 struct scatterlist *s = sg, *dma = sg, *start = sg;
1241 int i, count = 0, ret;
1242 unsigned int offset = s->offset;
1243 unsigned int size = s->offset + s->length;
1244 unsigned int max = dma_get_max_seg_size(dev);
1245
1246 for (i = 1; i < nents; i++) {
1247 s = sg_next(s);
1248
1249 s->dma_length = 0;
1250
1251 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1252 ret = __map_sg_chunk(dev, start, size,
1253 &dma->dma_address, dir, attrs);
1254 if (ret < 0)
1255 goto bad_mapping;
1256
1257 dma->dma_address += offset;
1258 dma->dma_length = size - offset;
1259
1260 size = offset = s->offset;
1261 start = s;
1262 dma = sg_next(dma);
1263 count += 1;
1264 }
1265 size += s->length;
1266 }
1267 ret = __map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs);
1268 if (ret < 0)
1269 goto bad_mapping;
1270
1271 dma->dma_address += offset;
1272 dma->dma_length = size - offset;
1273
1274 return count+1;
1275
1276bad_mapping:
1277 for_each_sg(sg, s, count, i)
1278 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1279 if (ret == -ENOMEM)
1280 return ret;
1281 return -EINVAL;
1282}
1283
1284/**
1285 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1286 * @dev: valid struct device pointer
1287 * @sg: list of buffers
1288 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1289 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1290 *
1291 * Unmap a set of streaming mode DMA translations. Again, CPU access
1292 * rules concerning calls here are the same as for dma_unmap_single().
1293 */
1294static void arm_iommu_unmap_sg(struct device *dev,
1295 struct scatterlist *sg, int nents,
1296 enum dma_data_direction dir,
1297 unsigned long attrs)
1298{
1299 struct scatterlist *s;
1300 int i;
1301
1302 for_each_sg(sg, s, nents, i) {
1303 if (sg_dma_len(s))
1304 __iommu_remove_mapping(dev, sg_dma_address(s),
1305 sg_dma_len(s));
1306 if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1307 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1308 s->length, dir);
1309 }
1310}
1311
1312/**
1313 * arm_iommu_sync_sg_for_cpu
1314 * @dev: valid struct device pointer
1315 * @sg: list of buffers
1316 * @nents: number of buffers to map (returned from dma_map_sg)
1317 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1318 */
1319static void arm_iommu_sync_sg_for_cpu(struct device *dev,
1320 struct scatterlist *sg,
1321 int nents, enum dma_data_direction dir)
1322{
1323 struct scatterlist *s;
1324 int i;
1325
1326 if (dev->dma_coherent)
1327 return;
1328
1329 for_each_sg(sg, s, nents, i)
1330 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1331
1332}
1333
1334/**
1335 * arm_iommu_sync_sg_for_device
1336 * @dev: valid struct device pointer
1337 * @sg: list of buffers
1338 * @nents: number of buffers to map (returned from dma_map_sg)
1339 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1340 */
1341static void arm_iommu_sync_sg_for_device(struct device *dev,
1342 struct scatterlist *sg,
1343 int nents, enum dma_data_direction dir)
1344{
1345 struct scatterlist *s;
1346 int i;
1347
1348 if (dev->dma_coherent)
1349 return;
1350
1351 for_each_sg(sg, s, nents, i)
1352 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1353}
1354
1355/**
1356 * arm_iommu_map_page
1357 * @dev: valid struct device pointer
1358 * @page: page that buffer resides in
1359 * @offset: offset into page for start of buffer
1360 * @size: size of buffer to map
1361 * @dir: DMA transfer direction
1362 *
1363 * IOMMU aware version of arm_dma_map_page()
1364 */
1365static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1366 unsigned long offset, size_t size, enum dma_data_direction dir,
1367 unsigned long attrs)
1368{
1369 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1370 dma_addr_t dma_addr;
1371 int ret, prot, len = PAGE_ALIGN(size + offset);
1372
1373 if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC))
1374 __dma_page_cpu_to_dev(page, offset, size, dir);
1375
1376 dma_addr = __alloc_iova(mapping, len);
1377 if (dma_addr == DMA_MAPPING_ERROR)
1378 return dma_addr;
1379
1380 prot = __dma_info_to_prot(dir, attrs);
1381
1382 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1383 if (ret < 0)
1384 goto fail;
1385
1386 return dma_addr + offset;
1387fail:
1388 __free_iova(mapping, dma_addr, len);
1389 return DMA_MAPPING_ERROR;
1390}
1391
1392/**
1393 * arm_iommu_unmap_page
1394 * @dev: valid struct device pointer
1395 * @handle: DMA address of buffer
1396 * @size: size of buffer (same as passed to dma_map_page)
1397 * @dir: DMA transfer direction (same as passed to dma_map_page)
1398 *
1399 * IOMMU aware version of arm_dma_unmap_page()
1400 */
1401static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1402 size_t size, enum dma_data_direction dir, unsigned long attrs)
1403{
1404 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1405 dma_addr_t iova = handle & PAGE_MASK;
1406 struct page *page;
1407 int offset = handle & ~PAGE_MASK;
1408 int len = PAGE_ALIGN(size + offset);
1409
1410 if (!iova)
1411 return;
1412
1413 if (!dev->dma_coherent && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) {
1414 page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1415 __dma_page_dev_to_cpu(page, offset, size, dir);
1416 }
1417
1418 iommu_unmap(mapping->domain, iova, len);
1419 __free_iova(mapping, iova, len);
1420}
1421
1422/**
1423 * arm_iommu_map_resource - map a device resource for DMA
1424 * @dev: valid struct device pointer
1425 * @phys_addr: physical address of resource
1426 * @size: size of resource to map
1427 * @dir: DMA transfer direction
1428 */
1429static dma_addr_t arm_iommu_map_resource(struct device *dev,
1430 phys_addr_t phys_addr, size_t size,
1431 enum dma_data_direction dir, unsigned long attrs)
1432{
1433 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1434 dma_addr_t dma_addr;
1435 int ret, prot;
1436 phys_addr_t addr = phys_addr & PAGE_MASK;
1437 unsigned int offset = phys_addr & ~PAGE_MASK;
1438 size_t len = PAGE_ALIGN(size + offset);
1439
1440 dma_addr = __alloc_iova(mapping, len);
1441 if (dma_addr == DMA_MAPPING_ERROR)
1442 return dma_addr;
1443
1444 prot = __dma_info_to_prot(dir, attrs) | IOMMU_MMIO;
1445
1446 ret = iommu_map(mapping->domain, dma_addr, addr, len, prot);
1447 if (ret < 0)
1448 goto fail;
1449
1450 return dma_addr + offset;
1451fail:
1452 __free_iova(mapping, dma_addr, len);
1453 return DMA_MAPPING_ERROR;
1454}
1455
1456/**
1457 * arm_iommu_unmap_resource - unmap a device DMA resource
1458 * @dev: valid struct device pointer
1459 * @dma_handle: DMA address to resource
1460 * @size: size of resource to map
1461 * @dir: DMA transfer direction
1462 */
1463static void arm_iommu_unmap_resource(struct device *dev, dma_addr_t dma_handle,
1464 size_t size, enum dma_data_direction dir,
1465 unsigned long attrs)
1466{
1467 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1468 dma_addr_t iova = dma_handle & PAGE_MASK;
1469 unsigned int offset = dma_handle & ~PAGE_MASK;
1470 size_t len = PAGE_ALIGN(size + offset);
1471
1472 if (!iova)
1473 return;
1474
1475 iommu_unmap(mapping->domain, iova, len);
1476 __free_iova(mapping, iova, len);
1477}
1478
1479static void arm_iommu_sync_single_for_cpu(struct device *dev,
1480 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1481{
1482 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1483 dma_addr_t iova = handle & PAGE_MASK;
1484 struct page *page;
1485 unsigned int offset = handle & ~PAGE_MASK;
1486
1487 if (dev->dma_coherent || !iova)
1488 return;
1489
1490 page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1491 __dma_page_dev_to_cpu(page, offset, size, dir);
1492}
1493
1494static void arm_iommu_sync_single_for_device(struct device *dev,
1495 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1496{
1497 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1498 dma_addr_t iova = handle & PAGE_MASK;
1499 struct page *page;
1500 unsigned int offset = handle & ~PAGE_MASK;
1501
1502 if (dev->dma_coherent || !iova)
1503 return;
1504
1505 page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1506 __dma_page_cpu_to_dev(page, offset, size, dir);
1507}
1508
1509static const struct dma_map_ops iommu_ops = {
1510 .alloc = arm_iommu_alloc_attrs,
1511 .free = arm_iommu_free_attrs,
1512 .mmap = arm_iommu_mmap_attrs,
1513 .get_sgtable = arm_iommu_get_sgtable,
1514
1515 .map_page = arm_iommu_map_page,
1516 .unmap_page = arm_iommu_unmap_page,
1517 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1518 .sync_single_for_device = arm_iommu_sync_single_for_device,
1519
1520 .map_sg = arm_iommu_map_sg,
1521 .unmap_sg = arm_iommu_unmap_sg,
1522 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1523 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1524
1525 .map_resource = arm_iommu_map_resource,
1526 .unmap_resource = arm_iommu_unmap_resource,
1527};
1528
1529/**
1530 * arm_iommu_create_mapping
1531 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1532 * @base: start address of the valid IO address space
1533 * @size: maximum size of the valid IO address space
1534 *
1535 * Creates a mapping structure which holds information about used/unused
1536 * IO address ranges, which is required to perform memory allocation and
1537 * mapping with IOMMU aware functions.
1538 *
1539 * The client device need to be attached to the mapping with
1540 * arm_iommu_attach_device function.
1541 */
1542struct dma_iommu_mapping *
1543arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
1544{
1545 unsigned int bits = size >> PAGE_SHIFT;
1546 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
1547 struct dma_iommu_mapping *mapping;
1548 int extensions = 1;
1549 int err = -ENOMEM;
1550
1551 /* currently only 32-bit DMA address space is supported */
1552 if (size > DMA_BIT_MASK(32) + 1)
1553 return ERR_PTR(-ERANGE);
1554
1555 if (!bitmap_size)
1556 return ERR_PTR(-EINVAL);
1557
1558 if (bitmap_size > PAGE_SIZE) {
1559 extensions = bitmap_size / PAGE_SIZE;
1560 bitmap_size = PAGE_SIZE;
1561 }
1562
1563 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1564 if (!mapping)
1565 goto err;
1566
1567 mapping->bitmap_size = bitmap_size;
1568 mapping->bitmaps = kcalloc(extensions, sizeof(unsigned long *),
1569 GFP_KERNEL);
1570 if (!mapping->bitmaps)
1571 goto err2;
1572
1573 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
1574 if (!mapping->bitmaps[0])
1575 goto err3;
1576
1577 mapping->nr_bitmaps = 1;
1578 mapping->extensions = extensions;
1579 mapping->base = base;
1580 mapping->bits = BITS_PER_BYTE * bitmap_size;
1581
1582 spin_lock_init(&mapping->lock);
1583
1584 mapping->domain = iommu_domain_alloc(bus);
1585 if (!mapping->domain)
1586 goto err4;
1587
1588 kref_init(&mapping->kref);
1589 return mapping;
1590err4:
1591 kfree(mapping->bitmaps[0]);
1592err3:
1593 kfree(mapping->bitmaps);
1594err2:
1595 kfree(mapping);
1596err:
1597 return ERR_PTR(err);
1598}
1599EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1600
1601static void release_iommu_mapping(struct kref *kref)
1602{
1603 int i;
1604 struct dma_iommu_mapping *mapping =
1605 container_of(kref, struct dma_iommu_mapping, kref);
1606
1607 iommu_domain_free(mapping->domain);
1608 for (i = 0; i < mapping->nr_bitmaps; i++)
1609 kfree(mapping->bitmaps[i]);
1610 kfree(mapping->bitmaps);
1611 kfree(mapping);
1612}
1613
1614static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
1615{
1616 int next_bitmap;
1617
1618 if (mapping->nr_bitmaps >= mapping->extensions)
1619 return -EINVAL;
1620
1621 next_bitmap = mapping->nr_bitmaps;
1622 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
1623 GFP_ATOMIC);
1624 if (!mapping->bitmaps[next_bitmap])
1625 return -ENOMEM;
1626
1627 mapping->nr_bitmaps++;
1628
1629 return 0;
1630}
1631
1632void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1633{
1634 if (mapping)
1635 kref_put(&mapping->kref, release_iommu_mapping);
1636}
1637EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1638
1639static int __arm_iommu_attach_device(struct device *dev,
1640 struct dma_iommu_mapping *mapping)
1641{
1642 int err;
1643
1644 err = iommu_attach_device(mapping->domain, dev);
1645 if (err)
1646 return err;
1647
1648 kref_get(&mapping->kref);
1649 to_dma_iommu_mapping(dev) = mapping;
1650
1651 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
1652 return 0;
1653}
1654
1655/**
1656 * arm_iommu_attach_device
1657 * @dev: valid struct device pointer
1658 * @mapping: io address space mapping structure (returned from
1659 * arm_iommu_create_mapping)
1660 *
1661 * Attaches specified io address space mapping to the provided device.
1662 * This replaces the dma operations (dma_map_ops pointer) with the
1663 * IOMMU aware version.
1664 *
1665 * More than one client might be attached to the same io address space
1666 * mapping.
1667 */
1668int arm_iommu_attach_device(struct device *dev,
1669 struct dma_iommu_mapping *mapping)
1670{
1671 int err;
1672
1673 err = __arm_iommu_attach_device(dev, mapping);
1674 if (err)
1675 return err;
1676
1677 set_dma_ops(dev, &iommu_ops);
1678 return 0;
1679}
1680EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
1681
1682/**
1683 * arm_iommu_detach_device
1684 * @dev: valid struct device pointer
1685 *
1686 * Detaches the provided device from a previously attached map.
1687 * This overwrites the dma_ops pointer with appropriate non-IOMMU ops.
1688 */
1689void arm_iommu_detach_device(struct device *dev)
1690{
1691 struct dma_iommu_mapping *mapping;
1692
1693 mapping = to_dma_iommu_mapping(dev);
1694 if (!mapping) {
1695 dev_warn(dev, "Not attached\n");
1696 return;
1697 }
1698
1699 iommu_detach_device(mapping->domain, dev);
1700 kref_put(&mapping->kref, release_iommu_mapping);
1701 to_dma_iommu_mapping(dev) = NULL;
1702 set_dma_ops(dev, NULL);
1703
1704 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
1705}
1706EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
1707
1708static void arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
1709 const struct iommu_ops *iommu, bool coherent)
1710{
1711 struct dma_iommu_mapping *mapping;
1712
1713 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
1714 if (IS_ERR(mapping)) {
1715 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
1716 size, dev_name(dev));
1717 return;
1718 }
1719
1720 if (__arm_iommu_attach_device(dev, mapping)) {
1721 pr_warn("Failed to attached device %s to IOMMU_mapping\n",
1722 dev_name(dev));
1723 arm_iommu_release_mapping(mapping);
1724 return;
1725 }
1726
1727 set_dma_ops(dev, &iommu_ops);
1728}
1729
1730static void arm_teardown_iommu_dma_ops(struct device *dev)
1731{
1732 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1733
1734 if (!mapping)
1735 return;
1736
1737 arm_iommu_detach_device(dev);
1738 arm_iommu_release_mapping(mapping);
1739}
1740
1741#else
1742
1743static void arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
1744 const struct iommu_ops *iommu, bool coherent)
1745{
1746}
1747
1748static void arm_teardown_iommu_dma_ops(struct device *dev) { }
1749
1750#endif /* CONFIG_ARM_DMA_USE_IOMMU */
1751
1752void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
1753 const struct iommu_ops *iommu, bool coherent)
1754{
1755 /*
1756 * Due to legacy code that sets the ->dma_coherent flag from a bus
1757 * notifier we can't just assign coherent to the ->dma_coherent flag
1758 * here, but instead have to make sure we only set but never clear it
1759 * for now.
1760 */
1761 if (coherent)
1762 dev->dma_coherent = true;
1763
1764 /*
1765 * Don't override the dma_ops if they have already been set. Ideally
1766 * this should be the only location where dma_ops are set, remove this
1767 * check when all other callers of set_dma_ops will have disappeared.
1768 */
1769 if (dev->dma_ops)
1770 return;
1771
1772 if (iommu)
1773 arm_setup_iommu_dma_ops(dev, dma_base, size, iommu, coherent);
1774
1775 xen_setup_dma_ops(dev);
1776 dev->archdata.dma_ops_setup = true;
1777}
1778
1779void arch_teardown_dma_ops(struct device *dev)
1780{
1781 if (!dev->archdata.dma_ops_setup)
1782 return;
1783
1784 arm_teardown_iommu_dma_ops(dev);
1785 /* Let arch_setup_dma_ops() start again from scratch upon re-probe */
1786 set_dma_ops(dev, NULL);
1787}
1788
1789void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
1790 enum dma_data_direction dir)
1791{
1792 __dma_page_cpu_to_dev(phys_to_page(paddr), paddr & (PAGE_SIZE - 1),
1793 size, dir);
1794}
1795
1796void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
1797 enum dma_data_direction dir)
1798{
1799 __dma_page_dev_to_cpu(phys_to_page(paddr), paddr & (PAGE_SIZE - 1),
1800 size, dir);
1801}
1802
1803void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
1804 gfp_t gfp, unsigned long attrs)
1805{
1806 return __dma_alloc(dev, size, dma_handle, gfp,
1807 __get_dma_pgprot(attrs, PAGE_KERNEL), false,
1808 attrs, __builtin_return_address(0));
1809}
1810
1811void arch_dma_free(struct device *dev, size_t size, void *cpu_addr,
1812 dma_addr_t dma_handle, unsigned long attrs)
1813{
1814 __arm_dma_free(dev, size, cpu_addr, dma_handle, attrs, false);
1815}
1/*
2 * linux/arch/arm/mm/dma-mapping.c
3 *
4 * Copyright (C) 2000-2004 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * DMA uncached mapping support.
11 */
12#include <linux/module.h>
13#include <linux/mm.h>
14#include <linux/gfp.h>
15#include <linux/errno.h>
16#include <linux/list.h>
17#include <linux/init.h>
18#include <linux/device.h>
19#include <linux/dma-mapping.h>
20#include <linux/dma-contiguous.h>
21#include <linux/highmem.h>
22#include <linux/memblock.h>
23#include <linux/slab.h>
24#include <linux/iommu.h>
25#include <linux/vmalloc.h>
26
27#include <asm/memory.h>
28#include <asm/highmem.h>
29#include <asm/cacheflush.h>
30#include <asm/tlbflush.h>
31#include <asm/sizes.h>
32#include <asm/mach/arch.h>
33#include <asm/dma-iommu.h>
34#include <asm/mach/map.h>
35#include <asm/system_info.h>
36#include <asm/dma-contiguous.h>
37
38#include "mm.h"
39
40/*
41 * The DMA API is built upon the notion of "buffer ownership". A buffer
42 * is either exclusively owned by the CPU (and therefore may be accessed
43 * by it) or exclusively owned by the DMA device. These helper functions
44 * represent the transitions between these two ownership states.
45 *
46 * Note, however, that on later ARMs, this notion does not work due to
47 * speculative prefetches. We model our approach on the assumption that
48 * the CPU does do speculative prefetches, which means we clean caches
49 * before transfers and delay cache invalidation until transfer completion.
50 *
51 */
52static void __dma_page_cpu_to_dev(struct page *, unsigned long,
53 size_t, enum dma_data_direction);
54static void __dma_page_dev_to_cpu(struct page *, unsigned long,
55 size_t, enum dma_data_direction);
56
57/**
58 * arm_dma_map_page - map a portion of a page for streaming DMA
59 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
60 * @page: page that buffer resides in
61 * @offset: offset into page for start of buffer
62 * @size: size of buffer to map
63 * @dir: DMA transfer direction
64 *
65 * Ensure that any data held in the cache is appropriately discarded
66 * or written back.
67 *
68 * The device owns this memory once this call has completed. The CPU
69 * can regain ownership by calling dma_unmap_page().
70 */
71static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
72 unsigned long offset, size_t size, enum dma_data_direction dir,
73 struct dma_attrs *attrs)
74{
75 if (!arch_is_coherent())
76 __dma_page_cpu_to_dev(page, offset, size, dir);
77 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
78}
79
80/**
81 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
82 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
83 * @handle: DMA address of buffer
84 * @size: size of buffer (same as passed to dma_map_page)
85 * @dir: DMA transfer direction (same as passed to dma_map_page)
86 *
87 * Unmap a page streaming mode DMA translation. The handle and size
88 * must match what was provided in the previous dma_map_page() call.
89 * All other usages are undefined.
90 *
91 * After this call, reads by the CPU to the buffer are guaranteed to see
92 * whatever the device wrote there.
93 */
94static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
95 size_t size, enum dma_data_direction dir,
96 struct dma_attrs *attrs)
97{
98 if (!arch_is_coherent())
99 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
100 handle & ~PAGE_MASK, size, dir);
101}
102
103static void arm_dma_sync_single_for_cpu(struct device *dev,
104 dma_addr_t handle, size_t size, enum dma_data_direction dir)
105{
106 unsigned int offset = handle & (PAGE_SIZE - 1);
107 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
108 if (!arch_is_coherent())
109 __dma_page_dev_to_cpu(page, offset, size, dir);
110}
111
112static void arm_dma_sync_single_for_device(struct device *dev,
113 dma_addr_t handle, size_t size, enum dma_data_direction dir)
114{
115 unsigned int offset = handle & (PAGE_SIZE - 1);
116 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
117 if (!arch_is_coherent())
118 __dma_page_cpu_to_dev(page, offset, size, dir);
119}
120
121static int arm_dma_set_mask(struct device *dev, u64 dma_mask);
122
123struct dma_map_ops arm_dma_ops = {
124 .alloc = arm_dma_alloc,
125 .free = arm_dma_free,
126 .mmap = arm_dma_mmap,
127 .map_page = arm_dma_map_page,
128 .unmap_page = arm_dma_unmap_page,
129 .map_sg = arm_dma_map_sg,
130 .unmap_sg = arm_dma_unmap_sg,
131 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
132 .sync_single_for_device = arm_dma_sync_single_for_device,
133 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
134 .sync_sg_for_device = arm_dma_sync_sg_for_device,
135 .set_dma_mask = arm_dma_set_mask,
136};
137EXPORT_SYMBOL(arm_dma_ops);
138
139static u64 get_coherent_dma_mask(struct device *dev)
140{
141 u64 mask = (u64)arm_dma_limit;
142
143 if (dev) {
144 mask = dev->coherent_dma_mask;
145
146 /*
147 * Sanity check the DMA mask - it must be non-zero, and
148 * must be able to be satisfied by a DMA allocation.
149 */
150 if (mask == 0) {
151 dev_warn(dev, "coherent DMA mask is unset\n");
152 return 0;
153 }
154
155 if ((~mask) & (u64)arm_dma_limit) {
156 dev_warn(dev, "coherent DMA mask %#llx is smaller "
157 "than system GFP_DMA mask %#llx\n",
158 mask, (u64)arm_dma_limit);
159 return 0;
160 }
161 }
162
163 return mask;
164}
165
166static void __dma_clear_buffer(struct page *page, size_t size)
167{
168 void *ptr;
169 /*
170 * Ensure that the allocated pages are zeroed, and that any data
171 * lurking in the kernel direct-mapped region is invalidated.
172 */
173 ptr = page_address(page);
174 if (ptr) {
175 memset(ptr, 0, size);
176 dmac_flush_range(ptr, ptr + size);
177 outer_flush_range(__pa(ptr), __pa(ptr) + size);
178 }
179}
180
181/*
182 * Allocate a DMA buffer for 'dev' of size 'size' using the
183 * specified gfp mask. Note that 'size' must be page aligned.
184 */
185static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
186{
187 unsigned long order = get_order(size);
188 struct page *page, *p, *e;
189
190 page = alloc_pages(gfp, order);
191 if (!page)
192 return NULL;
193
194 /*
195 * Now split the huge page and free the excess pages
196 */
197 split_page(page, order);
198 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
199 __free_page(p);
200
201 __dma_clear_buffer(page, size);
202
203 return page;
204}
205
206/*
207 * Free a DMA buffer. 'size' must be page aligned.
208 */
209static void __dma_free_buffer(struct page *page, size_t size)
210{
211 struct page *e = page + (size >> PAGE_SHIFT);
212
213 while (page < e) {
214 __free_page(page);
215 page++;
216 }
217}
218
219#ifdef CONFIG_MMU
220
221#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT)
222#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT)
223
224/*
225 * These are the page tables (2MB each) covering uncached, DMA consistent allocations
226 */
227static pte_t **consistent_pte;
228
229#define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M
230
231static unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE;
232
233void __init init_consistent_dma_size(unsigned long size)
234{
235 unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M);
236
237 BUG_ON(consistent_pte); /* Check we're called before DMA region init */
238 BUG_ON(base < VMALLOC_END);
239
240 /* Grow region to accommodate specified size */
241 if (base < consistent_base)
242 consistent_base = base;
243}
244
245#include "vmregion.h"
246
247static struct arm_vmregion_head consistent_head = {
248 .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock),
249 .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
250 .vm_end = CONSISTENT_END,
251};
252
253#ifdef CONFIG_HUGETLB_PAGE
254#error ARM Coherent DMA allocator does not (yet) support huge TLB
255#endif
256
257/*
258 * Initialise the consistent memory allocation.
259 */
260static int __init consistent_init(void)
261{
262 int ret = 0;
263 pgd_t *pgd;
264 pud_t *pud;
265 pmd_t *pmd;
266 pte_t *pte;
267 int i = 0;
268 unsigned long base = consistent_base;
269 unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT;
270
271 if (IS_ENABLED(CONFIG_CMA) && !IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU))
272 return 0;
273
274 consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
275 if (!consistent_pte) {
276 pr_err("%s: no memory\n", __func__);
277 return -ENOMEM;
278 }
279
280 pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END);
281 consistent_head.vm_start = base;
282
283 do {
284 pgd = pgd_offset(&init_mm, base);
285
286 pud = pud_alloc(&init_mm, pgd, base);
287 if (!pud) {
288 pr_err("%s: no pud tables\n", __func__);
289 ret = -ENOMEM;
290 break;
291 }
292
293 pmd = pmd_alloc(&init_mm, pud, base);
294 if (!pmd) {
295 pr_err("%s: no pmd tables\n", __func__);
296 ret = -ENOMEM;
297 break;
298 }
299 WARN_ON(!pmd_none(*pmd));
300
301 pte = pte_alloc_kernel(pmd, base);
302 if (!pte) {
303 pr_err("%s: no pte tables\n", __func__);
304 ret = -ENOMEM;
305 break;
306 }
307
308 consistent_pte[i++] = pte;
309 base += PMD_SIZE;
310 } while (base < CONSISTENT_END);
311
312 return ret;
313}
314core_initcall(consistent_init);
315
316static void *__alloc_from_contiguous(struct device *dev, size_t size,
317 pgprot_t prot, struct page **ret_page);
318
319static struct arm_vmregion_head coherent_head = {
320 .vm_lock = __SPIN_LOCK_UNLOCKED(&coherent_head.vm_lock),
321 .vm_list = LIST_HEAD_INIT(coherent_head.vm_list),
322};
323
324static size_t coherent_pool_size = DEFAULT_CONSISTENT_DMA_SIZE / 8;
325
326static int __init early_coherent_pool(char *p)
327{
328 coherent_pool_size = memparse(p, &p);
329 return 0;
330}
331early_param("coherent_pool", early_coherent_pool);
332
333/*
334 * Initialise the coherent pool for atomic allocations.
335 */
336static int __init coherent_init(void)
337{
338 pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
339 size_t size = coherent_pool_size;
340 struct page *page;
341 void *ptr;
342
343 if (!IS_ENABLED(CONFIG_CMA))
344 return 0;
345
346 ptr = __alloc_from_contiguous(NULL, size, prot, &page);
347 if (ptr) {
348 coherent_head.vm_start = (unsigned long) ptr;
349 coherent_head.vm_end = (unsigned long) ptr + size;
350 printk(KERN_INFO "DMA: preallocated %u KiB pool for atomic coherent allocations\n",
351 (unsigned)size / 1024);
352 return 0;
353 }
354 printk(KERN_ERR "DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
355 (unsigned)size / 1024);
356 return -ENOMEM;
357}
358/*
359 * CMA is activated by core_initcall, so we must be called after it.
360 */
361postcore_initcall(coherent_init);
362
363struct dma_contig_early_reserve {
364 phys_addr_t base;
365 unsigned long size;
366};
367
368static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
369
370static int dma_mmu_remap_num __initdata;
371
372void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
373{
374 dma_mmu_remap[dma_mmu_remap_num].base = base;
375 dma_mmu_remap[dma_mmu_remap_num].size = size;
376 dma_mmu_remap_num++;
377}
378
379void __init dma_contiguous_remap(void)
380{
381 int i;
382 for (i = 0; i < dma_mmu_remap_num; i++) {
383 phys_addr_t start = dma_mmu_remap[i].base;
384 phys_addr_t end = start + dma_mmu_remap[i].size;
385 struct map_desc map;
386 unsigned long addr;
387
388 if (end > arm_lowmem_limit)
389 end = arm_lowmem_limit;
390 if (start >= end)
391 return;
392
393 map.pfn = __phys_to_pfn(start);
394 map.virtual = __phys_to_virt(start);
395 map.length = end - start;
396 map.type = MT_MEMORY_DMA_READY;
397
398 /*
399 * Clear previous low-memory mapping
400 */
401 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
402 addr += PMD_SIZE)
403 pmd_clear(pmd_off_k(addr));
404
405 iotable_init(&map, 1);
406 }
407}
408
409static void *
410__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
411 const void *caller)
412{
413 struct arm_vmregion *c;
414 size_t align;
415 int bit;
416
417 if (!consistent_pte) {
418 pr_err("%s: not initialised\n", __func__);
419 dump_stack();
420 return NULL;
421 }
422
423 /*
424 * Align the virtual region allocation - maximum alignment is
425 * a section size, minimum is a page size. This helps reduce
426 * fragmentation of the DMA space, and also prevents allocations
427 * smaller than a section from crossing a section boundary.
428 */
429 bit = fls(size - 1);
430 if (bit > SECTION_SHIFT)
431 bit = SECTION_SHIFT;
432 align = 1 << bit;
433
434 /*
435 * Allocate a virtual address in the consistent mapping region.
436 */
437 c = arm_vmregion_alloc(&consistent_head, align, size,
438 gfp & ~(__GFP_DMA | __GFP_HIGHMEM), caller);
439 if (c) {
440 pte_t *pte;
441 int idx = CONSISTENT_PTE_INDEX(c->vm_start);
442 u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
443
444 pte = consistent_pte[idx] + off;
445 c->priv = page;
446
447 do {
448 BUG_ON(!pte_none(*pte));
449
450 set_pte_ext(pte, mk_pte(page, prot), 0);
451 page++;
452 pte++;
453 off++;
454 if (off >= PTRS_PER_PTE) {
455 off = 0;
456 pte = consistent_pte[++idx];
457 }
458 } while (size -= PAGE_SIZE);
459
460 dsb();
461
462 return (void *)c->vm_start;
463 }
464 return NULL;
465}
466
467static void __dma_free_remap(void *cpu_addr, size_t size)
468{
469 struct arm_vmregion *c;
470 unsigned long addr;
471 pte_t *ptep;
472 int idx;
473 u32 off;
474
475 c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr);
476 if (!c) {
477 pr_err("%s: trying to free invalid coherent area: %p\n",
478 __func__, cpu_addr);
479 dump_stack();
480 return;
481 }
482
483 if ((c->vm_end - c->vm_start) != size) {
484 pr_err("%s: freeing wrong coherent size (%ld != %d)\n",
485 __func__, c->vm_end - c->vm_start, size);
486 dump_stack();
487 size = c->vm_end - c->vm_start;
488 }
489
490 idx = CONSISTENT_PTE_INDEX(c->vm_start);
491 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
492 ptep = consistent_pte[idx] + off;
493 addr = c->vm_start;
494 do {
495 pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
496
497 ptep++;
498 addr += PAGE_SIZE;
499 off++;
500 if (off >= PTRS_PER_PTE) {
501 off = 0;
502 ptep = consistent_pte[++idx];
503 }
504
505 if (pte_none(pte) || !pte_present(pte))
506 pr_crit("%s: bad page in kernel page table\n",
507 __func__);
508 } while (size -= PAGE_SIZE);
509
510 flush_tlb_kernel_range(c->vm_start, c->vm_end);
511
512 arm_vmregion_free(&consistent_head, c);
513}
514
515static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
516 void *data)
517{
518 struct page *page = virt_to_page(addr);
519 pgprot_t prot = *(pgprot_t *)data;
520
521 set_pte_ext(pte, mk_pte(page, prot), 0);
522 return 0;
523}
524
525static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
526{
527 unsigned long start = (unsigned long) page_address(page);
528 unsigned end = start + size;
529
530 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
531 dsb();
532 flush_tlb_kernel_range(start, end);
533}
534
535static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
536 pgprot_t prot, struct page **ret_page,
537 const void *caller)
538{
539 struct page *page;
540 void *ptr;
541 page = __dma_alloc_buffer(dev, size, gfp);
542 if (!page)
543 return NULL;
544
545 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
546 if (!ptr) {
547 __dma_free_buffer(page, size);
548 return NULL;
549 }
550
551 *ret_page = page;
552 return ptr;
553}
554
555static void *__alloc_from_pool(struct device *dev, size_t size,
556 struct page **ret_page, const void *caller)
557{
558 struct arm_vmregion *c;
559 size_t align;
560
561 if (!coherent_head.vm_start) {
562 printk(KERN_ERR "%s: coherent pool not initialised!\n",
563 __func__);
564 dump_stack();
565 return NULL;
566 }
567
568 /*
569 * Align the region allocation - allocations from pool are rather
570 * small, so align them to their order in pages, minimum is a page
571 * size. This helps reduce fragmentation of the DMA space.
572 */
573 align = PAGE_SIZE << get_order(size);
574 c = arm_vmregion_alloc(&coherent_head, align, size, 0, caller);
575 if (c) {
576 void *ptr = (void *)c->vm_start;
577 struct page *page = virt_to_page(ptr);
578 *ret_page = page;
579 return ptr;
580 }
581 return NULL;
582}
583
584static int __free_from_pool(void *cpu_addr, size_t size)
585{
586 unsigned long start = (unsigned long)cpu_addr;
587 unsigned long end = start + size;
588 struct arm_vmregion *c;
589
590 if (start < coherent_head.vm_start || end > coherent_head.vm_end)
591 return 0;
592
593 c = arm_vmregion_find_remove(&coherent_head, (unsigned long)start);
594
595 if ((c->vm_end - c->vm_start) != size) {
596 printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
597 __func__, c->vm_end - c->vm_start, size);
598 dump_stack();
599 size = c->vm_end - c->vm_start;
600 }
601
602 arm_vmregion_free(&coherent_head, c);
603 return 1;
604}
605
606static void *__alloc_from_contiguous(struct device *dev, size_t size,
607 pgprot_t prot, struct page **ret_page)
608{
609 unsigned long order = get_order(size);
610 size_t count = size >> PAGE_SHIFT;
611 struct page *page;
612
613 page = dma_alloc_from_contiguous(dev, count, order);
614 if (!page)
615 return NULL;
616
617 __dma_clear_buffer(page, size);
618 __dma_remap(page, size, prot);
619
620 *ret_page = page;
621 return page_address(page);
622}
623
624static void __free_from_contiguous(struct device *dev, struct page *page,
625 size_t size)
626{
627 __dma_remap(page, size, pgprot_kernel);
628 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
629}
630
631static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
632{
633 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
634 pgprot_writecombine(prot) :
635 pgprot_dmacoherent(prot);
636 return prot;
637}
638
639#define nommu() 0
640
641#else /* !CONFIG_MMU */
642
643#define nommu() 1
644
645#define __get_dma_pgprot(attrs, prot) __pgprot(0)
646#define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
647#define __alloc_from_pool(dev, size, ret_page, c) NULL
648#define __alloc_from_contiguous(dev, size, prot, ret) NULL
649#define __free_from_pool(cpu_addr, size) 0
650#define __free_from_contiguous(dev, page, size) do { } while (0)
651#define __dma_free_remap(cpu_addr, size) do { } while (0)
652
653#endif /* CONFIG_MMU */
654
655static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
656 struct page **ret_page)
657{
658 struct page *page;
659 page = __dma_alloc_buffer(dev, size, gfp);
660 if (!page)
661 return NULL;
662
663 *ret_page = page;
664 return page_address(page);
665}
666
667
668
669static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
670 gfp_t gfp, pgprot_t prot, const void *caller)
671{
672 u64 mask = get_coherent_dma_mask(dev);
673 struct page *page;
674 void *addr;
675
676#ifdef CONFIG_DMA_API_DEBUG
677 u64 limit = (mask + 1) & ~mask;
678 if (limit && size >= limit) {
679 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
680 size, mask);
681 return NULL;
682 }
683#endif
684
685 if (!mask)
686 return NULL;
687
688 if (mask < 0xffffffffULL)
689 gfp |= GFP_DMA;
690
691 /*
692 * Following is a work-around (a.k.a. hack) to prevent pages
693 * with __GFP_COMP being passed to split_page() which cannot
694 * handle them. The real problem is that this flag probably
695 * should be 0 on ARM as it is not supported on this
696 * platform; see CONFIG_HUGETLBFS.
697 */
698 gfp &= ~(__GFP_COMP);
699
700 *handle = DMA_ERROR_CODE;
701 size = PAGE_ALIGN(size);
702
703 if (arch_is_coherent() || nommu())
704 addr = __alloc_simple_buffer(dev, size, gfp, &page);
705 else if (!IS_ENABLED(CONFIG_CMA))
706 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
707 else if (gfp & GFP_ATOMIC)
708 addr = __alloc_from_pool(dev, size, &page, caller);
709 else
710 addr = __alloc_from_contiguous(dev, size, prot, &page);
711
712 if (addr)
713 *handle = pfn_to_dma(dev, page_to_pfn(page));
714
715 return addr;
716}
717
718/*
719 * Allocate DMA-coherent memory space and return both the kernel remapped
720 * virtual and bus address for that space.
721 */
722void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
723 gfp_t gfp, struct dma_attrs *attrs)
724{
725 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
726 void *memory;
727
728 if (dma_alloc_from_coherent(dev, size, handle, &memory))
729 return memory;
730
731 return __dma_alloc(dev, size, handle, gfp, prot,
732 __builtin_return_address(0));
733}
734
735/*
736 * Create userspace mapping for the DMA-coherent memory.
737 */
738int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
739 void *cpu_addr, dma_addr_t dma_addr, size_t size,
740 struct dma_attrs *attrs)
741{
742 int ret = -ENXIO;
743#ifdef CONFIG_MMU
744 unsigned long pfn = dma_to_pfn(dev, dma_addr);
745 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
746
747 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
748 return ret;
749
750 ret = remap_pfn_range(vma, vma->vm_start,
751 pfn + vma->vm_pgoff,
752 vma->vm_end - vma->vm_start,
753 vma->vm_page_prot);
754#endif /* CONFIG_MMU */
755
756 return ret;
757}
758
759/*
760 * Free a buffer as defined by the above mapping.
761 */
762void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
763 dma_addr_t handle, struct dma_attrs *attrs)
764{
765 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
766
767 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
768 return;
769
770 size = PAGE_ALIGN(size);
771
772 if (arch_is_coherent() || nommu()) {
773 __dma_free_buffer(page, size);
774 } else if (!IS_ENABLED(CONFIG_CMA)) {
775 __dma_free_remap(cpu_addr, size);
776 __dma_free_buffer(page, size);
777 } else {
778 if (__free_from_pool(cpu_addr, size))
779 return;
780 /*
781 * Non-atomic allocations cannot be freed with IRQs disabled
782 */
783 WARN_ON(irqs_disabled());
784 __free_from_contiguous(dev, page, size);
785 }
786}
787
788static void dma_cache_maint_page(struct page *page, unsigned long offset,
789 size_t size, enum dma_data_direction dir,
790 void (*op)(const void *, size_t, int))
791{
792 /*
793 * A single sg entry may refer to multiple physically contiguous
794 * pages. But we still need to process highmem pages individually.
795 * If highmem is not configured then the bulk of this loop gets
796 * optimized out.
797 */
798 size_t left = size;
799 do {
800 size_t len = left;
801 void *vaddr;
802
803 if (PageHighMem(page)) {
804 if (len + offset > PAGE_SIZE) {
805 if (offset >= PAGE_SIZE) {
806 page += offset / PAGE_SIZE;
807 offset %= PAGE_SIZE;
808 }
809 len = PAGE_SIZE - offset;
810 }
811 vaddr = kmap_high_get(page);
812 if (vaddr) {
813 vaddr += offset;
814 op(vaddr, len, dir);
815 kunmap_high(page);
816 } else if (cache_is_vipt()) {
817 /* unmapped pages might still be cached */
818 vaddr = kmap_atomic(page);
819 op(vaddr + offset, len, dir);
820 kunmap_atomic(vaddr);
821 }
822 } else {
823 vaddr = page_address(page) + offset;
824 op(vaddr, len, dir);
825 }
826 offset = 0;
827 page++;
828 left -= len;
829 } while (left);
830}
831
832/*
833 * Make an area consistent for devices.
834 * Note: Drivers should NOT use this function directly, as it will break
835 * platforms with CONFIG_DMABOUNCE.
836 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
837 */
838static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
839 size_t size, enum dma_data_direction dir)
840{
841 unsigned long paddr;
842
843 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
844
845 paddr = page_to_phys(page) + off;
846 if (dir == DMA_FROM_DEVICE) {
847 outer_inv_range(paddr, paddr + size);
848 } else {
849 outer_clean_range(paddr, paddr + size);
850 }
851 /* FIXME: non-speculating: flush on bidirectional mappings? */
852}
853
854static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
855 size_t size, enum dma_data_direction dir)
856{
857 unsigned long paddr = page_to_phys(page) + off;
858
859 /* FIXME: non-speculating: not required */
860 /* don't bother invalidating if DMA to device */
861 if (dir != DMA_TO_DEVICE)
862 outer_inv_range(paddr, paddr + size);
863
864 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
865
866 /*
867 * Mark the D-cache clean for this page to avoid extra flushing.
868 */
869 if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
870 set_bit(PG_dcache_clean, &page->flags);
871}
872
873/**
874 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
875 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
876 * @sg: list of buffers
877 * @nents: number of buffers to map
878 * @dir: DMA transfer direction
879 *
880 * Map a set of buffers described by scatterlist in streaming mode for DMA.
881 * This is the scatter-gather version of the dma_map_single interface.
882 * Here the scatter gather list elements are each tagged with the
883 * appropriate dma address and length. They are obtained via
884 * sg_dma_{address,length}.
885 *
886 * Device ownership issues as mentioned for dma_map_single are the same
887 * here.
888 */
889int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
890 enum dma_data_direction dir, struct dma_attrs *attrs)
891{
892 struct dma_map_ops *ops = get_dma_ops(dev);
893 struct scatterlist *s;
894 int i, j;
895
896 for_each_sg(sg, s, nents, i) {
897#ifdef CONFIG_NEED_SG_DMA_LENGTH
898 s->dma_length = s->length;
899#endif
900 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
901 s->length, dir, attrs);
902 if (dma_mapping_error(dev, s->dma_address))
903 goto bad_mapping;
904 }
905 return nents;
906
907 bad_mapping:
908 for_each_sg(sg, s, i, j)
909 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
910 return 0;
911}
912
913/**
914 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
915 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
916 * @sg: list of buffers
917 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
918 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
919 *
920 * Unmap a set of streaming mode DMA translations. Again, CPU access
921 * rules concerning calls here are the same as for dma_unmap_single().
922 */
923void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
924 enum dma_data_direction dir, struct dma_attrs *attrs)
925{
926 struct dma_map_ops *ops = get_dma_ops(dev);
927 struct scatterlist *s;
928
929 int i;
930
931 for_each_sg(sg, s, nents, i)
932 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
933}
934
935/**
936 * arm_dma_sync_sg_for_cpu
937 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
938 * @sg: list of buffers
939 * @nents: number of buffers to map (returned from dma_map_sg)
940 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
941 */
942void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
943 int nents, enum dma_data_direction dir)
944{
945 struct dma_map_ops *ops = get_dma_ops(dev);
946 struct scatterlist *s;
947 int i;
948
949 for_each_sg(sg, s, nents, i)
950 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
951 dir);
952}
953
954/**
955 * arm_dma_sync_sg_for_device
956 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
957 * @sg: list of buffers
958 * @nents: number of buffers to map (returned from dma_map_sg)
959 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
960 */
961void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
962 int nents, enum dma_data_direction dir)
963{
964 struct dma_map_ops *ops = get_dma_ops(dev);
965 struct scatterlist *s;
966 int i;
967
968 for_each_sg(sg, s, nents, i)
969 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
970 dir);
971}
972
973/*
974 * Return whether the given device DMA address mask can be supported
975 * properly. For example, if your device can only drive the low 24-bits
976 * during bus mastering, then you would pass 0x00ffffff as the mask
977 * to this function.
978 */
979int dma_supported(struct device *dev, u64 mask)
980{
981 if (mask < (u64)arm_dma_limit)
982 return 0;
983 return 1;
984}
985EXPORT_SYMBOL(dma_supported);
986
987static int arm_dma_set_mask(struct device *dev, u64 dma_mask)
988{
989 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
990 return -EIO;
991
992 *dev->dma_mask = dma_mask;
993
994 return 0;
995}
996
997#define PREALLOC_DMA_DEBUG_ENTRIES 4096
998
999static int __init dma_debug_do_init(void)
1000{
1001#ifdef CONFIG_MMU
1002 arm_vmregion_create_proc("dma-mappings", &consistent_head);
1003#endif
1004 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1005 return 0;
1006}
1007fs_initcall(dma_debug_do_init);
1008
1009#ifdef CONFIG_ARM_DMA_USE_IOMMU
1010
1011/* IOMMU */
1012
1013static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1014 size_t size)
1015{
1016 unsigned int order = get_order(size);
1017 unsigned int align = 0;
1018 unsigned int count, start;
1019 unsigned long flags;
1020
1021 count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
1022 (1 << mapping->order) - 1) >> mapping->order;
1023
1024 if (order > mapping->order)
1025 align = (1 << (order - mapping->order)) - 1;
1026
1027 spin_lock_irqsave(&mapping->lock, flags);
1028 start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
1029 count, align);
1030 if (start > mapping->bits) {
1031 spin_unlock_irqrestore(&mapping->lock, flags);
1032 return DMA_ERROR_CODE;
1033 }
1034
1035 bitmap_set(mapping->bitmap, start, count);
1036 spin_unlock_irqrestore(&mapping->lock, flags);
1037
1038 return mapping->base + (start << (mapping->order + PAGE_SHIFT));
1039}
1040
1041static inline void __free_iova(struct dma_iommu_mapping *mapping,
1042 dma_addr_t addr, size_t size)
1043{
1044 unsigned int start = (addr - mapping->base) >>
1045 (mapping->order + PAGE_SHIFT);
1046 unsigned int count = ((size >> PAGE_SHIFT) +
1047 (1 << mapping->order) - 1) >> mapping->order;
1048 unsigned long flags;
1049
1050 spin_lock_irqsave(&mapping->lock, flags);
1051 bitmap_clear(mapping->bitmap, start, count);
1052 spin_unlock_irqrestore(&mapping->lock, flags);
1053}
1054
1055static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
1056{
1057 struct page **pages;
1058 int count = size >> PAGE_SHIFT;
1059 int array_size = count * sizeof(struct page *);
1060 int i = 0;
1061
1062 if (array_size <= PAGE_SIZE)
1063 pages = kzalloc(array_size, gfp);
1064 else
1065 pages = vzalloc(array_size);
1066 if (!pages)
1067 return NULL;
1068
1069 while (count) {
1070 int j, order = __fls(count);
1071
1072 pages[i] = alloc_pages(gfp | __GFP_NOWARN, order);
1073 while (!pages[i] && order)
1074 pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order);
1075 if (!pages[i])
1076 goto error;
1077
1078 if (order)
1079 split_page(pages[i], order);
1080 j = 1 << order;
1081 while (--j)
1082 pages[i + j] = pages[i] + j;
1083
1084 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1085 i += 1 << order;
1086 count -= 1 << order;
1087 }
1088
1089 return pages;
1090error:
1091 while (--i)
1092 if (pages[i])
1093 __free_pages(pages[i], 0);
1094 if (array_size <= PAGE_SIZE)
1095 kfree(pages);
1096 else
1097 vfree(pages);
1098 return NULL;
1099}
1100
1101static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t size)
1102{
1103 int count = size >> PAGE_SHIFT;
1104 int array_size = count * sizeof(struct page *);
1105 int i;
1106 for (i = 0; i < count; i++)
1107 if (pages[i])
1108 __free_pages(pages[i], 0);
1109 if (array_size <= PAGE_SIZE)
1110 kfree(pages);
1111 else
1112 vfree(pages);
1113 return 0;
1114}
1115
1116/*
1117 * Create a CPU mapping for a specified pages
1118 */
1119static void *
1120__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot)
1121{
1122 struct arm_vmregion *c;
1123 size_t align;
1124 size_t count = size >> PAGE_SHIFT;
1125 int bit;
1126
1127 if (!consistent_pte[0]) {
1128 pr_err("%s: not initialised\n", __func__);
1129 dump_stack();
1130 return NULL;
1131 }
1132
1133 /*
1134 * Align the virtual region allocation - maximum alignment is
1135 * a section size, minimum is a page size. This helps reduce
1136 * fragmentation of the DMA space, and also prevents allocations
1137 * smaller than a section from crossing a section boundary.
1138 */
1139 bit = fls(size - 1);
1140 if (bit > SECTION_SHIFT)
1141 bit = SECTION_SHIFT;
1142 align = 1 << bit;
1143
1144 /*
1145 * Allocate a virtual address in the consistent mapping region.
1146 */
1147 c = arm_vmregion_alloc(&consistent_head, align, size,
1148 gfp & ~(__GFP_DMA | __GFP_HIGHMEM), NULL);
1149 if (c) {
1150 pte_t *pte;
1151 int idx = CONSISTENT_PTE_INDEX(c->vm_start);
1152 int i = 0;
1153 u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
1154
1155 pte = consistent_pte[idx] + off;
1156 c->priv = pages;
1157
1158 do {
1159 BUG_ON(!pte_none(*pte));
1160
1161 set_pte_ext(pte, mk_pte(pages[i], prot), 0);
1162 pte++;
1163 off++;
1164 i++;
1165 if (off >= PTRS_PER_PTE) {
1166 off = 0;
1167 pte = consistent_pte[++idx];
1168 }
1169 } while (i < count);
1170
1171 dsb();
1172
1173 return (void *)c->vm_start;
1174 }
1175 return NULL;
1176}
1177
1178/*
1179 * Create a mapping in device IO address space for specified pages
1180 */
1181static dma_addr_t
1182__iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1183{
1184 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1185 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1186 dma_addr_t dma_addr, iova;
1187 int i, ret = DMA_ERROR_CODE;
1188
1189 dma_addr = __alloc_iova(mapping, size);
1190 if (dma_addr == DMA_ERROR_CODE)
1191 return dma_addr;
1192
1193 iova = dma_addr;
1194 for (i = 0; i < count; ) {
1195 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1196 phys_addr_t phys = page_to_phys(pages[i]);
1197 unsigned int len, j;
1198
1199 for (j = i + 1; j < count; j++, next_pfn++)
1200 if (page_to_pfn(pages[j]) != next_pfn)
1201 break;
1202
1203 len = (j - i) << PAGE_SHIFT;
1204 ret = iommu_map(mapping->domain, iova, phys, len, 0);
1205 if (ret < 0)
1206 goto fail;
1207 iova += len;
1208 i = j;
1209 }
1210 return dma_addr;
1211fail:
1212 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1213 __free_iova(mapping, dma_addr, size);
1214 return DMA_ERROR_CODE;
1215}
1216
1217static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1218{
1219 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1220
1221 /*
1222 * add optional in-page offset from iova to size and align
1223 * result to page size
1224 */
1225 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1226 iova &= PAGE_MASK;
1227
1228 iommu_unmap(mapping->domain, iova, size);
1229 __free_iova(mapping, iova, size);
1230 return 0;
1231}
1232
1233static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1234 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1235{
1236 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
1237 struct page **pages;
1238 void *addr = NULL;
1239
1240 *handle = DMA_ERROR_CODE;
1241 size = PAGE_ALIGN(size);
1242
1243 pages = __iommu_alloc_buffer(dev, size, gfp);
1244 if (!pages)
1245 return NULL;
1246
1247 *handle = __iommu_create_mapping(dev, pages, size);
1248 if (*handle == DMA_ERROR_CODE)
1249 goto err_buffer;
1250
1251 addr = __iommu_alloc_remap(pages, size, gfp, prot);
1252 if (!addr)
1253 goto err_mapping;
1254
1255 return addr;
1256
1257err_mapping:
1258 __iommu_remove_mapping(dev, *handle, size);
1259err_buffer:
1260 __iommu_free_buffer(dev, pages, size);
1261 return NULL;
1262}
1263
1264static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1265 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1266 struct dma_attrs *attrs)
1267{
1268 struct arm_vmregion *c;
1269
1270 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1271 c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
1272
1273 if (c) {
1274 struct page **pages = c->priv;
1275
1276 unsigned long uaddr = vma->vm_start;
1277 unsigned long usize = vma->vm_end - vma->vm_start;
1278 int i = 0;
1279
1280 do {
1281 int ret;
1282
1283 ret = vm_insert_page(vma, uaddr, pages[i++]);
1284 if (ret) {
1285 pr_err("Remapping memory, error: %d\n", ret);
1286 return ret;
1287 }
1288
1289 uaddr += PAGE_SIZE;
1290 usize -= PAGE_SIZE;
1291 } while (usize > 0);
1292 }
1293 return 0;
1294}
1295
1296/*
1297 * free a page as defined by the above mapping.
1298 * Must not be called with IRQs disabled.
1299 */
1300void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1301 dma_addr_t handle, struct dma_attrs *attrs)
1302{
1303 struct arm_vmregion *c;
1304 size = PAGE_ALIGN(size);
1305
1306 c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
1307 if (c) {
1308 struct page **pages = c->priv;
1309 __dma_free_remap(cpu_addr, size);
1310 __iommu_remove_mapping(dev, handle, size);
1311 __iommu_free_buffer(dev, pages, size);
1312 }
1313}
1314
1315/*
1316 * Map a part of the scatter-gather list into contiguous io address space
1317 */
1318static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1319 size_t size, dma_addr_t *handle,
1320 enum dma_data_direction dir)
1321{
1322 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1323 dma_addr_t iova, iova_base;
1324 int ret = 0;
1325 unsigned int count;
1326 struct scatterlist *s;
1327
1328 size = PAGE_ALIGN(size);
1329 *handle = DMA_ERROR_CODE;
1330
1331 iova_base = iova = __alloc_iova(mapping, size);
1332 if (iova == DMA_ERROR_CODE)
1333 return -ENOMEM;
1334
1335 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1336 phys_addr_t phys = page_to_phys(sg_page(s));
1337 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1338
1339 if (!arch_is_coherent())
1340 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1341
1342 ret = iommu_map(mapping->domain, iova, phys, len, 0);
1343 if (ret < 0)
1344 goto fail;
1345 count += len >> PAGE_SHIFT;
1346 iova += len;
1347 }
1348 *handle = iova_base;
1349
1350 return 0;
1351fail:
1352 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1353 __free_iova(mapping, iova_base, size);
1354 return ret;
1355}
1356
1357/**
1358 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1359 * @dev: valid struct device pointer
1360 * @sg: list of buffers
1361 * @nents: number of buffers to map
1362 * @dir: DMA transfer direction
1363 *
1364 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1365 * The scatter gather list elements are merged together (if possible) and
1366 * tagged with the appropriate dma address and length. They are obtained via
1367 * sg_dma_{address,length}.
1368 */
1369int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1370 enum dma_data_direction dir, struct dma_attrs *attrs)
1371{
1372 struct scatterlist *s = sg, *dma = sg, *start = sg;
1373 int i, count = 0;
1374 unsigned int offset = s->offset;
1375 unsigned int size = s->offset + s->length;
1376 unsigned int max = dma_get_max_seg_size(dev);
1377
1378 for (i = 1; i < nents; i++) {
1379 s = sg_next(s);
1380
1381 s->dma_address = DMA_ERROR_CODE;
1382 s->dma_length = 0;
1383
1384 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1385 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1386 dir) < 0)
1387 goto bad_mapping;
1388
1389 dma->dma_address += offset;
1390 dma->dma_length = size - offset;
1391
1392 size = offset = s->offset;
1393 start = s;
1394 dma = sg_next(dma);
1395 count += 1;
1396 }
1397 size += s->length;
1398 }
1399 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir) < 0)
1400 goto bad_mapping;
1401
1402 dma->dma_address += offset;
1403 dma->dma_length = size - offset;
1404
1405 return count+1;
1406
1407bad_mapping:
1408 for_each_sg(sg, s, count, i)
1409 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1410 return 0;
1411}
1412
1413/**
1414 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1415 * @dev: valid struct device pointer
1416 * @sg: list of buffers
1417 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1418 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1419 *
1420 * Unmap a set of streaming mode DMA translations. Again, CPU access
1421 * rules concerning calls here are the same as for dma_unmap_single().
1422 */
1423void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1424 enum dma_data_direction dir, struct dma_attrs *attrs)
1425{
1426 struct scatterlist *s;
1427 int i;
1428
1429 for_each_sg(sg, s, nents, i) {
1430 if (sg_dma_len(s))
1431 __iommu_remove_mapping(dev, sg_dma_address(s),
1432 sg_dma_len(s));
1433 if (!arch_is_coherent())
1434 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1435 s->length, dir);
1436 }
1437}
1438
1439/**
1440 * arm_iommu_sync_sg_for_cpu
1441 * @dev: valid struct device pointer
1442 * @sg: list of buffers
1443 * @nents: number of buffers to map (returned from dma_map_sg)
1444 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1445 */
1446void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1447 int nents, enum dma_data_direction dir)
1448{
1449 struct scatterlist *s;
1450 int i;
1451
1452 for_each_sg(sg, s, nents, i)
1453 if (!arch_is_coherent())
1454 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1455
1456}
1457
1458/**
1459 * arm_iommu_sync_sg_for_device
1460 * @dev: valid struct device pointer
1461 * @sg: list of buffers
1462 * @nents: number of buffers to map (returned from dma_map_sg)
1463 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1464 */
1465void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1466 int nents, enum dma_data_direction dir)
1467{
1468 struct scatterlist *s;
1469 int i;
1470
1471 for_each_sg(sg, s, nents, i)
1472 if (!arch_is_coherent())
1473 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1474}
1475
1476
1477/**
1478 * arm_iommu_map_page
1479 * @dev: valid struct device pointer
1480 * @page: page that buffer resides in
1481 * @offset: offset into page for start of buffer
1482 * @size: size of buffer to map
1483 * @dir: DMA transfer direction
1484 *
1485 * IOMMU aware version of arm_dma_map_page()
1486 */
1487static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1488 unsigned long offset, size_t size, enum dma_data_direction dir,
1489 struct dma_attrs *attrs)
1490{
1491 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1492 dma_addr_t dma_addr;
1493 int ret, len = PAGE_ALIGN(size + offset);
1494
1495 if (!arch_is_coherent())
1496 __dma_page_cpu_to_dev(page, offset, size, dir);
1497
1498 dma_addr = __alloc_iova(mapping, len);
1499 if (dma_addr == DMA_ERROR_CODE)
1500 return dma_addr;
1501
1502 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0);
1503 if (ret < 0)
1504 goto fail;
1505
1506 return dma_addr + offset;
1507fail:
1508 __free_iova(mapping, dma_addr, len);
1509 return DMA_ERROR_CODE;
1510}
1511
1512/**
1513 * arm_iommu_unmap_page
1514 * @dev: valid struct device pointer
1515 * @handle: DMA address of buffer
1516 * @size: size of buffer (same as passed to dma_map_page)
1517 * @dir: DMA transfer direction (same as passed to dma_map_page)
1518 *
1519 * IOMMU aware version of arm_dma_unmap_page()
1520 */
1521static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1522 size_t size, enum dma_data_direction dir,
1523 struct dma_attrs *attrs)
1524{
1525 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1526 dma_addr_t iova = handle & PAGE_MASK;
1527 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1528 int offset = handle & ~PAGE_MASK;
1529 int len = PAGE_ALIGN(size + offset);
1530
1531 if (!iova)
1532 return;
1533
1534 if (!arch_is_coherent())
1535 __dma_page_dev_to_cpu(page, offset, size, dir);
1536
1537 iommu_unmap(mapping->domain, iova, len);
1538 __free_iova(mapping, iova, len);
1539}
1540
1541static void arm_iommu_sync_single_for_cpu(struct device *dev,
1542 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1543{
1544 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1545 dma_addr_t iova = handle & PAGE_MASK;
1546 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1547 unsigned int offset = handle & ~PAGE_MASK;
1548
1549 if (!iova)
1550 return;
1551
1552 if (!arch_is_coherent())
1553 __dma_page_dev_to_cpu(page, offset, size, dir);
1554}
1555
1556static void arm_iommu_sync_single_for_device(struct device *dev,
1557 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1558{
1559 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1560 dma_addr_t iova = handle & PAGE_MASK;
1561 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1562 unsigned int offset = handle & ~PAGE_MASK;
1563
1564 if (!iova)
1565 return;
1566
1567 __dma_page_cpu_to_dev(page, offset, size, dir);
1568}
1569
1570struct dma_map_ops iommu_ops = {
1571 .alloc = arm_iommu_alloc_attrs,
1572 .free = arm_iommu_free_attrs,
1573 .mmap = arm_iommu_mmap_attrs,
1574
1575 .map_page = arm_iommu_map_page,
1576 .unmap_page = arm_iommu_unmap_page,
1577 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1578 .sync_single_for_device = arm_iommu_sync_single_for_device,
1579
1580 .map_sg = arm_iommu_map_sg,
1581 .unmap_sg = arm_iommu_unmap_sg,
1582 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1583 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1584};
1585
1586/**
1587 * arm_iommu_create_mapping
1588 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1589 * @base: start address of the valid IO address space
1590 * @size: size of the valid IO address space
1591 * @order: accuracy of the IO addresses allocations
1592 *
1593 * Creates a mapping structure which holds information about used/unused
1594 * IO address ranges, which is required to perform memory allocation and
1595 * mapping with IOMMU aware functions.
1596 *
1597 * The client device need to be attached to the mapping with
1598 * arm_iommu_attach_device function.
1599 */
1600struct dma_iommu_mapping *
1601arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
1602 int order)
1603{
1604 unsigned int count = size >> (PAGE_SHIFT + order);
1605 unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
1606 struct dma_iommu_mapping *mapping;
1607 int err = -ENOMEM;
1608
1609 if (!count)
1610 return ERR_PTR(-EINVAL);
1611
1612 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1613 if (!mapping)
1614 goto err;
1615
1616 mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1617 if (!mapping->bitmap)
1618 goto err2;
1619
1620 mapping->base = base;
1621 mapping->bits = BITS_PER_BYTE * bitmap_size;
1622 mapping->order = order;
1623 spin_lock_init(&mapping->lock);
1624
1625 mapping->domain = iommu_domain_alloc(bus);
1626 if (!mapping->domain)
1627 goto err3;
1628
1629 kref_init(&mapping->kref);
1630 return mapping;
1631err3:
1632 kfree(mapping->bitmap);
1633err2:
1634 kfree(mapping);
1635err:
1636 return ERR_PTR(err);
1637}
1638
1639static void release_iommu_mapping(struct kref *kref)
1640{
1641 struct dma_iommu_mapping *mapping =
1642 container_of(kref, struct dma_iommu_mapping, kref);
1643
1644 iommu_domain_free(mapping->domain);
1645 kfree(mapping->bitmap);
1646 kfree(mapping);
1647}
1648
1649void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1650{
1651 if (mapping)
1652 kref_put(&mapping->kref, release_iommu_mapping);
1653}
1654
1655/**
1656 * arm_iommu_attach_device
1657 * @dev: valid struct device pointer
1658 * @mapping: io address space mapping structure (returned from
1659 * arm_iommu_create_mapping)
1660 *
1661 * Attaches specified io address space mapping to the provided device,
1662 * this replaces the dma operations (dma_map_ops pointer) with the
1663 * IOMMU aware version. More than one client might be attached to
1664 * the same io address space mapping.
1665 */
1666int arm_iommu_attach_device(struct device *dev,
1667 struct dma_iommu_mapping *mapping)
1668{
1669 int err;
1670
1671 err = iommu_attach_device(mapping->domain, dev);
1672 if (err)
1673 return err;
1674
1675 kref_get(&mapping->kref);
1676 dev->archdata.mapping = mapping;
1677 set_dma_ops(dev, &iommu_ops);
1678
1679 pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev));
1680 return 0;
1681}
1682
1683#endif