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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * Motherboard Express uATX
6 * V2M-P1
7 *
8 * HBI-0190D
9 *
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
11 * Technical Reference Manual)
12 *
13 * WARNING! The hardware described in this file is independent from the
14 * original variant (vexpress-v2m.dtsi), but there is a strong
15 * correspondence between the two configurations.
16 *
17 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18 * CHANGES TO vexpress-v2m.dtsi!
19 */
20#include <dt-bindings/interrupt-controller/arm-gic.h>
21
22/ {
23 v2m_fixed_3v3: fixed-regulator-0 {
24 compatible = "regulator-fixed";
25 regulator-name = "3V3";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
28 regulator-always-on;
29 };
30
31 v2m_clk24mhz: clk24mhz {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
35 clock-output-names = "v2m:clk24mhz";
36 };
37
38 v2m_refclk1mhz: refclk1mhz {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <1000000>;
42 clock-output-names = "v2m:refclk1mhz";
43 };
44
45 v2m_refclk32khz: refclk32khz {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
49 clock-output-names = "v2m:refclk32khz";
50 };
51
52 leds {
53 compatible = "gpio-leds";
54
55 led-1 {
56 label = "v2m:green:user1";
57 gpios = <&v2m_led_gpios 0 0>;
58 linux,default-trigger = "heartbeat";
59 };
60
61 led-2 {
62 label = "v2m:green:user2";
63 gpios = <&v2m_led_gpios 1 0>;
64 linux,default-trigger = "disk-activity";
65 };
66
67 led-3 {
68 label = "v2m:green:user3";
69 gpios = <&v2m_led_gpios 2 0>;
70 linux,default-trigger = "cpu0";
71 };
72
73 led-4 {
74 label = "v2m:green:user4";
75 gpios = <&v2m_led_gpios 3 0>;
76 linux,default-trigger = "cpu1";
77 };
78
79 led-5 {
80 label = "v2m:green:user5";
81 gpios = <&v2m_led_gpios 4 0>;
82 linux,default-trigger = "cpu2";
83 };
84
85 led-6 {
86 label = "v2m:green:user6";
87 gpios = <&v2m_led_gpios 5 0>;
88 linux,default-trigger = "cpu3";
89 };
90
91 led-7 {
92 label = "v2m:green:user7";
93 gpios = <&v2m_led_gpios 6 0>;
94 linux,default-trigger = "cpu4";
95 };
96
97 led-8 {
98 label = "v2m:green:user8";
99 gpios = <&v2m_led_gpios 7 0>;
100 linux,default-trigger = "cpu5";
101 };
102 };
103
104 bus@8000000 {
105 compatible = "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108
109 #interrupt-cells = <1>;
110 interrupt-map-mask = <0 63>;
111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
120 <0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
121 <0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
122 <0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
123 <0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
124 <0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
125 <0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
126 <0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
127 <0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
128 <0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
129 <0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
130 <0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
131 <0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
132 <0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
133 <0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
134 <0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
135 <0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
136 <0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
137 <0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
138 <0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
139 <0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
140 <0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
141 <0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
142 <0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
143 <0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
144 <0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
145 <0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
146 <0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
147 <0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
148 <0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
149 <0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
150 <0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
151 <0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
152 <0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
153 <0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
154
155 motherboard-bus@8000000 {
156 arm,hbi = <0x190>;
157 arm,vexpress,site = <0>;
158 compatible = "arm,vexpress,v2m-p1", "simple-bus";
159 #address-cells = <2>; /* SMB chipselect number and offset */
160 #size-cells = <1>;
161 ranges = <0 0 0x08000000 0x04000000>,
162 <1 0 0x14000000 0x04000000>,
163 <2 0 0x18000000 0x04000000>,
164 <3 0 0x1c000000 0x04000000>,
165 <4 0 0x0c000000 0x04000000>,
166 <5 0 0x10000000 0x04000000>;
167
168 nor_flash: flash@0 {
169 compatible = "arm,vexpress-flash", "cfi-flash";
170 reg = <0 0x00000000 0x04000000>,
171 <4 0x00000000 0x04000000>;
172 bank-width = <4>;
173 partitions {
174 compatible = "arm,arm-firmware-suite";
175 };
176 };
177
178 psram@100000000 {
179 compatible = "arm,vexpress-psram", "mtd-ram";
180 reg = <1 0x00000000 0x02000000>;
181 bank-width = <4>;
182 };
183
184 ethernet@202000000 {
185 compatible = "smsc,lan9118", "smsc,lan9115";
186 reg = <2 0x02000000 0x10000>;
187 interrupts = <15>;
188 phy-mode = "mii";
189 reg-io-width = <4>;
190 smsc,irq-active-high;
191 smsc,irq-push-pull;
192 vdd33a-supply = <&v2m_fixed_3v3>;
193 vddvario-supply = <&v2m_fixed_3v3>;
194 };
195
196 usb@203000000 {
197 compatible = "nxp,usb-isp1761";
198 reg = <2 0x03000000 0x20000>;
199 interrupts = <16>;
200 dr_mode = "peripheral";
201 };
202
203 iofpga-bus@300000000 {
204 compatible = "simple-bus";
205 #address-cells = <1>;
206 #size-cells = <1>;
207 ranges = <0 3 0 0x200000>;
208
209 v2m_sysreg: sysreg@10000 {
210 compatible = "arm,vexpress-sysreg";
211 reg = <0x010000 0x1000>;
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0 0x10000 0x1000>;
215
216 v2m_led_gpios: gpio@8 {
217 compatible = "arm,vexpress-sysreg,sys_led";
218 reg = <0x008 4>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 };
222
223 v2m_mmc_gpios: gpio@48 {
224 compatible = "arm,vexpress-sysreg,sys_mci";
225 reg = <0x048 4>;
226 gpio-controller;
227 #gpio-cells = <2>;
228 };
229
230 v2m_flash_gpios: gpio@4c {
231 compatible = "arm,vexpress-sysreg,sys_flash";
232 reg = <0x04c 4>;
233 gpio-controller;
234 #gpio-cells = <2>;
235 };
236 };
237
238 v2m_sysctl: sysctl@20000 {
239 compatible = "arm,sp810", "arm,primecell";
240 reg = <0x020000 0x1000>;
241 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
242 clock-names = "refclk", "timclk", "apb_pclk";
243 #clock-cells = <1>;
244 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
245 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
246 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
247 };
248
249 /* PCI-E I2C bus */
250 v2m_i2c_pcie: i2c@30000 {
251 compatible = "arm,versatile-i2c";
252 reg = <0x030000 0x1000>;
253
254 #address-cells = <1>;
255 #size-cells = <0>;
256
257 pcie-switch@60 {
258 compatible = "idt,89hpes32h8";
259 reg = <0x60>;
260 };
261 };
262
263 aaci@40000 {
264 compatible = "arm,pl041", "arm,primecell";
265 reg = <0x040000 0x1000>;
266 interrupts = <11>;
267 clocks = <&smbclk>;
268 clock-names = "apb_pclk";
269 };
270
271 mmc@50000 {
272 compatible = "arm,pl180", "arm,primecell";
273 reg = <0x050000 0x1000>;
274 interrupts = <9>, <10>;
275 cd-gpios = <&v2m_mmc_gpios 0 0>;
276 wp-gpios = <&v2m_mmc_gpios 1 0>;
277 max-frequency = <12000000>;
278 vmmc-supply = <&v2m_fixed_3v3>;
279 clocks = <&v2m_clk24mhz>, <&smbclk>;
280 clock-names = "mclk", "apb_pclk";
281 };
282
283 kmi@60000 {
284 compatible = "arm,pl050", "arm,primecell";
285 reg = <0x060000 0x1000>;
286 interrupts = <12>;
287 clocks = <&v2m_clk24mhz>, <&smbclk>;
288 clock-names = "KMIREFCLK", "apb_pclk";
289 };
290
291 kmi@70000 {
292 compatible = "arm,pl050", "arm,primecell";
293 reg = <0x070000 0x1000>;
294 interrupts = <13>;
295 clocks = <&v2m_clk24mhz>, <&smbclk>;
296 clock-names = "KMIREFCLK", "apb_pclk";
297 };
298
299 v2m_serial0: serial@90000 {
300 compatible = "arm,pl011", "arm,primecell";
301 reg = <0x090000 0x1000>;
302 interrupts = <5>;
303 clocks = <&v2m_oscclk2>, <&smbclk>;
304 clock-names = "uartclk", "apb_pclk";
305 };
306
307 v2m_serial1: serial@a0000 {
308 compatible = "arm,pl011", "arm,primecell";
309 reg = <0x0a0000 0x1000>;
310 interrupts = <6>;
311 clocks = <&v2m_oscclk2>, <&smbclk>;
312 clock-names = "uartclk", "apb_pclk";
313 };
314
315 v2m_serial2: serial@b0000 {
316 compatible = "arm,pl011", "arm,primecell";
317 reg = <0x0b0000 0x1000>;
318 interrupts = <7>;
319 clocks = <&v2m_oscclk2>, <&smbclk>;
320 clock-names = "uartclk", "apb_pclk";
321 };
322
323 v2m_serial3: serial@c0000 {
324 compatible = "arm,pl011", "arm,primecell";
325 reg = <0x0c0000 0x1000>;
326 interrupts = <8>;
327 clocks = <&v2m_oscclk2>, <&smbclk>;
328 clock-names = "uartclk", "apb_pclk";
329 };
330
331 watchdog@f0000 {
332 compatible = "arm,sp805", "arm,primecell";
333 reg = <0x0f0000 0x1000>;
334 interrupts = <0>;
335 clocks = <&v2m_refclk32khz>, <&smbclk>;
336 clock-names = "wdog_clk", "apb_pclk";
337 };
338
339 v2m_timer01: timer@110000 {
340 compatible = "arm,sp804", "arm,primecell";
341 reg = <0x110000 0x1000>;
342 interrupts = <2>;
343 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
344 clock-names = "timclken1", "timclken2", "apb_pclk";
345 };
346
347 v2m_timer23: timer@120000 {
348 compatible = "arm,sp804", "arm,primecell";
349 reg = <0x120000 0x1000>;
350 interrupts = <3>;
351 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
352 clock-names = "timclken1", "timclken2", "apb_pclk";
353 };
354
355 /* DVI I2C bus */
356 v2m_i2c_dvi: i2c@160000 {
357 compatible = "arm,versatile-i2c";
358 reg = <0x160000 0x1000>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361
362 dvi-transmitter@39 {
363 compatible = "sil,sii9022-tpi", "sil,sii9022";
364 reg = <0x39>;
365
366 ports {
367 #address-cells = <1>;
368 #size-cells = <0>;
369
370 port@0 {
371 reg = <0>;
372 dvi_bridge_in: endpoint {
373 remote-endpoint = <&clcd_pads>;
374 };
375 };
376 };
377 };
378
379 dvi-transmitter@60 {
380 compatible = "sil,sii9022-cpi", "sil,sii9022";
381 reg = <0x60>;
382 };
383 };
384
385 rtc@170000 {
386 compatible = "arm,pl031", "arm,primecell";
387 reg = <0x170000 0x1000>;
388 interrupts = <4>;
389 clocks = <&smbclk>;
390 clock-names = "apb_pclk";
391 };
392
393 compact-flash@1a0000 {
394 compatible = "arm,vexpress-cf", "ata-generic";
395 reg = <0x1a0000 0x100
396 0x1a0100 0xf00>;
397 reg-shift = <2>;
398 };
399
400 clcd@1f0000 {
401 compatible = "arm,pl111", "arm,primecell";
402 reg = <0x1f0000 0x1000>;
403 interrupt-names = "combined";
404 interrupts = <14>;
405 clocks = <&v2m_oscclk1>, <&smbclk>;
406 clock-names = "clcdclk", "apb_pclk";
407 /* 800x600 16bpp @36MHz works fine */
408 max-memory-bandwidth = <54000000>;
409 memory-region = <&vram>;
410
411 port {
412 clcd_pads: endpoint {
413 remote-endpoint = <&dvi_bridge_in>;
414 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
415 };
416 };
417 };
418
419 mcc {
420 compatible = "arm,vexpress,config-bus";
421 arm,vexpress,config-bridge = <&v2m_sysreg>;
422
423 oscclk0 {
424 /* MCC static memory clock */
425 compatible = "arm,vexpress-osc";
426 arm,vexpress-sysreg,func = <1 0>;
427 freq-range = <25000000 60000000>;
428 #clock-cells = <0>;
429 clock-output-names = "v2m:oscclk0";
430 };
431
432 v2m_oscclk1: oscclk1 {
433 /* CLCD clock */
434 compatible = "arm,vexpress-osc";
435 arm,vexpress-sysreg,func = <1 1>;
436 freq-range = <23750000 65000000>;
437 #clock-cells = <0>;
438 clock-output-names = "v2m:oscclk1";
439 };
440
441 v2m_oscclk2: oscclk2 {
442 /* IO FPGA peripheral clock */
443 compatible = "arm,vexpress-osc";
444 arm,vexpress-sysreg,func = <1 2>;
445 freq-range = <24000000 24000000>;
446 #clock-cells = <0>;
447 clock-output-names = "v2m:oscclk2";
448 };
449
450 volt-vio {
451 /* Logic level voltage */
452 compatible = "arm,vexpress-volt";
453 arm,vexpress-sysreg,func = <2 0>;
454 regulator-name = "VIO";
455 regulator-always-on;
456 label = "VIO";
457 };
458
459 temp-mcc {
460 /* MCC internal operating temperature */
461 compatible = "arm,vexpress-temp";
462 arm,vexpress-sysreg,func = <4 0>;
463 label = "MCC";
464 };
465
466 reset {
467 compatible = "arm,vexpress-reset";
468 arm,vexpress-sysreg,func = <5 0>;
469 };
470
471 muxfpga {
472 compatible = "arm,vexpress-muxfpga";
473 arm,vexpress-sysreg,func = <7 0>;
474 };
475
476 shutdown {
477 compatible = "arm,vexpress-shutdown";
478 arm,vexpress-sysreg,func = <8 0>;
479 };
480
481 reboot {
482 compatible = "arm,vexpress-reboot";
483 arm,vexpress-sysreg,func = <9 0>;
484 };
485
486 dvimode {
487 compatible = "arm,vexpress-dvimode";
488 arm,vexpress-sysreg,func = <11 0>;
489 };
490 };
491 };
492 };
493 };
494};
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * original variant (vexpress-v2m.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m.dtsi!
18 */
19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard {
26 compatible = "simple-bus";
27 arm,v2m-memory-map = "rs1";
28 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
31
32 flash@0,00000000 {
33 compatible = "arm,vexpress-flash", "cfi-flash";
34 reg = <0 0x00000000 0x04000000>,
35 <4 0x00000000 0x04000000>;
36 bank-width = <4>;
37 };
38
39 psram@1,00000000 {
40 compatible = "arm,vexpress-psram", "mtd-ram";
41 reg = <1 0x00000000 0x02000000>;
42 bank-width = <4>;
43 };
44
45 vram@2,00000000 {
46 compatible = "arm,vexpress-vram";
47 reg = <2 0x00000000 0x00800000>;
48 };
49
50 ethernet@2,02000000 {
51 compatible = "smsc,lan9118", "smsc,lan9115";
52 reg = <2 0x02000000 0x10000>;
53 interrupts = <15>;
54 phy-mode = "mii";
55 reg-io-width = <4>;
56 smsc,irq-active-high;
57 smsc,irq-push-pull;
58 };
59
60 usb@2,03000000 {
61 compatible = "nxp,usb-isp1761";
62 reg = <2 0x03000000 0x20000>;
63 interrupts = <16>;
64 port1-otg;
65 };
66
67 iofpga@3,00000000 {
68 compatible = "arm,amba-bus", "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 3 0 0x200000>;
72
73 sysreg@010000 {
74 compatible = "arm,vexpress-sysreg";
75 reg = <0x010000 0x1000>;
76 };
77
78 sysctl@020000 {
79 compatible = "arm,sp810", "arm,primecell";
80 reg = <0x020000 0x1000>;
81 };
82
83 /* PCI-E I2C bus */
84 v2m_i2c_pcie: i2c@030000 {
85 compatible = "arm,versatile-i2c";
86 reg = <0x030000 0x1000>;
87
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 pcie-switch@60 {
92 compatible = "idt,89hpes32h8";
93 reg = <0x60>;
94 };
95 };
96
97 aaci@040000 {
98 compatible = "arm,pl041", "arm,primecell";
99 reg = <0x040000 0x1000>;
100 interrupts = <11>;
101 };
102
103 mmci@050000 {
104 compatible = "arm,pl180", "arm,primecell";
105 reg = <0x050000 0x1000>;
106 interrupts = <9 10>;
107 };
108
109 kmi@060000 {
110 compatible = "arm,pl050", "arm,primecell";
111 reg = <0x060000 0x1000>;
112 interrupts = <12>;
113 };
114
115 kmi@070000 {
116 compatible = "arm,pl050", "arm,primecell";
117 reg = <0x070000 0x1000>;
118 interrupts = <13>;
119 };
120
121 v2m_serial0: uart@090000 {
122 compatible = "arm,pl011", "arm,primecell";
123 reg = <0x090000 0x1000>;
124 interrupts = <5>;
125 };
126
127 v2m_serial1: uart@0a0000 {
128 compatible = "arm,pl011", "arm,primecell";
129 reg = <0x0a0000 0x1000>;
130 interrupts = <6>;
131 };
132
133 v2m_serial2: uart@0b0000 {
134 compatible = "arm,pl011", "arm,primecell";
135 reg = <0x0b0000 0x1000>;
136 interrupts = <7>;
137 };
138
139 v2m_serial3: uart@0c0000 {
140 compatible = "arm,pl011", "arm,primecell";
141 reg = <0x0c0000 0x1000>;
142 interrupts = <8>;
143 };
144
145 wdt@0f0000 {
146 compatible = "arm,sp805", "arm,primecell";
147 reg = <0x0f0000 0x1000>;
148 interrupts = <0>;
149 };
150
151 v2m_timer01: timer@110000 {
152 compatible = "arm,sp804", "arm,primecell";
153 reg = <0x110000 0x1000>;
154 interrupts = <2>;
155 };
156
157 v2m_timer23: timer@120000 {
158 compatible = "arm,sp804", "arm,primecell";
159 reg = <0x120000 0x1000>;
160 };
161
162 /* DVI I2C bus */
163 v2m_i2c_dvi: i2c@160000 {
164 compatible = "arm,versatile-i2c";
165 reg = <0x160000 0x1000>;
166
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 dvi-transmitter@39 {
171 compatible = "sil,sii9022-tpi", "sil,sii9022";
172 reg = <0x39>;
173 };
174
175 dvi-transmitter@60 {
176 compatible = "sil,sii9022-cpi", "sil,sii9022";
177 reg = <0x60>;
178 };
179 };
180
181 rtc@170000 {
182 compatible = "arm,pl031", "arm,primecell";
183 reg = <0x170000 0x1000>;
184 interrupts = <4>;
185 };
186
187 compact-flash@1a0000 {
188 compatible = "arm,vexpress-cf", "ata-generic";
189 reg = <0x1a0000 0x100
190 0x1a0100 0xf00>;
191 reg-shift = <2>;
192 };
193
194 clcd@1f0000 {
195 compatible = "arm,pl111", "arm,primecell";
196 reg = <0x1f0000 0x1000>;
197 interrupts = <14>;
198 };
199 };
200 };
201};