Loading...
Note: File does not exist in v3.5.6.
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/clock/qcom,lcc-msm8960.h>
6#include <dt-bindings/reset/qcom,gcc-msm8960.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "Qualcomm APQ8064";
16 compatible = "qcom,apq8064";
17 interrupt-parent = <&intc>;
18
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 smem_region: smem@80000000 {
25 reg = <0x80000000 0x200000>;
26 no-map;
27 };
28
29 wcnss_mem: wcnss@8f000000 {
30 reg = <0x8f000000 0x700000>;
31 no-map;
32 };
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 CPU0: cpu@0 {
40 compatible = "qcom,krait";
41 enable-method = "qcom,kpss-acc-v1";
42 device_type = "cpu";
43 reg = <0>;
44 next-level-cache = <&L2>;
45 qcom,acc = <&acc0>;
46 qcom,saw = <&saw0>;
47 cpu-idle-states = <&CPU_SPC>;
48 };
49
50 CPU1: cpu@1 {
51 compatible = "qcom,krait";
52 enable-method = "qcom,kpss-acc-v1";
53 device_type = "cpu";
54 reg = <1>;
55 next-level-cache = <&L2>;
56 qcom,acc = <&acc1>;
57 qcom,saw = <&saw1>;
58 cpu-idle-states = <&CPU_SPC>;
59 };
60
61 CPU2: cpu@2 {
62 compatible = "qcom,krait";
63 enable-method = "qcom,kpss-acc-v1";
64 device_type = "cpu";
65 reg = <2>;
66 next-level-cache = <&L2>;
67 qcom,acc = <&acc2>;
68 qcom,saw = <&saw2>;
69 cpu-idle-states = <&CPU_SPC>;
70 };
71
72 CPU3: cpu@3 {
73 compatible = "qcom,krait";
74 enable-method = "qcom,kpss-acc-v1";
75 device_type = "cpu";
76 reg = <3>;
77 next-level-cache = <&L2>;
78 qcom,acc = <&acc3>;
79 qcom,saw = <&saw3>;
80 cpu-idle-states = <&CPU_SPC>;
81 };
82
83 L2: l2-cache {
84 compatible = "cache";
85 cache-level = <2>;
86 };
87
88 idle-states {
89 CPU_SPC: spc {
90 compatible = "qcom,idle-state-spc",
91 "arm,idle-state";
92 entry-latency-us = <400>;
93 exit-latency-us = <900>;
94 min-residency-us = <3000>;
95 };
96 };
97 };
98
99 memory@0 {
100 device_type = "memory";
101 reg = <0x0 0x0>;
102 };
103
104 thermal-zones {
105 cpu0-thermal {
106 polling-delay-passive = <250>;
107 polling-delay = <1000>;
108
109 thermal-sensors = <&tsens 7>;
110 coefficients = <1199 0>;
111
112 trips {
113 cpu_alert0: trip0 {
114 temperature = <75000>;
115 hysteresis = <2000>;
116 type = "passive";
117 };
118 cpu_crit0: trip1 {
119 temperature = <110000>;
120 hysteresis = <2000>;
121 type = "critical";
122 };
123 };
124 };
125
126 cpu1-thermal {
127 polling-delay-passive = <250>;
128 polling-delay = <1000>;
129
130 thermal-sensors = <&tsens 8>;
131 coefficients = <1132 0>;
132
133 trips {
134 cpu_alert1: trip0 {
135 temperature = <75000>;
136 hysteresis = <2000>;
137 type = "passive";
138 };
139 cpu_crit1: trip1 {
140 temperature = <110000>;
141 hysteresis = <2000>;
142 type = "critical";
143 };
144 };
145 };
146
147 cpu2-thermal {
148 polling-delay-passive = <250>;
149 polling-delay = <1000>;
150
151 thermal-sensors = <&tsens 9>;
152 coefficients = <1199 0>;
153
154 trips {
155 cpu_alert2: trip0 {
156 temperature = <75000>;
157 hysteresis = <2000>;
158 type = "passive";
159 };
160 cpu_crit2: trip1 {
161 temperature = <110000>;
162 hysteresis = <2000>;
163 type = "critical";
164 };
165 };
166 };
167
168 cpu3-thermal {
169 polling-delay-passive = <250>;
170 polling-delay = <1000>;
171
172 thermal-sensors = <&tsens 10>;
173 coefficients = <1132 0>;
174
175 trips {
176 cpu_alert3: trip0 {
177 temperature = <75000>;
178 hysteresis = <2000>;
179 type = "passive";
180 };
181 cpu_crit3: trip1 {
182 temperature = <110000>;
183 hysteresis = <2000>;
184 type = "critical";
185 };
186 };
187 };
188 };
189
190 cpu-pmu {
191 compatible = "qcom,krait-pmu";
192 interrupts = <1 10 0x304>;
193 };
194
195 clocks {
196 cxo_board: cxo_board {
197 compatible = "fixed-clock";
198 #clock-cells = <0>;
199 clock-frequency = <19200000>;
200 };
201
202 pxo_board: pxo_board {
203 compatible = "fixed-clock";
204 #clock-cells = <0>;
205 clock-frequency = <27000000>;
206 };
207
208 sleep_clk: sleep_clk {
209 compatible = "fixed-clock";
210 #clock-cells = <0>;
211 clock-frequency = <32768>;
212 };
213 };
214
215 sfpb_mutex: hwmutex {
216 compatible = "qcom,sfpb-mutex";
217 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
218 #hwlock-cells = <1>;
219 };
220
221 smem {
222 compatible = "qcom,smem";
223 memory-region = <&smem_region>;
224
225 hwlocks = <&sfpb_mutex 3>;
226 };
227
228 smd {
229 compatible = "qcom,smd";
230
231 modem-edge {
232 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
233
234 qcom,ipc = <&l2cc 8 3>;
235 qcom,smd-edge = <0>;
236
237 status = "disabled";
238 };
239
240 q6-edge {
241 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
242
243 qcom,ipc = <&l2cc 8 15>;
244 qcom,smd-edge = <1>;
245
246 status = "disabled";
247 };
248
249 dsps-edge {
250 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
251
252 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
253 qcom,smd-edge = <3>;
254
255 status = "disabled";
256 };
257
258 riva-edge {
259 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
260
261 qcom,ipc = <&l2cc 8 25>;
262 qcom,smd-edge = <6>;
263
264 status = "disabled";
265 };
266 };
267
268 smsm {
269 compatible = "qcom,smsm";
270
271 #address-cells = <1>;
272 #size-cells = <0>;
273
274 qcom,ipc-1 = <&l2cc 8 4>;
275 qcom,ipc-2 = <&l2cc 8 14>;
276 qcom,ipc-3 = <&l2cc 8 23>;
277 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
278
279 apps_smsm: apps@0 {
280 reg = <0>;
281 #qcom,smem-state-cells = <1>;
282 };
283
284 modem_smsm: modem@1 {
285 reg = <1>;
286 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
287
288 interrupt-controller;
289 #interrupt-cells = <2>;
290 };
291
292 q6_smsm: q6@2 {
293 reg = <2>;
294 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
295
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 };
299
300 wcnss_smsm: wcnss@3 {
301 reg = <3>;
302 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
303
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
307
308 dsps_smsm: dsps@4 {
309 reg = <4>;
310 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
311
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 };
315 };
316
317 firmware {
318 scm {
319 compatible = "qcom,scm-apq8064", "qcom,scm";
320
321 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
322 clock-names = "core";
323 };
324 };
325
326
327 /*
328 * These channels from the ADC are simply hardware monitors.
329 * That is why the ADC is referred to as "HKADC" - HouseKeeping
330 * ADC.
331 */
332 iio-hwmon {
333 compatible = "iio-hwmon";
334 io-channels = <&xoadc 0x00 0x01>, /* Battery */
335 <&xoadc 0x00 0x02>, /* DC in (charger) */
336 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
337 <&xoadc 0x00 0x0b>, /* Die temperature */
338 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
339 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
340 <&xoadc 0x00 0x0e>; /* Charger temperature */
341 };
342
343 soc: soc {
344 #address-cells = <1>;
345 #size-cells = <1>;
346 ranges;
347 compatible = "simple-bus";
348
349 tlmm_pinmux: pinctrl@800000 {
350 compatible = "qcom,apq8064-pinctrl";
351 reg = <0x800000 0x4000>;
352
353 gpio-controller;
354 gpio-ranges = <&tlmm_pinmux 0 0 90>;
355 #gpio-cells = <2>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
359
360 pinctrl-names = "default";
361 pinctrl-0 = <&ps_hold>;
362 };
363
364 sfpb_wrapper_mutex: syscon@1200000 {
365 compatible = "syscon";
366 reg = <0x01200000 0x8000>;
367 };
368
369 intc: interrupt-controller@2000000 {
370 compatible = "qcom,msm-qgic2";
371 interrupt-controller;
372 #interrupt-cells = <3>;
373 reg = <0x02000000 0x1000>,
374 <0x02002000 0x1000>;
375 };
376
377 timer@200a000 {
378 compatible = "qcom,kpss-timer",
379 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
380 interrupts = <1 1 0x301>,
381 <1 2 0x301>,
382 <1 3 0x301>;
383 reg = <0x0200a000 0x100>;
384 clock-frequency = <27000000>,
385 <32768>;
386 cpu-offset = <0x80000>;
387 };
388
389 acc0: clock-controller@2088000 {
390 compatible = "qcom,kpss-acc-v1";
391 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
392 };
393
394 acc1: clock-controller@2098000 {
395 compatible = "qcom,kpss-acc-v1";
396 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
397 };
398
399 acc2: clock-controller@20a8000 {
400 compatible = "qcom,kpss-acc-v1";
401 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
402 };
403
404 acc3: clock-controller@20b8000 {
405 compatible = "qcom,kpss-acc-v1";
406 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
407 };
408
409 saw0: power-controller@2089000 {
410 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
411 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
412 regulator;
413 };
414
415 saw1: power-controller@2099000 {
416 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
417 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
418 regulator;
419 };
420
421 saw2: power-controller@20a9000 {
422 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
423 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
424 regulator;
425 };
426
427 saw3: power-controller@20b9000 {
428 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
429 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
430 regulator;
431 };
432
433 sps_sic_non_secure: sps-sic-non-secure@12100000 {
434 compatible = "syscon";
435 reg = <0x12100000 0x10000>;
436 };
437
438 gsbi1: gsbi@12440000 {
439 status = "disabled";
440 compatible = "qcom,gsbi-v1.0.0";
441 cell-index = <1>;
442 reg = <0x12440000 0x100>;
443 clocks = <&gcc GSBI1_H_CLK>;
444 clock-names = "iface";
445 #address-cells = <1>;
446 #size-cells = <1>;
447 ranges;
448
449 syscon-tcsr = <&tcsr>;
450
451 gsbi1_serial: serial@12450000 {
452 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
453 reg = <0x12450000 0x100>,
454 <0x12400000 0x03>;
455 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
457 clock-names = "core", "iface";
458 status = "disabled";
459 };
460
461 gsbi1_i2c: i2c@12460000 {
462 compatible = "qcom,i2c-qup-v1.1.1";
463 pinctrl-0 = <&i2c1_pins>;
464 pinctrl-1 = <&i2c1_pins_sleep>;
465 pinctrl-names = "default", "sleep";
466 reg = <0x12460000 0x1000>;
467 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
469 clock-names = "core", "iface";
470 #address-cells = <1>;
471 #size-cells = <0>;
472 status = "disabled";
473 };
474
475 };
476
477 gsbi2: gsbi@12480000 {
478 status = "disabled";
479 compatible = "qcom,gsbi-v1.0.0";
480 cell-index = <2>;
481 reg = <0x12480000 0x100>;
482 clocks = <&gcc GSBI2_H_CLK>;
483 clock-names = "iface";
484 #address-cells = <1>;
485 #size-cells = <1>;
486 ranges;
487
488 syscon-tcsr = <&tcsr>;
489
490 gsbi2_i2c: i2c@124a0000 {
491 compatible = "qcom,i2c-qup-v1.1.1";
492 reg = <0x124a0000 0x1000>;
493 pinctrl-0 = <&i2c2_pins>;
494 pinctrl-1 = <&i2c2_pins_sleep>;
495 pinctrl-names = "default", "sleep";
496 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
498 clock-names = "core", "iface";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 status = "disabled";
502 };
503 };
504
505 gsbi3: gsbi@16200000 {
506 status = "disabled";
507 compatible = "qcom,gsbi-v1.0.0";
508 cell-index = <3>;
509 reg = <0x16200000 0x100>;
510 clocks = <&gcc GSBI3_H_CLK>;
511 clock-names = "iface";
512 #address-cells = <1>;
513 #size-cells = <1>;
514 ranges;
515 gsbi3_i2c: i2c@16280000 {
516 compatible = "qcom,i2c-qup-v1.1.1";
517 pinctrl-0 = <&i2c3_pins>;
518 pinctrl-1 = <&i2c3_pins_sleep>;
519 pinctrl-names = "default", "sleep";
520 reg = <0x16280000 0x1000>;
521 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&gcc GSBI3_QUP_CLK>,
523 <&gcc GSBI3_H_CLK>;
524 clock-names = "core", "iface";
525 #address-cells = <1>;
526 #size-cells = <0>;
527 status = "disabled";
528 };
529 };
530
531 gsbi4: gsbi@16300000 {
532 status = "disabled";
533 compatible = "qcom,gsbi-v1.0.0";
534 cell-index = <4>;
535 reg = <0x16300000 0x03>;
536 clocks = <&gcc GSBI4_H_CLK>;
537 clock-names = "iface";
538 #address-cells = <1>;
539 #size-cells = <1>;
540 ranges;
541
542 gsbi4_i2c: i2c@16380000 {
543 compatible = "qcom,i2c-qup-v1.1.1";
544 pinctrl-0 = <&i2c4_pins>;
545 pinctrl-1 = <&i2c4_pins_sleep>;
546 pinctrl-names = "default", "sleep";
547 reg = <0x16380000 0x1000>;
548 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&gcc GSBI4_QUP_CLK>,
550 <&gcc GSBI4_H_CLK>;
551 clock-names = "core", "iface";
552 status = "disabled";
553 };
554 };
555
556 gsbi5: gsbi@1a200000 {
557 status = "disabled";
558 compatible = "qcom,gsbi-v1.0.0";
559 cell-index = <5>;
560 reg = <0x1a200000 0x03>;
561 clocks = <&gcc GSBI5_H_CLK>;
562 clock-names = "iface";
563 #address-cells = <1>;
564 #size-cells = <1>;
565 ranges;
566
567 gsbi5_serial: serial@1a240000 {
568 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
569 reg = <0x1a240000 0x100>,
570 <0x1a200000 0x03>;
571 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
573 clock-names = "core", "iface";
574 status = "disabled";
575 };
576
577 gsbi5_spi: spi@1a280000 {
578 compatible = "qcom,spi-qup-v1.1.1";
579 reg = <0x1a280000 0x1000>;
580 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
581 pinctrl-0 = <&spi5_default>;
582 pinctrl-1 = <&spi5_sleep>;
583 pinctrl-names = "default", "sleep";
584 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
585 clock-names = "core", "iface";
586 status = "disabled";
587 #address-cells = <1>;
588 #size-cells = <0>;
589 };
590 };
591
592 gsbi6: gsbi@16500000 {
593 status = "disabled";
594 compatible = "qcom,gsbi-v1.0.0";
595 cell-index = <6>;
596 reg = <0x16500000 0x03>;
597 clocks = <&gcc GSBI6_H_CLK>;
598 clock-names = "iface";
599 #address-cells = <1>;
600 #size-cells = <1>;
601 ranges;
602
603 gsbi6_serial: serial@16540000 {
604 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
605 reg = <0x16540000 0x100>,
606 <0x16500000 0x03>;
607 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
609 clock-names = "core", "iface";
610 status = "disabled";
611 };
612
613 gsbi6_i2c: i2c@16580000 {
614 compatible = "qcom,i2c-qup-v1.1.1";
615 pinctrl-0 = <&i2c6_pins>;
616 pinctrl-1 = <&i2c6_pins_sleep>;
617 pinctrl-names = "default", "sleep";
618 reg = <0x16580000 0x1000>;
619 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&gcc GSBI6_QUP_CLK>,
621 <&gcc GSBI6_H_CLK>;
622 clock-names = "core", "iface";
623 status = "disabled";
624 };
625 };
626
627 gsbi7: gsbi@16600000 {
628 status = "disabled";
629 compatible = "qcom,gsbi-v1.0.0";
630 cell-index = <7>;
631 reg = <0x16600000 0x100>;
632 clocks = <&gcc GSBI7_H_CLK>;
633 clock-names = "iface";
634 #address-cells = <1>;
635 #size-cells = <1>;
636 ranges;
637 syscon-tcsr = <&tcsr>;
638
639 gsbi7_serial: serial@16640000 {
640 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
641 reg = <0x16640000 0x1000>,
642 <0x16600000 0x1000>;
643 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
645 clock-names = "core", "iface";
646 status = "disabled";
647 };
648
649 gsbi7_i2c: i2c@16680000 {
650 compatible = "qcom,i2c-qup-v1.1.1";
651 pinctrl-0 = <&i2c7_pins>;
652 pinctrl-1 = <&i2c7_pins_sleep>;
653 pinctrl-names = "default", "sleep";
654 reg = <0x16680000 0x1000>;
655 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&gcc GSBI7_QUP_CLK>,
657 <&gcc GSBI7_H_CLK>;
658 clock-names = "core", "iface";
659 status = "disabled";
660 };
661 };
662
663 rng@1a500000 {
664 compatible = "qcom,prng";
665 reg = <0x1a500000 0x200>;
666 clocks = <&gcc PRNG_CLK>;
667 clock-names = "core";
668 };
669
670 ssbi@c00000 {
671 compatible = "qcom,ssbi";
672 reg = <0x00c00000 0x1000>;
673 qcom,controller-type = "pmic-arbiter";
674
675 pm8821: pmic {
676 compatible = "qcom,pm8821";
677 interrupt-parent = <&tlmm_pinmux>;
678 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
679 #interrupt-cells = <2>;
680 interrupt-controller;
681 #address-cells = <1>;
682 #size-cells = <0>;
683
684 pm8821_mpps: mpps@50 {
685 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
686 reg = <0x50>;
687 interrupt-controller;
688 #interrupt-cells = <2>;
689 gpio-controller;
690 #gpio-cells = <2>;
691 gpio-ranges = <&pm8821_mpps 0 0 4>;
692 };
693 };
694 };
695
696 ssbi@500000 {
697 compatible = "qcom,ssbi";
698 reg = <0x00500000 0x1000>;
699 qcom,controller-type = "pmic-arbiter";
700
701 pmicintc: pmic {
702 compatible = "qcom,pm8921";
703 interrupt-parent = <&tlmm_pinmux>;
704 interrupts = <74 8>;
705 #interrupt-cells = <2>;
706 interrupt-controller;
707 #address-cells = <1>;
708 #size-cells = <0>;
709
710 pm8921_gpio: gpio@150 {
711
712 compatible = "qcom,pm8921-gpio",
713 "qcom,ssbi-gpio";
714 reg = <0x150>;
715 interrupt-controller;
716 #interrupt-cells = <2>;
717 gpio-controller;
718 gpio-ranges = <&pm8921_gpio 0 0 44>;
719 #gpio-cells = <2>;
720
721 };
722
723 pm8921_mpps: mpps@50 {
724 compatible = "qcom,pm8921-mpp",
725 "qcom,ssbi-mpp";
726 reg = <0x50>;
727 gpio-controller;
728 #gpio-cells = <2>;
729 gpio-ranges = <&pm8921_mpps 0 0 12>;
730 interrupt-controller;
731 #interrupt-cells = <2>;
732 };
733
734 rtc@11d {
735 compatible = "qcom,pm8921-rtc";
736 interrupt-parent = <&pmicintc>;
737 interrupts = <39 1>;
738 reg = <0x11d>;
739 allow-set-time;
740 };
741
742 pwrkey@1c {
743 compatible = "qcom,pm8921-pwrkey";
744 reg = <0x1c>;
745 interrupt-parent = <&pmicintc>;
746 interrupts = <50 1>, <51 1>;
747 debounce = <15625>;
748 pull-up;
749 };
750
751 xoadc: xoadc@197 {
752 compatible = "qcom,pm8921-adc";
753 reg = <197>;
754 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
755 #address-cells = <2>;
756 #size-cells = <0>;
757 #io-channel-cells = <2>;
758
759 vcoin: adc-channel@0 {
760 reg = <0x00 0x00>;
761 };
762 vbat: adc-channel@1 {
763 reg = <0x00 0x01>;
764 };
765 dcin: adc-channel@2 {
766 reg = <0x00 0x02>;
767 };
768 vph_pwr: adc-channel@4 {
769 reg = <0x00 0x04>;
770 };
771 batt_therm: adc-channel@8 {
772 reg = <0x00 0x08>;
773 };
774 batt_id: adc-channel@9 {
775 reg = <0x00 0x09>;
776 };
777 usb_vbus: adc-channel@a {
778 reg = <0x00 0x0a>;
779 };
780 die_temp: adc-channel@b {
781 reg = <0x00 0x0b>;
782 };
783 ref_625mv: adc-channel@c {
784 reg = <0x00 0x0c>;
785 };
786 ref_1250mv: adc-channel@d {
787 reg = <0x00 0x0d>;
788 };
789 chg_temp: adc-channel@e {
790 reg = <0x00 0x0e>;
791 };
792 ref_muxoff: adc-channel@f {
793 reg = <0x00 0x0f>;
794 };
795 };
796 };
797 };
798
799 qfprom: qfprom@700000 {
800 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
801 reg = <0x00700000 0x1000>;
802 #address-cells = <1>;
803 #size-cells = <1>;
804 ranges;
805 tsens_calib: calib@404 {
806 reg = <0x404 0x10>;
807 };
808 tsens_backup: backup_calib@414 {
809 reg = <0x414 0x10>;
810 };
811 };
812
813 gcc: clock-controller@900000 {
814 compatible = "qcom,gcc-apq8064", "syscon";
815 reg = <0x00900000 0x4000>;
816 #clock-cells = <1>;
817 #power-domain-cells = <1>;
818 #reset-cells = <1>;
819 clocks = <&cxo_board>,
820 <&pxo_board>,
821 <&lcc PLL4>;
822 clock-names = "cxo", "pxo", "pll4";
823
824 tsens: thermal-sensor {
825 compatible = "qcom,msm8960-tsens";
826
827 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
828 nvmem-cell-names = "calib", "calib_backup";
829 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
830 interrupt-names = "uplow";
831
832 #qcom,sensors = <11>;
833 #thermal-sensor-cells = <1>;
834 };
835 };
836
837 lcc: clock-controller@28000000 {
838 compatible = "qcom,lcc-apq8064";
839 reg = <0x28000000 0x1000>;
840 #clock-cells = <1>;
841 #reset-cells = <1>;
842 clocks = <&pxo_board>,
843 <&gcc PLL4_VOTE>,
844 <0>,
845 <0>, <0>,
846 <0>, <0>,
847 <0>;
848 clock-names = "pxo",
849 "pll4_vote",
850 "mi2s_codec_clk",
851 "codec_i2s_mic_codec_clk",
852 "spare_i2s_mic_codec_clk",
853 "codec_i2s_spkr_codec_clk",
854 "spare_i2s_spkr_codec_clk",
855 "pcm_codec_clk";
856 };
857
858 mmcc: clock-controller@4000000 {
859 compatible = "qcom,mmcc-apq8064";
860 reg = <0x4000000 0x1000>;
861 #clock-cells = <1>;
862 #power-domain-cells = <1>;
863 #reset-cells = <1>;
864 clocks = <&pxo_board>,
865 <&gcc PLL3>,
866 <&gcc PLL8_VOTE>,
867 <&dsi0_phy 1>,
868 <&dsi0_phy 0>,
869 <0>,
870 <0>,
871 <0>;
872 clock-names = "pxo",
873 "pll3",
874 "pll8_vote",
875 "dsi1pll",
876 "dsi1pllbyte",
877 "dsi2pll",
878 "dsi2pllbyte",
879 "hdmipll";
880 };
881
882 l2cc: clock-controller@2011000 {
883 compatible = "qcom,kpss-gcc", "syscon";
884 reg = <0x2011000 0x1000>;
885 };
886
887 rpm: rpm@108000 {
888 compatible = "qcom,rpm-apq8064";
889 reg = <0x108000 0x1000>;
890 qcom,ipc = <&l2cc 0x8 2>;
891
892 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
893 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
894 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
895 interrupt-names = "ack", "err", "wakeup";
896
897 rpmcc: clock-controller {
898 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
899 #clock-cells = <1>;
900 clocks = <&pxo_board>, <&cxo_board>;
901 clock-names = "pxo", "cxo";
902 };
903
904 regulators {
905 compatible = "qcom,rpm-pm8921-regulators";
906
907 pm8921_s1: s1 {};
908 pm8921_s2: s2 {};
909 pm8921_s3: s3 {};
910 pm8921_s4: s4 {};
911 pm8921_s7: s7 {};
912 pm8921_s8: s8 {};
913
914 pm8921_l1: l1 {};
915 pm8921_l2: l2 {};
916 pm8921_l3: l3 {};
917 pm8921_l4: l4 {};
918 pm8921_l5: l5 {};
919 pm8921_l6: l6 {};
920 pm8921_l7: l7 {};
921 pm8921_l8: l8 {};
922 pm8921_l9: l9 {};
923 pm8921_l10: l10 {};
924 pm8921_l11: l11 {};
925 pm8921_l12: l12 {};
926 pm8921_l14: l14 {};
927 pm8921_l15: l15 {};
928 pm8921_l16: l16 {};
929 pm8921_l17: l17 {};
930 pm8921_l18: l18 {};
931 pm8921_l21: l21 {};
932 pm8921_l22: l22 {};
933 pm8921_l23: l23 {};
934 pm8921_l24: l24 {};
935 pm8921_l25: l25 {};
936 pm8921_l26: l26 {};
937 pm8921_l27: l27 {};
938 pm8921_l28: l28 {};
939 pm8921_l29: l29 {};
940
941 pm8921_lvs1: lvs1 {};
942 pm8921_lvs2: lvs2 {};
943 pm8921_lvs3: lvs3 {};
944 pm8921_lvs4: lvs4 {};
945 pm8921_lvs5: lvs5 {};
946 pm8921_lvs6: lvs6 {};
947 pm8921_lvs7: lvs7 {};
948
949 pm8921_usb_switch: usb-switch {};
950
951 pm8921_hdmi_switch: hdmi-switch {
952 bias-pull-down;
953 };
954
955 pm8921_ncp: ncp {};
956 };
957 };
958
959 usb1: usb@12500000 {
960 compatible = "qcom,ci-hdrc";
961 reg = <0x12500000 0x200>,
962 <0x12500200 0x200>;
963 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
965 clock-names = "core", "iface";
966 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
967 assigned-clock-rates = <60000000>;
968 resets = <&gcc USB_HS1_RESET>;
969 reset-names = "core";
970 phy_type = "ulpi";
971 ahb-burst-config = <0>;
972 phys = <&usb_hs1_phy>;
973 phy-names = "usb-phy";
974 status = "disabled";
975 #reset-cells = <1>;
976
977 ulpi {
978 usb_hs1_phy: phy {
979 compatible = "qcom,usb-hs-phy-apq8064",
980 "qcom,usb-hs-phy";
981 clocks = <&sleep_clk>, <&cxo_board>;
982 clock-names = "sleep", "ref";
983 resets = <&usb1 0>;
984 reset-names = "por";
985 #phy-cells = <0>;
986 };
987 };
988 };
989
990 usb3: usb@12520000 {
991 compatible = "qcom,ci-hdrc";
992 reg = <0x12520000 0x200>,
993 <0x12520200 0x200>;
994 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
996 clock-names = "core", "iface";
997 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
998 assigned-clock-rates = <60000000>;
999 resets = <&gcc USB_HS3_RESET>;
1000 reset-names = "core";
1001 phy_type = "ulpi";
1002 ahb-burst-config = <0>;
1003 phys = <&usb_hs3_phy>;
1004 phy-names = "usb-phy";
1005 status = "disabled";
1006 #reset-cells = <1>;
1007
1008 ulpi {
1009 usb_hs3_phy: phy {
1010 compatible = "qcom,usb-hs-phy-apq8064",
1011 "qcom,usb-hs-phy";
1012 #phy-cells = <0>;
1013 clocks = <&sleep_clk>, <&cxo_board>;
1014 clock-names = "sleep", "ref";
1015 resets = <&usb3 0>;
1016 reset-names = "por";
1017 };
1018 };
1019 };
1020
1021 usb4: usb@12530000 {
1022 compatible = "qcom,ci-hdrc";
1023 reg = <0x12530000 0x200>,
1024 <0x12530200 0x200>;
1025 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1027 clock-names = "core", "iface";
1028 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1029 assigned-clock-rates = <60000000>;
1030 resets = <&gcc USB_HS4_RESET>;
1031 reset-names = "core";
1032 phy_type = "ulpi";
1033 ahb-burst-config = <0>;
1034 phys = <&usb_hs4_phy>;
1035 phy-names = "usb-phy";
1036 status = "disabled";
1037 #reset-cells = <1>;
1038
1039 ulpi {
1040 usb_hs4_phy: phy {
1041 compatible = "qcom,usb-hs-phy-apq8064",
1042 "qcom,usb-hs-phy";
1043 #phy-cells = <0>;
1044 clocks = <&sleep_clk>, <&cxo_board>;
1045 clock-names = "sleep", "ref";
1046 resets = <&usb4 0>;
1047 reset-names = "por";
1048 };
1049 };
1050 };
1051
1052 sata_phy0: phy@1b400000 {
1053 compatible = "qcom,apq8064-sata-phy";
1054 status = "disabled";
1055 reg = <0x1b400000 0x200>;
1056 reg-names = "phy_mem";
1057 clocks = <&gcc SATA_PHY_CFG_CLK>;
1058 clock-names = "cfg";
1059 #phy-cells = <0>;
1060 };
1061
1062 sata0: sata@29000000 {
1063 compatible = "qcom,apq8064-ahci", "generic-ahci";
1064 status = "disabled";
1065 reg = <0x29000000 0x180>;
1066 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1067
1068 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1069 <&gcc SATA_H_CLK>,
1070 <&gcc SATA_A_CLK>,
1071 <&gcc SATA_RXOOB_CLK>,
1072 <&gcc SATA_PMALIVE_CLK>;
1073 clock-names = "slave_iface",
1074 "iface",
1075 "bus",
1076 "rxoob",
1077 "core_pmalive";
1078
1079 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1080 <&gcc SATA_PMALIVE_CLK>;
1081 assigned-clock-rates = <100000000>, <100000000>;
1082
1083 phys = <&sata_phy0>;
1084 phy-names = "sata-phy";
1085 ports-implemented = <0x1>;
1086 };
1087
1088 sdcc3: mmc@12180000 {
1089 compatible = "arm,pl18x", "arm,primecell";
1090 arm,primecell-periphid = <0x00051180>;
1091 status = "disabled";
1092 reg = <0x12180000 0x2000>;
1093 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1095 clock-names = "mclk", "apb_pclk";
1096 bus-width = <4>;
1097 cap-sd-highspeed;
1098 cap-mmc-highspeed;
1099 max-frequency = <192000000>;
1100 no-1-8-v;
1101 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1102 dma-names = "tx", "rx";
1103 };
1104
1105 sdcc3bam: dma-controller@12182000{
1106 compatible = "qcom,bam-v1.3.0";
1107 reg = <0x12182000 0x8000>;
1108 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&gcc SDC3_H_CLK>;
1110 clock-names = "bam_clk";
1111 #dma-cells = <1>;
1112 qcom,ee = <0>;
1113 };
1114
1115 sdcc4: mmc@121c0000 {
1116 compatible = "arm,pl18x", "arm,primecell";
1117 arm,primecell-periphid = <0x00051180>;
1118 status = "disabled";
1119 reg = <0x121c0000 0x2000>;
1120 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1122 clock-names = "mclk", "apb_pclk";
1123 bus-width = <4>;
1124 cap-sd-highspeed;
1125 cap-mmc-highspeed;
1126 max-frequency = <48000000>;
1127 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1128 dma-names = "tx", "rx";
1129 pinctrl-names = "default";
1130 pinctrl-0 = <&sdc4_gpios>;
1131 };
1132
1133 sdcc4bam: dma-controller@121c2000{
1134 compatible = "qcom,bam-v1.3.0";
1135 reg = <0x121c2000 0x8000>;
1136 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1137 clocks = <&gcc SDC4_H_CLK>;
1138 clock-names = "bam_clk";
1139 #dma-cells = <1>;
1140 qcom,ee = <0>;
1141 };
1142
1143 sdcc1: mmc@12400000 {
1144 status = "disabled";
1145 compatible = "arm,pl18x", "arm,primecell";
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&sdcc1_pins>;
1148 arm,primecell-periphid = <0x00051180>;
1149 reg = <0x12400000 0x2000>;
1150 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1151 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1152 clock-names = "mclk", "apb_pclk";
1153 bus-width = <8>;
1154 max-frequency = <96000000>;
1155 non-removable;
1156 cap-sd-highspeed;
1157 cap-mmc-highspeed;
1158 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1159 dma-names = "tx", "rx";
1160 };
1161
1162 sdcc1bam: dma-controller@12402000{
1163 compatible = "qcom,bam-v1.3.0";
1164 reg = <0x12402000 0x8000>;
1165 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&gcc SDC1_H_CLK>;
1167 clock-names = "bam_clk";
1168 #dma-cells = <1>;
1169 qcom,ee = <0>;
1170 };
1171
1172 tcsr: syscon@1a400000 {
1173 compatible = "qcom,tcsr-apq8064", "syscon";
1174 reg = <0x1a400000 0x100>;
1175 };
1176
1177 gpu: adreno-3xx@4300000 {
1178 compatible = "qcom,adreno-320.2", "qcom,adreno";
1179 reg = <0x04300000 0x20000>;
1180 reg-names = "kgsl_3d0_reg_memory";
1181 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1182 interrupt-names = "kgsl_3d0_irq";
1183 clock-names =
1184 "core",
1185 "iface",
1186 "mem",
1187 "mem_iface";
1188 clocks =
1189 <&mmcc GFX3D_CLK>,
1190 <&mmcc GFX3D_AHB_CLK>,
1191 <&mmcc GFX3D_AXI_CLK>,
1192 <&mmcc MMSS_IMEM_AHB_CLK>;
1193
1194 iommus = <&gfx3d 0
1195 &gfx3d 1
1196 &gfx3d 2
1197 &gfx3d 3
1198 &gfx3d 4
1199 &gfx3d 5
1200 &gfx3d 6
1201 &gfx3d 7
1202 &gfx3d 8
1203 &gfx3d 9
1204 &gfx3d 10
1205 &gfx3d 11
1206 &gfx3d 12
1207 &gfx3d 13
1208 &gfx3d 14
1209 &gfx3d 15
1210 &gfx3d 16
1211 &gfx3d 17
1212 &gfx3d 18
1213 &gfx3d 19
1214 &gfx3d 20
1215 &gfx3d 21
1216 &gfx3d 22
1217 &gfx3d 23
1218 &gfx3d 24
1219 &gfx3d 25
1220 &gfx3d 26
1221 &gfx3d 27
1222 &gfx3d 28
1223 &gfx3d 29
1224 &gfx3d 30
1225 &gfx3d 31
1226 &gfx3d1 0
1227 &gfx3d1 1
1228 &gfx3d1 2
1229 &gfx3d1 3
1230 &gfx3d1 4
1231 &gfx3d1 5
1232 &gfx3d1 6
1233 &gfx3d1 7
1234 &gfx3d1 8
1235 &gfx3d1 9
1236 &gfx3d1 10
1237 &gfx3d1 11
1238 &gfx3d1 12
1239 &gfx3d1 13
1240 &gfx3d1 14
1241 &gfx3d1 15
1242 &gfx3d1 16
1243 &gfx3d1 17
1244 &gfx3d1 18
1245 &gfx3d1 19
1246 &gfx3d1 20
1247 &gfx3d1 21
1248 &gfx3d1 22
1249 &gfx3d1 23
1250 &gfx3d1 24
1251 &gfx3d1 25
1252 &gfx3d1 26
1253 &gfx3d1 27
1254 &gfx3d1 28
1255 &gfx3d1 29
1256 &gfx3d1 30
1257 &gfx3d1 31>;
1258
1259 operating-points-v2 = <&gpu_opp_table>;
1260
1261 gpu_opp_table: opp-table {
1262 compatible = "operating-points-v2";
1263
1264 opp-320000000 {
1265 opp-hz = /bits/ 64 <450000000>;
1266 };
1267
1268 opp-27000000 {
1269 opp-hz = /bits/ 64 <27000000>;
1270 };
1271 };
1272 };
1273
1274 mmss_sfpb: syscon@5700000 {
1275 compatible = "syscon";
1276 reg = <0x5700000 0x70>;
1277 };
1278
1279 dsi0: dsi@4700000 {
1280 compatible = "qcom,mdss-dsi-ctrl";
1281 label = "MDSS DSI CTRL->0";
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1285 reg = <0x04700000 0x200>;
1286 reg-names = "dsi_ctrl";
1287
1288 clocks = <&mmcc DSI_M_AHB_CLK>,
1289 <&mmcc DSI_S_AHB_CLK>,
1290 <&mmcc AMP_AHB_CLK>,
1291 <&mmcc DSI_CLK>,
1292 <&mmcc DSI1_BYTE_CLK>,
1293 <&mmcc DSI_PIXEL_CLK>,
1294 <&mmcc DSI1_ESC_CLK>;
1295 clock-names = "iface", "bus", "core_mmss",
1296 "src", "byte", "pixel",
1297 "core";
1298
1299 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1300 <&mmcc DSI1_ESC_SRC>,
1301 <&mmcc DSI_SRC>,
1302 <&mmcc DSI_PIXEL_SRC>;
1303 assigned-clock-parents = <&dsi0_phy 0>,
1304 <&dsi0_phy 0>,
1305 <&dsi0_phy 1>,
1306 <&dsi0_phy 1>;
1307 syscon-sfpb = <&mmss_sfpb>;
1308 phys = <&dsi0_phy>;
1309 status = "disabled";
1310
1311 ports {
1312 #address-cells = <1>;
1313 #size-cells = <0>;
1314
1315 port@0 {
1316 reg = <0>;
1317 dsi0_in: endpoint {
1318 };
1319 };
1320
1321 port@1 {
1322 reg = <1>;
1323 dsi0_out: endpoint {
1324 };
1325 };
1326 };
1327 };
1328
1329
1330 dsi0_phy: phy@4700200 {
1331 compatible = "qcom,dsi-phy-28nm-8960";
1332 #clock-cells = <1>;
1333 #phy-cells = <0>;
1334
1335 reg = <0x04700200 0x100>,
1336 <0x04700300 0x200>,
1337 <0x04700500 0x5c>;
1338 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1339 clock-names = "iface", "ref";
1340 clocks = <&mmcc DSI_M_AHB_CLK>,
1341 <&pxo_board>;
1342 status = "disabled";
1343 };
1344
1345
1346 mdp_port0: iommu@7500000 {
1347 compatible = "qcom,apq8064-iommu";
1348 #iommu-cells = <1>;
1349 clock-names =
1350 "smmu_pclk",
1351 "iommu_clk";
1352 clocks =
1353 <&mmcc SMMU_AHB_CLK>,
1354 <&mmcc MDP_AXI_CLK>;
1355 reg = <0x07500000 0x100000>;
1356 interrupts =
1357 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1359 qcom,ncb = <2>;
1360 };
1361
1362 mdp_port1: iommu@7600000 {
1363 compatible = "qcom,apq8064-iommu";
1364 #iommu-cells = <1>;
1365 clock-names =
1366 "smmu_pclk",
1367 "iommu_clk";
1368 clocks =
1369 <&mmcc SMMU_AHB_CLK>,
1370 <&mmcc MDP_AXI_CLK>;
1371 reg = <0x07600000 0x100000>;
1372 interrupts =
1373 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1375 qcom,ncb = <2>;
1376 };
1377
1378 gfx3d: iommu@7c00000 {
1379 compatible = "qcom,apq8064-iommu";
1380 #iommu-cells = <1>;
1381 clock-names =
1382 "smmu_pclk",
1383 "iommu_clk";
1384 clocks =
1385 <&mmcc SMMU_AHB_CLK>,
1386 <&mmcc GFX3D_AXI_CLK>;
1387 reg = <0x07c00000 0x100000>;
1388 interrupts =
1389 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1391 qcom,ncb = <3>;
1392 };
1393
1394 gfx3d1: iommu@7d00000 {
1395 compatible = "qcom,apq8064-iommu";
1396 #iommu-cells = <1>;
1397 clock-names =
1398 "smmu_pclk",
1399 "iommu_clk";
1400 clocks =
1401 <&mmcc SMMU_AHB_CLK>,
1402 <&mmcc GFX3D_AXI_CLK>;
1403 reg = <0x07d00000 0x100000>;
1404 interrupts =
1405 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1407 qcom,ncb = <3>;
1408 };
1409
1410 pcie: pci@1b500000 {
1411 compatible = "qcom,pcie-apq8064";
1412 reg = <0x1b500000 0x1000>,
1413 <0x1b502000 0x80>,
1414 <0x1b600000 0x100>,
1415 <0x0ff00000 0x100000>;
1416 reg-names = "dbi", "elbi", "parf", "config";
1417 device_type = "pci";
1418 linux,pci-domain = <0>;
1419 bus-range = <0x00 0xff>;
1420 num-lanes = <1>;
1421 #address-cells = <3>;
1422 #size-cells = <2>;
1423 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */
1424 <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */
1425 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1426 interrupt-names = "msi";
1427 #interrupt-cells = <1>;
1428 interrupt-map-mask = <0 0 0 0x7>;
1429 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1430 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1431 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1432 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1433 clocks = <&gcc PCIE_A_CLK>,
1434 <&gcc PCIE_H_CLK>,
1435 <&gcc PCIE_PHY_REF_CLK>;
1436 clock-names = "core", "iface", "phy";
1437 resets = <&gcc PCIE_ACLK_RESET>,
1438 <&gcc PCIE_HCLK_RESET>,
1439 <&gcc PCIE_POR_RESET>,
1440 <&gcc PCIE_PCI_RESET>,
1441 <&gcc PCIE_PHY_RESET>;
1442 reset-names = "axi", "ahb", "por", "pci", "phy";
1443 status = "disabled";
1444 };
1445
1446 hdmi: hdmi-tx@4a00000 {
1447 compatible = "qcom,hdmi-tx-8960";
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&hdmi_pinctrl>;
1450 reg = <0x04a00000 0x2f0>;
1451 reg-names = "core_physical";
1452 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1453 clocks = <&mmcc HDMI_APP_CLK>,
1454 <&mmcc HDMI_M_AHB_CLK>,
1455 <&mmcc HDMI_S_AHB_CLK>;
1456 clock-names = "core",
1457 "master_iface",
1458 "slave_iface";
1459
1460 phys = <&hdmi_phy>;
1461
1462 status = "disabled";
1463
1464 ports {
1465 #address-cells = <1>;
1466 #size-cells = <0>;
1467
1468 port@0 {
1469 reg = <0>;
1470 hdmi_in: endpoint {
1471 };
1472 };
1473
1474 port@1 {
1475 reg = <1>;
1476 hdmi_out: endpoint {
1477 };
1478 };
1479 };
1480 };
1481
1482 hdmi_phy: phy@4a00400 {
1483 compatible = "qcom,hdmi-phy-8960";
1484 reg = <0x4a00400 0x60>,
1485 <0x4a00500 0x100>;
1486 reg-names = "hdmi_phy",
1487 "hdmi_pll";
1488
1489 clocks = <&mmcc HDMI_S_AHB_CLK>;
1490 clock-names = "slave_iface";
1491 #phy-cells = <0>;
1492
1493 status = "disabled";
1494 };
1495
1496 mdp: mdp@5100000 {
1497 compatible = "qcom,mdp4";
1498 reg = <0x05100000 0xf0000>;
1499 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1500 clocks = <&mmcc MDP_CLK>,
1501 <&mmcc MDP_AHB_CLK>,
1502 <&mmcc MDP_AXI_CLK>,
1503 <&mmcc MDP_LUT_CLK>,
1504 <&mmcc HDMI_TV_CLK>,
1505 <&mmcc MDP_TV_CLK>;
1506 clock-names = "core_clk",
1507 "iface_clk",
1508 "bus_clk",
1509 "lut_clk",
1510 "hdmi_clk",
1511 "tv_clk";
1512
1513 iommus = <&mdp_port0 0
1514 &mdp_port0 2
1515 &mdp_port1 0
1516 &mdp_port1 2>;
1517
1518 ports {
1519 #address-cells = <1>;
1520 #size-cells = <0>;
1521
1522 port@0 {
1523 reg = <0>;
1524 mdp_lvds_out: endpoint {
1525 };
1526 };
1527
1528 port@1 {
1529 reg = <1>;
1530 mdp_dsi1_out: endpoint {
1531 };
1532 };
1533
1534 port@2 {
1535 reg = <2>;
1536 mdp_dsi2_out: endpoint {
1537 };
1538 };
1539
1540 port@3 {
1541 reg = <3>;
1542 mdp_dtv_out: endpoint {
1543 };
1544 };
1545 };
1546 };
1547
1548 riva: riva-pil@3200800 {
1549 compatible = "qcom,riva-pil";
1550
1551 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1552 reg-names = "ccu", "dxe", "pmu";
1553
1554 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1555 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1556 interrupt-names = "wdog", "fatal";
1557
1558 memory-region = <&wcnss_mem>;
1559
1560 vddcx-supply = <&pm8921_s3>;
1561 vddmx-supply = <&pm8921_l24>;
1562 vddpx-supply = <&pm8921_s4>;
1563
1564 status = "disabled";
1565
1566 iris {
1567 compatible = "qcom,wcn3660";
1568
1569 clocks = <&cxo_board>;
1570 clock-names = "xo";
1571
1572 vddxo-supply = <&pm8921_l4>;
1573 vddrfa-supply = <&pm8921_s2>;
1574 vddpa-supply = <&pm8921_l10>;
1575 vdddig-supply = <&pm8921_lvs2>;
1576 };
1577
1578 smd-edge {
1579 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1580
1581 qcom,ipc = <&l2cc 8 25>;
1582 qcom,smd-edge = <6>;
1583
1584 label = "riva";
1585
1586 wcnss {
1587 compatible = "qcom,wcnss";
1588 qcom,smd-channels = "WCNSS_CTRL";
1589
1590 qcom,mmio = <&riva>;
1591
1592 bluetooth {
1593 compatible = "qcom,wcnss-bt";
1594 };
1595
1596 wifi {
1597 compatible = "qcom,wcnss-wlan";
1598
1599 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1600 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1601 interrupt-names = "tx", "rx";
1602
1603 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1604 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1605 };
1606 };
1607 };
1608 };
1609
1610 etb@1a01000 {
1611 compatible = "arm,coresight-etb10", "arm,primecell";
1612 reg = <0x1a01000 0x1000>;
1613
1614 clocks = <&rpmcc RPM_QDSS_CLK>;
1615 clock-names = "apb_pclk";
1616
1617 in-ports {
1618 port {
1619 etb_in: endpoint {
1620 remote-endpoint = <&replicator_out0>;
1621 };
1622 };
1623 };
1624 };
1625
1626 tpiu@1a03000 {
1627 compatible = "arm,coresight-tpiu", "arm,primecell";
1628 reg = <0x1a03000 0x1000>;
1629
1630 clocks = <&rpmcc RPM_QDSS_CLK>;
1631 clock-names = "apb_pclk";
1632
1633 in-ports {
1634 port {
1635 tpiu_in: endpoint {
1636 remote-endpoint = <&replicator_out1>;
1637 };
1638 };
1639 };
1640 };
1641
1642 replicator {
1643 compatible = "arm,coresight-static-replicator";
1644
1645 clocks = <&rpmcc RPM_QDSS_CLK>;
1646 clock-names = "apb_pclk";
1647
1648 out-ports {
1649 #address-cells = <1>;
1650 #size-cells = <0>;
1651
1652 port@0 {
1653 reg = <0>;
1654 replicator_out0: endpoint {
1655 remote-endpoint = <&etb_in>;
1656 };
1657 };
1658 port@1 {
1659 reg = <1>;
1660 replicator_out1: endpoint {
1661 remote-endpoint = <&tpiu_in>;
1662 };
1663 };
1664 };
1665
1666 in-ports {
1667 port {
1668 replicator_in: endpoint {
1669 remote-endpoint = <&funnel_out>;
1670 };
1671 };
1672 };
1673 };
1674
1675 funnel@1a04000 {
1676 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1677 reg = <0x1a04000 0x1000>;
1678
1679 clocks = <&rpmcc RPM_QDSS_CLK>;
1680 clock-names = "apb_pclk";
1681
1682 in-ports {
1683 #address-cells = <1>;
1684 #size-cells = <0>;
1685
1686 /*
1687 * Not described input ports:
1688 * 2 - connected to STM component
1689 * 3 - not-connected
1690 * 6 - not-connected
1691 * 7 - not-connected
1692 */
1693 port@0 {
1694 reg = <0>;
1695 funnel_in0: endpoint {
1696 remote-endpoint = <&etm0_out>;
1697 };
1698 };
1699 port@1 {
1700 reg = <1>;
1701 funnel_in1: endpoint {
1702 remote-endpoint = <&etm1_out>;
1703 };
1704 };
1705 port@4 {
1706 reg = <4>;
1707 funnel_in4: endpoint {
1708 remote-endpoint = <&etm2_out>;
1709 };
1710 };
1711 port@5 {
1712 reg = <5>;
1713 funnel_in5: endpoint {
1714 remote-endpoint = <&etm3_out>;
1715 };
1716 };
1717 };
1718
1719 out-ports {
1720 port {
1721 funnel_out: endpoint {
1722 remote-endpoint = <&replicator_in>;
1723 };
1724 };
1725 };
1726 };
1727
1728 etm@1a1c000 {
1729 compatible = "arm,coresight-etm3x", "arm,primecell";
1730 reg = <0x1a1c000 0x1000>;
1731
1732 clocks = <&rpmcc RPM_QDSS_CLK>;
1733 clock-names = "apb_pclk";
1734
1735 cpu = <&CPU0>;
1736
1737 out-ports {
1738 port {
1739 etm0_out: endpoint {
1740 remote-endpoint = <&funnel_in0>;
1741 };
1742 };
1743 };
1744 };
1745
1746 etm@1a1d000 {
1747 compatible = "arm,coresight-etm3x", "arm,primecell";
1748 reg = <0x1a1d000 0x1000>;
1749
1750 clocks = <&rpmcc RPM_QDSS_CLK>;
1751 clock-names = "apb_pclk";
1752
1753 cpu = <&CPU1>;
1754
1755 out-ports {
1756 port {
1757 etm1_out: endpoint {
1758 remote-endpoint = <&funnel_in1>;
1759 };
1760 };
1761 };
1762 };
1763
1764 etm@1a1e000 {
1765 compatible = "arm,coresight-etm3x", "arm,primecell";
1766 reg = <0x1a1e000 0x1000>;
1767
1768 clocks = <&rpmcc RPM_QDSS_CLK>;
1769 clock-names = "apb_pclk";
1770
1771 cpu = <&CPU2>;
1772
1773 out-ports {
1774 port {
1775 etm2_out: endpoint {
1776 remote-endpoint = <&funnel_in4>;
1777 };
1778 };
1779 };
1780 };
1781
1782 etm@1a1f000 {
1783 compatible = "arm,coresight-etm3x", "arm,primecell";
1784 reg = <0x1a1f000 0x1000>;
1785
1786 clocks = <&rpmcc RPM_QDSS_CLK>;
1787 clock-names = "apb_pclk";
1788
1789 cpu = <&CPU3>;
1790
1791 out-ports {
1792 port {
1793 etm3_out: endpoint {
1794 remote-endpoint = <&funnel_in5>;
1795 };
1796 };
1797 };
1798 };
1799 };
1800};
1801#include "qcom-apq8064-pins.dtsi"