1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2017 exceet electronics GmbH
  4 * Copyright (C) 2018 Kontron Electronics GmbH
  5 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
  6 */
  7
  8#include <dt-bindings/gpio/gpio.h>
  9
 10/ {
 11	chosen {
 12		stdout-path = &uart4;
 13	};
 14
 15	memory@80000000 {
 16		reg = <0x80000000 0x10000000>;
 17		device_type = "memory";
 18	};
 19};
 20
 21&ecspi2 {
 22	cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 23	pinctrl-names = "default";
 24	pinctrl-0 = <&pinctrl_ecspi2>;
 25	status = "okay";
 26
 27	flash@0 {
 28		compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
 29		spi-max-frequency = <50000000>;
 30		reg = <0>;
 31	};
 32};
 33
 34&fec1 {
 35	pinctrl-names = "default";
 36	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
 37	phy-mode = "rmii";
 38	phy-handle = <&ethphy1>;
 39	status = "okay";
 40
 41	mdio {
 42		#address-cells = <1>;
 43		#size-cells = <0>;
 44
 45		ethphy1: ethernet-phy@1 {
 46			reg = <1>;
 47			micrel,led-mode = <0>;
 48			clocks = <&clks IMX6UL_CLK_ENET_REF>;
 49			clock-names = "rmii-ref";
 50		};
 51	};
 52};
 53
 54&fec2 {
 55	phy-mode = "rmii";
 56	status = "disabled";
 57};
 58
 59&qspi {
 60	pinctrl-names = "default";
 61	pinctrl-0 = <&pinctrl_qspi>;
 62	status = "okay";
 63
 64	spi-flash@0 {
 65		#address-cells = <1>;
 66		#size-cells = <1>;
 67		compatible = "spi-nand";
 68		spi-max-frequency = <104000000>;
 69		spi-tx-bus-width = <4>;
 70		spi-rx-bus-width = <4>;
 71		reg = <0>;
 72	};
 73};
 74
 75&wdog1 {
 76	pinctrl-names = "default";
 77	pinctrl-0 = <&pinctrl_wdog>;
 78	fsl,ext-reset-output;
 79	status = "okay";
 80};
 81
 82&iomuxc {
 83	pinctrl-names = "default";
 84	pinctrl-0 = <&pinctrl_reset_out>;
 85
 86	pinctrl_ecspi2: ecspi2grp {
 87		fsl,pins = <
 88			MX6UL_PAD_CSI_DATA03__ECSPI2_MISO      0x100b1
 89			MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI      0x100b1
 90			MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK      0x100b1
 91			MX6UL_PAD_CSI_DATA01__GPIO4_IO22       0x100b1
 92		>;
 93	};
 94
 95	pinctrl_enet1: enet1grp {
 96		fsl,pins = <
 97			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 98			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 99			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
100			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
101			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
102			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
103			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
104			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b009
105		>;
106	};
107
108	pinctrl_enet1_mdio: enet1mdiogrp {
109		fsl,pins = <
110			MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
111			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
112		>;
113	};
114
115	pinctrl_qspi: qspigrp {
116		fsl,pins = <
117			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
118			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
119			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
120			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
121			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
122			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
123		>;
124	};
125
126	pinctrl_reset_out: rstoutgrp {
127		fsl,pins = <
128			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x1b0b0
129		>;
130	};
131
132	pinctrl_wdog: wdoggrp {
133		fsl,pins = <
134			MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY    0x18b0
135		>;
136	};
137};