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1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/interrupt-controller/irq.h>
6#include "imx6q-pinfunc.h"
7#include "imx6qdl.dtsi"
8
9/ {
10 aliases {
11 ipu1 = &ipu2;
12 spi4 = &ecspi5;
13 };
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 operating-points = <
25 /* kHz uV */
26 1200000 1275000
27 996000 1250000
28 852000 1250000
29 792000 1175000
30 396000 975000
31 >;
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
34 1200000 1275000
35 996000 1250000
36 852000 1250000
37 792000 1175000
38 396000 1175000
39 >;
40 clock-latency = <61036>; /* two CLK32 periods */
41 #cooling-cells = <2>;
42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
47 clock-names = "arm", "pll2_pfd2_396m", "step",
48 "pll1_sw", "pll1_sys";
49 arm-supply = <®_arm>;
50 pu-supply = <®_pu>;
51 soc-supply = <®_soc>;
52 nvmem-cells = <&cpu_speed_grade>;
53 nvmem-cell-names = "speed_grade";
54 };
55
56 cpu1: cpu@1 {
57 compatible = "arm,cortex-a9";
58 device_type = "cpu";
59 reg = <1>;
60 next-level-cache = <&L2>;
61 operating-points = <
62 /* kHz uV */
63 1200000 1275000
64 996000 1250000
65 852000 1250000
66 792000 1175000
67 396000 975000
68 >;
69 fsl,soc-operating-points = <
70 /* ARM kHz SOC-PU uV */
71 1200000 1275000
72 996000 1250000
73 852000 1250000
74 792000 1175000
75 396000 1175000
76 >;
77 clock-latency = <61036>; /* two CLK32 periods */
78 #cooling-cells = <2>;
79 clocks = <&clks IMX6QDL_CLK_ARM>,
80 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
81 <&clks IMX6QDL_CLK_STEP>,
82 <&clks IMX6QDL_CLK_PLL1_SW>,
83 <&clks IMX6QDL_CLK_PLL1_SYS>;
84 clock-names = "arm", "pll2_pfd2_396m", "step",
85 "pll1_sw", "pll1_sys";
86 arm-supply = <®_arm>;
87 pu-supply = <®_pu>;
88 soc-supply = <®_soc>;
89 };
90
91 cpu2: cpu@2 {
92 compatible = "arm,cortex-a9";
93 device_type = "cpu";
94 reg = <2>;
95 next-level-cache = <&L2>;
96 operating-points = <
97 /* kHz uV */
98 1200000 1275000
99 996000 1250000
100 852000 1250000
101 792000 1175000
102 396000 975000
103 >;
104 fsl,soc-operating-points = <
105 /* ARM kHz SOC-PU uV */
106 1200000 1275000
107 996000 1250000
108 852000 1250000
109 792000 1175000
110 396000 1175000
111 >;
112 clock-latency = <61036>; /* two CLK32 periods */
113 #cooling-cells = <2>;
114 clocks = <&clks IMX6QDL_CLK_ARM>,
115 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
116 <&clks IMX6QDL_CLK_STEP>,
117 <&clks IMX6QDL_CLK_PLL1_SW>,
118 <&clks IMX6QDL_CLK_PLL1_SYS>;
119 clock-names = "arm", "pll2_pfd2_396m", "step",
120 "pll1_sw", "pll1_sys";
121 arm-supply = <®_arm>;
122 pu-supply = <®_pu>;
123 soc-supply = <®_soc>;
124 };
125
126 cpu3: cpu@3 {
127 compatible = "arm,cortex-a9";
128 device_type = "cpu";
129 reg = <3>;
130 next-level-cache = <&L2>;
131 operating-points = <
132 /* kHz uV */
133 1200000 1275000
134 996000 1250000
135 852000 1250000
136 792000 1175000
137 396000 975000
138 >;
139 fsl,soc-operating-points = <
140 /* ARM kHz SOC-PU uV */
141 1200000 1275000
142 996000 1250000
143 852000 1250000
144 792000 1175000
145 396000 1175000
146 >;
147 clock-latency = <61036>; /* two CLK32 periods */
148 #cooling-cells = <2>;
149 clocks = <&clks IMX6QDL_CLK_ARM>,
150 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
151 <&clks IMX6QDL_CLK_STEP>,
152 <&clks IMX6QDL_CLK_PLL1_SW>,
153 <&clks IMX6QDL_CLK_PLL1_SYS>;
154 clock-names = "arm", "pll2_pfd2_396m", "step",
155 "pll1_sw", "pll1_sys";
156 arm-supply = <®_arm>;
157 pu-supply = <®_pu>;
158 soc-supply = <®_soc>;
159 };
160 };
161
162 soc: soc {
163 ocram: sram@900000 {
164 compatible = "mmio-sram";
165 reg = <0x00900000 0x40000>;
166 ranges = <0 0x00900000 0x40000>;
167 #address-cells = <1>;
168 #size-cells = <1>;
169 clocks = <&clks IMX6QDL_CLK_OCRAM>;
170 };
171
172 aips1: bus@2000000 { /* AIPS1 */
173 spba-bus@2000000 {
174 ecspi5: spi@2018000 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02018000 0x4000>;
179 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&clks IMX6Q_CLK_ECSPI5>,
181 <&clks IMX6Q_CLK_ECSPI5>;
182 clock-names = "ipg", "per";
183 dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
184 dma-names = "rx", "tx";
185 status = "disabled";
186 };
187 };
188 };
189
190 sata: sata@2200000 {
191 compatible = "fsl,imx6q-ahci";
192 reg = <0x02200000 0x4000>;
193 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&clks IMX6QDL_CLK_SATA>,
195 <&clks IMX6QDL_CLK_SATA_REF_100M>,
196 <&clks IMX6QDL_CLK_AHB>;
197 clock-names = "sata", "sata_ref", "ahb";
198 status = "disabled";
199 };
200
201 gpu_vg: gpu@2204000 {
202 compatible = "vivante,gc";
203 reg = <0x02204000 0x4000>;
204 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
206 <&clks IMX6QDL_CLK_GPU2D_CORE>;
207 clock-names = "bus", "core";
208 power-domains = <&pd_pu>;
209 #cooling-cells = <2>;
210 };
211
212 ipu2: ipu@2800000 {
213 #address-cells = <1>;
214 #size-cells = <0>;
215 compatible = "fsl,imx6q-ipu";
216 reg = <0x02800000 0x400000>;
217 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
218 <0 7 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&clks IMX6QDL_CLK_IPU2>,
220 <&clks IMX6QDL_CLK_IPU2_DI0>,
221 <&clks IMX6QDL_CLK_IPU2_DI1>;
222 clock-names = "bus", "di0", "di1";
223 resets = <&src 4>;
224
225 ipu2_csi0: port@0 {
226 reg = <0>;
227
228 ipu2_csi0_from_mipi_vc2: endpoint {
229 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
230 };
231 };
232
233 ipu2_csi1: port@1 {
234 reg = <1>;
235
236 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
237 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
238 };
239 };
240
241 ipu2_di0: port@2 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 reg = <2>;
245
246 ipu2_di0_disp0: endpoint@0 {
247 reg = <0>;
248 };
249
250 ipu2_di0_hdmi: endpoint@1 {
251 reg = <1>;
252 remote-endpoint = <&hdmi_mux_2>;
253 };
254
255 ipu2_di0_mipi: endpoint@2 {
256 reg = <2>;
257 remote-endpoint = <&mipi_mux_2>;
258 };
259
260 ipu2_di0_lvds0: endpoint@3 {
261 reg = <3>;
262 remote-endpoint = <&lvds0_mux_2>;
263 };
264
265 ipu2_di0_lvds1: endpoint@4 {
266 reg = <4>;
267 remote-endpoint = <&lvds1_mux_2>;
268 };
269 };
270
271 ipu2_di1: port@3 {
272 #address-cells = <1>;
273 #size-cells = <0>;
274 reg = <3>;
275
276 ipu2_di1_hdmi: endpoint@1 {
277 reg = <1>;
278 remote-endpoint = <&hdmi_mux_3>;
279 };
280
281 ipu2_di1_mipi: endpoint@2 {
282 reg = <2>;
283 remote-endpoint = <&mipi_mux_3>;
284 };
285
286 ipu2_di1_lvds0: endpoint@3 {
287 reg = <3>;
288 remote-endpoint = <&lvds0_mux_3>;
289 };
290
291 ipu2_di1_lvds1: endpoint@4 {
292 reg = <4>;
293 remote-endpoint = <&lvds1_mux_3>;
294 };
295 };
296 };
297 };
298
299 capture-subsystem {
300 compatible = "fsl,imx-capture-subsystem";
301 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
302 };
303
304 display-subsystem {
305 compatible = "fsl,imx-display-subsystem";
306 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
307 };
308};
309
310&gpio1 {
311 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
312 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
313 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
314 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
315 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
316 <&iomuxc 22 116 10>;
317};
318
319&gpio2 {
320 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
321 <&iomuxc 31 44 1>;
322};
323
324&gpio3 {
325 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
326};
327
328&gpio4 {
329 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
330};
331
332&gpio5 {
333 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
334 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
335};
336
337&gpio6 {
338 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
339 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
340 <&iomuxc 31 86 1>;
341};
342
343&gpio7 {
344 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
345};
346
347&gpr {
348 ipu1_csi0_mux {
349 compatible = "video-mux";
350 mux-controls = <&mux 0>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353
354 port@0 {
355 reg = <0>;
356
357 ipu1_csi0_mux_from_mipi_vc0: endpoint {
358 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
359 };
360 };
361
362 port@1 {
363 reg = <1>;
364
365 ipu1_csi0_mux_from_parallel_sensor: endpoint {
366 };
367 };
368
369 port@2 {
370 reg = <2>;
371
372 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
373 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
374 };
375 };
376 };
377
378 ipu2_csi1_mux {
379 compatible = "video-mux";
380 mux-controls = <&mux 1>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383
384 port@0 {
385 reg = <0>;
386
387 ipu2_csi1_mux_from_mipi_vc3: endpoint {
388 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
389 };
390 };
391
392 port@1 {
393 reg = <1>;
394
395 ipu2_csi1_mux_from_parallel_sensor: endpoint {
396 };
397 };
398
399 port@2 {
400 reg = <2>;
401
402 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
403 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
404 };
405 };
406 };
407};
408
409&hdmi {
410 compatible = "fsl,imx6q-hdmi";
411
412 ports {
413 port@2 {
414 reg = <2>;
415
416 hdmi_mux_2: endpoint {
417 remote-endpoint = <&ipu2_di0_hdmi>;
418 };
419 };
420
421 port@3 {
422 reg = <3>;
423
424 hdmi_mux_3: endpoint {
425 remote-endpoint = <&ipu2_di1_hdmi>;
426 };
427 };
428 };
429};
430
431&iomuxc {
432 compatible = "fsl,imx6q-iomuxc";
433};
434
435&ipu1_csi1 {
436 ipu1_csi1_from_mipi_vc1: endpoint {
437 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
438 };
439};
440
441&ldb {
442 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
443 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
444 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
445 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
446 clock-names = "di0_pll", "di1_pll",
447 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
448 "di0", "di1";
449
450 lvds-channel@0 {
451 port@2 {
452 reg = <2>;
453
454 lvds0_mux_2: endpoint {
455 remote-endpoint = <&ipu2_di0_lvds0>;
456 };
457 };
458
459 port@3 {
460 reg = <3>;
461
462 lvds0_mux_3: endpoint {
463 remote-endpoint = <&ipu2_di1_lvds0>;
464 };
465 };
466 };
467
468 lvds-channel@1 {
469 port@2 {
470 reg = <2>;
471
472 lvds1_mux_2: endpoint {
473 remote-endpoint = <&ipu2_di0_lvds1>;
474 };
475 };
476
477 port@3 {
478 reg = <3>;
479
480 lvds1_mux_3: endpoint {
481 remote-endpoint = <&ipu2_di1_lvds1>;
482 };
483 };
484 };
485};
486
487&mipi_csi {
488 port@1 {
489 reg = <1>;
490
491 mipi_vc0_to_ipu1_csi0_mux: endpoint {
492 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
493 };
494 };
495
496 port@2 {
497 reg = <2>;
498
499 mipi_vc1_to_ipu1_csi1: endpoint {
500 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
501 };
502 };
503
504 port@3 {
505 reg = <3>;
506
507 mipi_vc2_to_ipu2_csi0: endpoint {
508 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
509 };
510 };
511
512 port@4 {
513 reg = <4>;
514
515 mipi_vc3_to_ipu2_csi1_mux: endpoint {
516 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
517 };
518 };
519};
520
521&mipi_dsi {
522 ports {
523 port@2 {
524 reg = <2>;
525
526 mipi_mux_2: endpoint {
527 remote-endpoint = <&ipu2_di0_mipi>;
528 };
529 };
530
531 port@3 {
532 reg = <3>;
533
534 mipi_mux_3: endpoint {
535 remote-endpoint = <&ipu2_di1_mipi>;
536 };
537 };
538 };
539};
540
541&mux {
542 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
543 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
544 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
545 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
546 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
547 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
548 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
549};
550
551&vpu {
552 compatible = "fsl,imx6q-vpu", "cnm,coda960";
553};
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 cpu@0 {
29 compatible = "arm,cortex-a9";
30 reg = <0>;
31 next-level-cache = <&L2>;
32 };
33
34 cpu@1 {
35 compatible = "arm,cortex-a9";
36 reg = <1>;
37 next-level-cache = <&L2>;
38 };
39
40 cpu@2 {
41 compatible = "arm,cortex-a9";
42 reg = <2>;
43 next-level-cache = <&L2>;
44 };
45
46 cpu@3 {
47 compatible = "arm,cortex-a9";
48 reg = <3>;
49 next-level-cache = <&L2>;
50 };
51 };
52
53 intc: interrupt-controller@00a01000 {
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58 interrupt-controller;
59 reg = <0x00a01000 0x1000>,
60 <0x00a00100 0x100>;
61 };
62
63 clocks {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ckil {
68 compatible = "fsl,imx-ckil", "fixed-clock";
69 clock-frequency = <32768>;
70 };
71
72 ckih1 {
73 compatible = "fsl,imx-ckih1", "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 osc {
78 compatible = "fsl,imx-osc", "fixed-clock";
79 clock-frequency = <24000000>;
80 };
81 };
82
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&intc>;
88 ranges;
89
90 timer@00a00600 {
91 compatible = "arm,cortex-a9-twd-timer";
92 reg = <0x00a00600 0x20>;
93 interrupts = <1 13 0xf01>;
94 };
95
96 L2: l2-cache@00a02000 {
97 compatible = "arm,pl310-cache";
98 reg = <0x00a02000 0x1000>;
99 interrupts = <0 92 0x04>;
100 cache-unified;
101 cache-level = <2>;
102 };
103
104 aips-bus@02000000 { /* AIPS1 */
105 compatible = "fsl,aips-bus", "simple-bus";
106 #address-cells = <1>;
107 #size-cells = <1>;
108 reg = <0x02000000 0x100000>;
109 ranges;
110
111 spba-bus@02000000 {
112 compatible = "fsl,spba-bus", "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x02000000 0x40000>;
116 ranges;
117
118 spdif@02004000 {
119 reg = <0x02004000 0x4000>;
120 interrupts = <0 52 0x04>;
121 };
122
123 ecspi@02008000 { /* eCSPI1 */
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
127 reg = <0x02008000 0x4000>;
128 interrupts = <0 31 0x04>;
129 status = "disabled";
130 };
131
132 ecspi@0200c000 { /* eCSPI2 */
133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
136 reg = <0x0200c000 0x4000>;
137 interrupts = <0 32 0x04>;
138 status = "disabled";
139 };
140
141 ecspi@02010000 { /* eCSPI3 */
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
145 reg = <0x02010000 0x4000>;
146 interrupts = <0 33 0x04>;
147 status = "disabled";
148 };
149
150 ecspi@02014000 { /* eCSPI4 */
151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
154 reg = <0x02014000 0x4000>;
155 interrupts = <0 34 0x04>;
156 status = "disabled";
157 };
158
159 ecspi@02018000 { /* eCSPI5 */
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
163 reg = <0x02018000 0x4000>;
164 interrupts = <0 35 0x04>;
165 status = "disabled";
166 };
167
168 uart1: serial@02020000 {
169 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
170 reg = <0x02020000 0x4000>;
171 interrupts = <0 26 0x04>;
172 status = "disabled";
173 };
174
175 esai@02024000 {
176 reg = <0x02024000 0x4000>;
177 interrupts = <0 51 0x04>;
178 };
179
180 ssi1: ssi@02028000 {
181 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
182 reg = <0x02028000 0x4000>;
183 interrupts = <0 46 0x04>;
184 fsl,fifo-depth = <15>;
185 fsl,ssi-dma-events = <38 37>;
186 status = "disabled";
187 };
188
189 ssi2: ssi@0202c000 {
190 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
191 reg = <0x0202c000 0x4000>;
192 interrupts = <0 47 0x04>;
193 fsl,fifo-depth = <15>;
194 fsl,ssi-dma-events = <42 41>;
195 status = "disabled";
196 };
197
198 ssi3: ssi@02030000 {
199 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
200 reg = <0x02030000 0x4000>;
201 interrupts = <0 48 0x04>;
202 fsl,fifo-depth = <15>;
203 fsl,ssi-dma-events = <46 45>;
204 status = "disabled";
205 };
206
207 asrc@02034000 {
208 reg = <0x02034000 0x4000>;
209 interrupts = <0 50 0x04>;
210 };
211
212 spba@0203c000 {
213 reg = <0x0203c000 0x4000>;
214 };
215 };
216
217 vpu@02040000 {
218 reg = <0x02040000 0x3c000>;
219 interrupts = <0 3 0x04 0 12 0x04>;
220 };
221
222 aipstz@0207c000 { /* AIPSTZ1 */
223 reg = <0x0207c000 0x4000>;
224 };
225
226 pwm@02080000 { /* PWM1 */
227 reg = <0x02080000 0x4000>;
228 interrupts = <0 83 0x04>;
229 };
230
231 pwm@02084000 { /* PWM2 */
232 reg = <0x02084000 0x4000>;
233 interrupts = <0 84 0x04>;
234 };
235
236 pwm@02088000 { /* PWM3 */
237 reg = <0x02088000 0x4000>;
238 interrupts = <0 85 0x04>;
239 };
240
241 pwm@0208c000 { /* PWM4 */
242 reg = <0x0208c000 0x4000>;
243 interrupts = <0 86 0x04>;
244 };
245
246 flexcan@02090000 { /* CAN1 */
247 reg = <0x02090000 0x4000>;
248 interrupts = <0 110 0x04>;
249 };
250
251 flexcan@02094000 { /* CAN2 */
252 reg = <0x02094000 0x4000>;
253 interrupts = <0 111 0x04>;
254 };
255
256 gpt@02098000 {
257 compatible = "fsl,imx6q-gpt";
258 reg = <0x02098000 0x4000>;
259 interrupts = <0 55 0x04>;
260 };
261
262 gpio1: gpio@0209c000 {
263 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
264 reg = <0x0209c000 0x4000>;
265 interrupts = <0 66 0x04 0 67 0x04>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
269 #interrupt-cells = <1>;
270 };
271
272 gpio2: gpio@020a0000 {
273 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
274 reg = <0x020a0000 0x4000>;
275 interrupts = <0 68 0x04 0 69 0x04>;
276 gpio-controller;
277 #gpio-cells = <2>;
278 interrupt-controller;
279 #interrupt-cells = <1>;
280 };
281
282 gpio3: gpio@020a4000 {
283 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
284 reg = <0x020a4000 0x4000>;
285 interrupts = <0 70 0x04 0 71 0x04>;
286 gpio-controller;
287 #gpio-cells = <2>;
288 interrupt-controller;
289 #interrupt-cells = <1>;
290 };
291
292 gpio4: gpio@020a8000 {
293 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
294 reg = <0x020a8000 0x4000>;
295 interrupts = <0 72 0x04 0 73 0x04>;
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-controller;
299 #interrupt-cells = <1>;
300 };
301
302 gpio5: gpio@020ac000 {
303 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
304 reg = <0x020ac000 0x4000>;
305 interrupts = <0 74 0x04 0 75 0x04>;
306 gpio-controller;
307 #gpio-cells = <2>;
308 interrupt-controller;
309 #interrupt-cells = <1>;
310 };
311
312 gpio6: gpio@020b0000 {
313 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
314 reg = <0x020b0000 0x4000>;
315 interrupts = <0 76 0x04 0 77 0x04>;
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <1>;
320 };
321
322 gpio7: gpio@020b4000 {
323 compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
324 reg = <0x020b4000 0x4000>;
325 interrupts = <0 78 0x04 0 79 0x04>;
326 gpio-controller;
327 #gpio-cells = <2>;
328 interrupt-controller;
329 #interrupt-cells = <1>;
330 };
331
332 kpp@020b8000 {
333 reg = <0x020b8000 0x4000>;
334 interrupts = <0 82 0x04>;
335 };
336
337 wdog@020bc000 { /* WDOG1 */
338 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
339 reg = <0x020bc000 0x4000>;
340 interrupts = <0 80 0x04>;
341 status = "disabled";
342 };
343
344 wdog@020c0000 { /* WDOG2 */
345 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
346 reg = <0x020c0000 0x4000>;
347 interrupts = <0 81 0x04>;
348 status = "disabled";
349 };
350
351 ccm@020c4000 {
352 compatible = "fsl,imx6q-ccm";
353 reg = <0x020c4000 0x4000>;
354 interrupts = <0 87 0x04 0 88 0x04>;
355 };
356
357 anatop@020c8000 {
358 compatible = "fsl,imx6q-anatop";
359 reg = <0x020c8000 0x1000>;
360 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
361
362 regulator-1p1@110 {
363 compatible = "fsl,anatop-regulator";
364 regulator-name = "vdd1p1";
365 regulator-min-microvolt = <800000>;
366 regulator-max-microvolt = <1375000>;
367 regulator-always-on;
368 anatop-reg-offset = <0x110>;
369 anatop-vol-bit-shift = <8>;
370 anatop-vol-bit-width = <5>;
371 anatop-min-bit-val = <4>;
372 anatop-min-voltage = <800000>;
373 anatop-max-voltage = <1375000>;
374 };
375
376 regulator-3p0@120 {
377 compatible = "fsl,anatop-regulator";
378 regulator-name = "vdd3p0";
379 regulator-min-microvolt = <2800000>;
380 regulator-max-microvolt = <3150000>;
381 regulator-always-on;
382 anatop-reg-offset = <0x120>;
383 anatop-vol-bit-shift = <8>;
384 anatop-vol-bit-width = <5>;
385 anatop-min-bit-val = <0>;
386 anatop-min-voltage = <2625000>;
387 anatop-max-voltage = <3400000>;
388 };
389
390 regulator-2p5@130 {
391 compatible = "fsl,anatop-regulator";
392 regulator-name = "vdd2p5";
393 regulator-min-microvolt = <2000000>;
394 regulator-max-microvolt = <2750000>;
395 regulator-always-on;
396 anatop-reg-offset = <0x130>;
397 anatop-vol-bit-shift = <8>;
398 anatop-vol-bit-width = <5>;
399 anatop-min-bit-val = <0>;
400 anatop-min-voltage = <2000000>;
401 anatop-max-voltage = <2750000>;
402 };
403
404 regulator-vddcore@140 {
405 compatible = "fsl,anatop-regulator";
406 regulator-name = "cpu";
407 regulator-min-microvolt = <725000>;
408 regulator-max-microvolt = <1450000>;
409 regulator-always-on;
410 anatop-reg-offset = <0x140>;
411 anatop-vol-bit-shift = <0>;
412 anatop-vol-bit-width = <5>;
413 anatop-min-bit-val = <1>;
414 anatop-min-voltage = <725000>;
415 anatop-max-voltage = <1450000>;
416 };
417
418 regulator-vddpu@140 {
419 compatible = "fsl,anatop-regulator";
420 regulator-name = "vddpu";
421 regulator-min-microvolt = <725000>;
422 regulator-max-microvolt = <1450000>;
423 regulator-always-on;
424 anatop-reg-offset = <0x140>;
425 anatop-vol-bit-shift = <9>;
426 anatop-vol-bit-width = <5>;
427 anatop-min-bit-val = <1>;
428 anatop-min-voltage = <725000>;
429 anatop-max-voltage = <1450000>;
430 };
431
432 regulator-vddsoc@140 {
433 compatible = "fsl,anatop-regulator";
434 regulator-name = "vddsoc";
435 regulator-min-microvolt = <725000>;
436 regulator-max-microvolt = <1450000>;
437 regulator-always-on;
438 anatop-reg-offset = <0x140>;
439 anatop-vol-bit-shift = <18>;
440 anatop-vol-bit-width = <5>;
441 anatop-min-bit-val = <1>;
442 anatop-min-voltage = <725000>;
443 anatop-max-voltage = <1450000>;
444 };
445 };
446
447 usbphy@020c9000 { /* USBPHY1 */
448 reg = <0x020c9000 0x1000>;
449 interrupts = <0 44 0x04>;
450 };
451
452 usbphy@020ca000 { /* USBPHY2 */
453 reg = <0x020ca000 0x1000>;
454 interrupts = <0 45 0x04>;
455 };
456
457 snvs@020cc000 {
458 reg = <0x020cc000 0x4000>;
459 interrupts = <0 19 0x04 0 20 0x04>;
460 };
461
462 epit@020d0000 { /* EPIT1 */
463 reg = <0x020d0000 0x4000>;
464 interrupts = <0 56 0x04>;
465 };
466
467 epit@020d4000 { /* EPIT2 */
468 reg = <0x020d4000 0x4000>;
469 interrupts = <0 57 0x04>;
470 };
471
472 src@020d8000 {
473 compatible = "fsl,imx6q-src";
474 reg = <0x020d8000 0x4000>;
475 interrupts = <0 91 0x04 0 96 0x04>;
476 };
477
478 gpc@020dc000 {
479 compatible = "fsl,imx6q-gpc";
480 reg = <0x020dc000 0x4000>;
481 interrupts = <0 89 0x04 0 90 0x04>;
482 };
483
484 iomuxc@020e0000 {
485 compatible = "fsl,imx6q-iomuxc";
486 reg = <0x020e0000 0x4000>;
487
488 /* shared pinctrl settings */
489 audmux {
490 pinctrl_audmux_1: audmux-1 {
491 fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
492 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
493 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
494 3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
495 };
496 };
497
498 i2c1 {
499 pinctrl_i2c1_1: i2c1grp-1 {
500 fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
501 196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
502 };
503 };
504
505 serial2 {
506 pinctrl_serial2_1: serial2grp-1 {
507 fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
508 191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
509 };
510 };
511
512 usdhc3 {
513 pinctrl_usdhc3_1: usdhc3grp-1 {
514 fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
515 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
516 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
517 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
518 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
519 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
520 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
521 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
522 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
523 1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
524 };
525 };
526
527 usdhc4 {
528 pinctrl_usdhc4_1: usdhc4grp-1 {
529 fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
530 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
531 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
532 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
533 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
534 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
535 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
536 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
537 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
538 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
539 };
540 };
541 };
542
543 dcic@020e4000 { /* DCIC1 */
544 reg = <0x020e4000 0x4000>;
545 interrupts = <0 124 0x04>;
546 };
547
548 dcic@020e8000 { /* DCIC2 */
549 reg = <0x020e8000 0x4000>;
550 interrupts = <0 125 0x04>;
551 };
552
553 sdma@020ec000 {
554 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
555 reg = <0x020ec000 0x4000>;
556 interrupts = <0 2 0x04>;
557 };
558 };
559
560 aips-bus@02100000 { /* AIPS2 */
561 compatible = "fsl,aips-bus", "simple-bus";
562 #address-cells = <1>;
563 #size-cells = <1>;
564 reg = <0x02100000 0x100000>;
565 ranges;
566
567 caam@02100000 {
568 reg = <0x02100000 0x40000>;
569 interrupts = <0 105 0x04 0 106 0x04>;
570 };
571
572 aipstz@0217c000 { /* AIPSTZ2 */
573 reg = <0x0217c000 0x4000>;
574 };
575
576 ethernet@02188000 {
577 compatible = "fsl,imx6q-fec";
578 reg = <0x02188000 0x4000>;
579 interrupts = <0 118 0x04 0 119 0x04>;
580 status = "disabled";
581 };
582
583 mlb@0218c000 {
584 reg = <0x0218c000 0x4000>;
585 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
586 };
587
588 usdhc@02190000 { /* uSDHC1 */
589 compatible = "fsl,imx6q-usdhc";
590 reg = <0x02190000 0x4000>;
591 interrupts = <0 22 0x04>;
592 status = "disabled";
593 };
594
595 usdhc@02194000 { /* uSDHC2 */
596 compatible = "fsl,imx6q-usdhc";
597 reg = <0x02194000 0x4000>;
598 interrupts = <0 23 0x04>;
599 status = "disabled";
600 };
601
602 usdhc@02198000 { /* uSDHC3 */
603 compatible = "fsl,imx6q-usdhc";
604 reg = <0x02198000 0x4000>;
605 interrupts = <0 24 0x04>;
606 status = "disabled";
607 };
608
609 usdhc@0219c000 { /* uSDHC4 */
610 compatible = "fsl,imx6q-usdhc";
611 reg = <0x0219c000 0x4000>;
612 interrupts = <0 25 0x04>;
613 status = "disabled";
614 };
615
616 i2c@021a0000 { /* I2C1 */
617 #address-cells = <1>;
618 #size-cells = <0>;
619 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
620 reg = <0x021a0000 0x4000>;
621 interrupts = <0 36 0x04>;
622 status = "disabled";
623 };
624
625 i2c@021a4000 { /* I2C2 */
626 #address-cells = <1>;
627 #size-cells = <0>;
628 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
629 reg = <0x021a4000 0x4000>;
630 interrupts = <0 37 0x04>;
631 status = "disabled";
632 };
633
634 i2c@021a8000 { /* I2C3 */
635 #address-cells = <1>;
636 #size-cells = <0>;
637 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
638 reg = <0x021a8000 0x4000>;
639 interrupts = <0 38 0x04>;
640 status = "disabled";
641 };
642
643 romcp@021ac000 {
644 reg = <0x021ac000 0x4000>;
645 };
646
647 mmdc@021b0000 { /* MMDC0 */
648 compatible = "fsl,imx6q-mmdc";
649 reg = <0x021b0000 0x4000>;
650 };
651
652 mmdc@021b4000 { /* MMDC1 */
653 reg = <0x021b4000 0x4000>;
654 };
655
656 weim@021b8000 {
657 reg = <0x021b8000 0x4000>;
658 interrupts = <0 14 0x04>;
659 };
660
661 ocotp@021bc000 {
662 reg = <0x021bc000 0x4000>;
663 };
664
665 ocotp@021c0000 {
666 reg = <0x021c0000 0x4000>;
667 interrupts = <0 21 0x04>;
668 };
669
670 tzasc@021d0000 { /* TZASC1 */
671 reg = <0x021d0000 0x4000>;
672 interrupts = <0 108 0x04>;
673 };
674
675 tzasc@021d4000 { /* TZASC2 */
676 reg = <0x021d4000 0x4000>;
677 interrupts = <0 109 0x04>;
678 };
679
680 audmux@021d8000 {
681 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
682 reg = <0x021d8000 0x4000>;
683 status = "disabled";
684 };
685
686 mipi@021dc000 { /* MIPI-CSI */
687 reg = <0x021dc000 0x4000>;
688 };
689
690 mipi@021e0000 { /* MIPI-DSI */
691 reg = <0x021e0000 0x4000>;
692 };
693
694 vdoa@021e4000 {
695 reg = <0x021e4000 0x4000>;
696 interrupts = <0 18 0x04>;
697 };
698
699 uart2: serial@021e8000 {
700 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
701 reg = <0x021e8000 0x4000>;
702 interrupts = <0 27 0x04>;
703 status = "disabled";
704 };
705
706 uart3: serial@021ec000 {
707 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
708 reg = <0x021ec000 0x4000>;
709 interrupts = <0 28 0x04>;
710 status = "disabled";
711 };
712
713 uart4: serial@021f0000 {
714 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
715 reg = <0x021f0000 0x4000>;
716 interrupts = <0 29 0x04>;
717 status = "disabled";
718 };
719
720 uart5: serial@021f4000 {
721 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
722 reg = <0x021f4000 0x4000>;
723 interrupts = <0 30 0x04>;
724 status = "disabled";
725 };
726 };
727 };
728};