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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2011 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
5
6#include "imx51-pinfunc.h"
7#include <dt-bindings/clock/imx5-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 /*
16 * The decompressor and also some bootloaders rely on a
17 * pre-existing /chosen node to be available to insert the
18 * command line and merge other ATAGS info.
19 */
20 chosen {};
21
22 aliases {
23 ethernet0 = &fec;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 mmc0 = &esdhc1;
31 mmc1 = &esdhc2;
32 mmc2 = &esdhc3;
33 mmc3 = &esdhc4;
34 serial0 = &uart1;
35 serial1 = &uart2;
36 serial2 = &uart3;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &cspi;
40 };
41
42 tzic: tz-interrupt-controller@e0000000 {
43 compatible = "fsl,imx51-tzic", "fsl,tzic";
44 interrupt-controller;
45 #interrupt-cells = <1>;
46 reg = <0xe0000000 0x4000>;
47 };
48
49 clocks {
50 ckil {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <32768>;
54 };
55
56 ckih1 {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <0>;
60 };
61
62 ckih2 {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
67
68 osc {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <24000000>;
72 };
73 };
74
75 cpus {
76 #address-cells = <1>;
77 #size-cells = <0>;
78 cpu: cpu@0 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a8";
81 reg = <0>;
82 clock-latency = <62500>;
83 clocks = <&clks IMX5_CLK_CPU_PODF>;
84 clock-names = "cpu";
85 operating-points = <
86 166000 1000000
87 600000 1050000
88 800000 1100000
89 >;
90 voltage-tolerance = <5>;
91 };
92 };
93
94 pmu: pmu {
95 compatible = "arm,cortex-a8-pmu";
96 interrupt-parent = <&tzic>;
97 interrupts = <77>;
98 };
99
100 usbphy0: usbphy0 {
101 compatible = "usb-nop-xceiv";
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
103 clock-names = "main_clk";
104 #phy-cells = <0>;
105 };
106
107 capture-subsystem {
108 compatible = "fsl,imx-capture-subsystem";
109 ports = <&ipu_csi0>, <&ipu_csi1>;
110 };
111
112 display-subsystem {
113 compatible = "fsl,imx-display-subsystem";
114 ports = <&ipu_di0>, <&ipu_di1>;
115 };
116
117 soc: soc {
118 #address-cells = <1>;
119 #size-cells = <1>;
120 compatible = "simple-bus";
121 interrupt-parent = <&tzic>;
122 ranges;
123
124 iram: sram@1ffe0000 {
125 compatible = "mmio-sram";
126 reg = <0x1ffe0000 0x20000>;
127 };
128
129 gpu: gpu@30000000 {
130 compatible = "amd,imageon-200.1", "amd,imageon";
131 reg = <0x30000000 0x20000>;
132 reg-names = "kgsl_3d0_reg_memory";
133 interrupts = <12>;
134 interrupt-names = "kgsl_3d0_irq";
135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
136 clock-names = "core_clk", "mem_iface_clk";
137 };
138
139 ipu: ipu@40000000 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 compatible = "fsl,imx51-ipu";
143 reg = <0x40000000 0x20000000>;
144 interrupts = <11 10>;
145 clocks = <&clks IMX5_CLK_IPU_GATE>,
146 <&clks IMX5_CLK_IPU_DI0_GATE>,
147 <&clks IMX5_CLK_IPU_DI1_GATE>;
148 clock-names = "bus", "di0", "di1";
149 resets = <&src 2>;
150
151 ipu_csi0: port@0 {
152 reg = <0>;
153 };
154
155 ipu_csi1: port@1 {
156 reg = <1>;
157 };
158
159 ipu_di0: port@2 {
160 reg = <2>;
161
162 ipu_di0_disp1: endpoint {
163 };
164 };
165
166 ipu_di1: port@3 {
167 reg = <3>;
168
169 ipu_di1_disp2: endpoint {
170 };
171 };
172 };
173
174 aips1: bus@70000000 { /* AIPS1 */
175 compatible = "fsl,aips-bus", "simple-bus";
176 #address-cells = <1>;
177 #size-cells = <1>;
178 reg = <0x70000000 0x10000000>;
179 ranges;
180
181 spba-bus@70000000 {
182 compatible = "fsl,spba-bus", "simple-bus";
183 #address-cells = <1>;
184 #size-cells = <1>;
185 reg = <0x70000000 0x40000>;
186 ranges;
187
188 esdhc1: mmc@70004000 {
189 compatible = "fsl,imx51-esdhc";
190 reg = <0x70004000 0x4000>;
191 interrupts = <1>;
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
195 clock-names = "ipg", "ahb", "per";
196 status = "disabled";
197 };
198
199 esdhc2: mmc@70008000 {
200 compatible = "fsl,imx51-esdhc";
201 reg = <0x70008000 0x4000>;
202 interrupts = <2>;
203 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
204 <&clks IMX5_CLK_DUMMY>,
205 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
206 clock-names = "ipg", "ahb", "per";
207 bus-width = <4>;
208 status = "disabled";
209 };
210
211 uart3: serial@7000c000 {
212 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
213 reg = <0x7000c000 0x4000>;
214 interrupts = <33>;
215 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
216 <&clks IMX5_CLK_UART3_PER_GATE>;
217 clock-names = "ipg", "per";
218 dmas = <&sdma 43 5 1>, <&sdma 44 5 2>;
219 dma-names = "rx", "tx";
220 status = "disabled";
221 };
222
223 ecspi1: spi@70010000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "fsl,imx51-ecspi";
227 reg = <0x70010000 0x4000>;
228 interrupts = <36>;
229 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
230 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
231 clock-names = "ipg", "per";
232 status = "disabled";
233 };
234
235 ssi2: ssi@70014000 {
236 #sound-dai-cells = <0>;
237 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
238 reg = <0x70014000 0x4000>;
239 interrupts = <30>;
240 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
241 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
242 clock-names = "ipg", "baud";
243 dmas = <&sdma 24 1 0>,
244 <&sdma 25 1 0>;
245 dma-names = "rx", "tx";
246 fsl,fifo-depth = <15>;
247 status = "disabled";
248 };
249
250 esdhc3: mmc@70020000 {
251 compatible = "fsl,imx51-esdhc";
252 reg = <0x70020000 0x4000>;
253 interrupts = <3>;
254 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
255 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
257 clock-names = "ipg", "ahb", "per";
258 bus-width = <4>;
259 status = "disabled";
260 };
261
262 esdhc4: mmc@70024000 {
263 compatible = "fsl,imx51-esdhc";
264 reg = <0x70024000 0x4000>;
265 interrupts = <4>;
266 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
267 <&clks IMX5_CLK_DUMMY>,
268 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
269 clock-names = "ipg", "ahb", "per";
270 bus-width = <4>;
271 status = "disabled";
272 };
273 };
274
275 aipstz1: bridge@73f00000 {
276 compatible = "fsl,imx51-aipstz";
277 reg = <0x73f00000 0x60>;
278 };
279
280 usbotg: usb@73f80000 {
281 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
282 reg = <0x73f80000 0x0200>;
283 interrupts = <18>;
284 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
285 fsl,usbmisc = <&usbmisc 0>;
286 fsl,usbphy = <&usbphy0>;
287 status = "disabled";
288 };
289
290 usbh1: usb@73f80200 {
291 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
292 reg = <0x73f80200 0x0200>;
293 interrupts = <14>;
294 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
295 fsl,usbmisc = <&usbmisc 1>;
296 dr_mode = "host";
297 status = "disabled";
298 };
299
300 usbh2: usb@73f80400 {
301 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
302 reg = <0x73f80400 0x0200>;
303 interrupts = <16>;
304 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
305 fsl,usbmisc = <&usbmisc 2>;
306 dr_mode = "host";
307 status = "disabled";
308 };
309
310 usbh3: usb@73f80600 {
311 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
312 reg = <0x73f80600 0x0200>;
313 interrupts = <17>;
314 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
315 fsl,usbmisc = <&usbmisc 3>;
316 dr_mode = "host";
317 status = "disabled";
318 };
319
320 usbmisc: usbmisc@73f80800 {
321 #index-cells = <1>;
322 compatible = "fsl,imx51-usbmisc";
323 reg = <0x73f80800 0x200>;
324 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
325 };
326
327 gpio1: gpio@73f84000 {
328 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
329 reg = <0x73f84000 0x4000>;
330 interrupts = <50 51>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
335 };
336
337 gpio2: gpio@73f88000 {
338 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
339 reg = <0x73f88000 0x4000>;
340 interrupts = <52 53>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 };
346
347 gpio3: gpio@73f8c000 {
348 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
349 reg = <0x73f8c000 0x4000>;
350 interrupts = <54 55>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
354 #interrupt-cells = <2>;
355 };
356
357 gpio4: gpio@73f90000 {
358 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
359 reg = <0x73f90000 0x4000>;
360 interrupts = <56 57>;
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
365 };
366
367 kpp: kpp@73f94000 {
368 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
369 reg = <0x73f94000 0x4000>;
370 interrupts = <60>;
371 clocks = <&clks IMX5_CLK_DUMMY>;
372 status = "disabled";
373 };
374
375 wdog1: watchdog@73f98000 {
376 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
377 reg = <0x73f98000 0x4000>;
378 interrupts = <58>;
379 clocks = <&clks IMX5_CLK_DUMMY>;
380 };
381
382 wdog2: watchdog@73f9c000 {
383 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
384 reg = <0x73f9c000 0x4000>;
385 interrupts = <59>;
386 clocks = <&clks IMX5_CLK_DUMMY>;
387 status = "disabled";
388 };
389
390 gpt: timer@73fa0000 {
391 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
392 reg = <0x73fa0000 0x4000>;
393 interrupts = <39>;
394 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
395 <&clks IMX5_CLK_GPT_HF_GATE>;
396 clock-names = "ipg", "per";
397 };
398
399 iomuxc: iomuxc@73fa8000 {
400 compatible = "fsl,imx51-iomuxc";
401 reg = <0x73fa8000 0x4000>;
402 };
403
404 pwm1: pwm@73fb4000 {
405 #pwm-cells = <3>;
406 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
407 reg = <0x73fb4000 0x4000>;
408 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
409 <&clks IMX5_CLK_PWM1_HF_GATE>;
410 clock-names = "ipg", "per";
411 interrupts = <61>;
412 };
413
414 pwm2: pwm@73fb8000 {
415 #pwm-cells = <3>;
416 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
417 reg = <0x73fb8000 0x4000>;
418 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
419 <&clks IMX5_CLK_PWM2_HF_GATE>;
420 clock-names = "ipg", "per";
421 interrupts = <94>;
422 };
423
424 uart1: serial@73fbc000 {
425 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
426 reg = <0x73fbc000 0x4000>;
427 interrupts = <31>;
428 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
429 <&clks IMX5_CLK_UART1_PER_GATE>;
430 clock-names = "ipg", "per";
431 dmas = <&sdma 18 4 1>, <&sdma 19 4 2>;
432 dma-names = "rx", "tx";
433 status = "disabled";
434 };
435
436 uart2: serial@73fc0000 {
437 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
438 reg = <0x73fc0000 0x4000>;
439 interrupts = <32>;
440 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
441 <&clks IMX5_CLK_UART2_PER_GATE>;
442 clock-names = "ipg", "per";
443 dmas = <&sdma 16 4 1>, <&sdma 17 4 2>;
444 dma-names = "rx", "tx";
445 status = "disabled";
446 };
447
448 src: reset-controller@73fd0000 {
449 compatible = "fsl,imx51-src";
450 reg = <0x73fd0000 0x4000>;
451 interrupts = <75>;
452 #reset-cells = <1>;
453 };
454
455 clks: ccm@73fd4000{
456 compatible = "fsl,imx51-ccm";
457 reg = <0x73fd4000 0x4000>;
458 interrupts = <0 71 0x04 0 72 0x04>;
459 #clock-cells = <1>;
460 };
461 };
462
463 aips2: bus@80000000 { /* AIPS2 */
464 compatible = "fsl,aips-bus", "simple-bus";
465 #address-cells = <1>;
466 #size-cells = <1>;
467 reg = <0x80000000 0x10000000>;
468 ranges;
469
470 aipstz2: bridge@83f00000 {
471 compatible = "fsl,imx51-aipstz";
472 reg = <0x83f00000 0x60>;
473 };
474
475 iim: efuse@83f98000 {
476 compatible = "fsl,imx51-iim", "fsl,imx27-iim", "syscon";
477 reg = <0x83f98000 0x4000>;
478 interrupts = <69>;
479 clocks = <&clks IMX5_CLK_IIM_GATE>;
480 };
481
482 tigerp: tigerp@83fa0000 {
483 compatible = "fsl,imx51-tigerp";
484 reg = <0x83fa0000 0x28>;
485 };
486
487 owire: owire@83fa4000 {
488 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
489 reg = <0x83fa4000 0x4000>;
490 interrupts = <88>;
491 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
492 status = "disabled";
493 };
494
495 ecspi2: spi@83fac000 {
496 #address-cells = <1>;
497 #size-cells = <0>;
498 compatible = "fsl,imx51-ecspi";
499 reg = <0x83fac000 0x4000>;
500 interrupts = <37>;
501 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
502 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
503 clock-names = "ipg", "per";
504 status = "disabled";
505 };
506
507 sdma: dma-controller@83fb0000 {
508 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
509 reg = <0x83fb0000 0x4000>;
510 interrupts = <6>;
511 clocks = <&clks IMX5_CLK_SDMA_GATE>,
512 <&clks IMX5_CLK_AHB>;
513 clock-names = "ipg", "ahb";
514 #dma-cells = <3>;
515 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
516 };
517
518 cspi: spi@83fc0000 {
519 #address-cells = <1>;
520 #size-cells = <0>;
521 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
522 reg = <0x83fc0000 0x4000>;
523 interrupts = <38>;
524 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
525 <&clks IMX5_CLK_CSPI_IPG_GATE>;
526 clock-names = "ipg", "per";
527 status = "disabled";
528 };
529
530 i2c2: i2c@83fc4000 {
531 #address-cells = <1>;
532 #size-cells = <0>;
533 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
534 reg = <0x83fc4000 0x4000>;
535 interrupts = <63>;
536 clocks = <&clks IMX5_CLK_I2C2_GATE>;
537 status = "disabled";
538 };
539
540 i2c1: i2c@83fc8000 {
541 #address-cells = <1>;
542 #size-cells = <0>;
543 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
544 reg = <0x83fc8000 0x4000>;
545 interrupts = <62>;
546 clocks = <&clks IMX5_CLK_I2C1_GATE>;
547 status = "disabled";
548 };
549
550 ssi1: ssi@83fcc000 {
551 #sound-dai-cells = <0>;
552 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
553 reg = <0x83fcc000 0x4000>;
554 interrupts = <29>;
555 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
556 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
557 clock-names = "ipg", "baud";
558 dmas = <&sdma 28 0 0>,
559 <&sdma 29 0 0>;
560 dma-names = "rx", "tx";
561 fsl,fifo-depth = <15>;
562 status = "disabled";
563 };
564
565 audmux: audmux@83fd0000 {
566 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
567 reg = <0x83fd0000 0x4000>;
568 clocks = <&clks IMX5_CLK_DUMMY>;
569 clock-names = "audmux";
570 status = "disabled";
571 };
572
573 m4if: m4if@83fd8000 {
574 compatible = "fsl,imx51-m4if";
575 reg = <0x83fd8000 0x1000>;
576 };
577
578 weim: weim@83fda000 {
579 #address-cells = <2>;
580 #size-cells = <1>;
581 compatible = "fsl,imx51-weim";
582 reg = <0x83fda000 0x1000>;
583 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
584 ranges = <
585 0 0 0xb0000000 0x08000000
586 1 0 0xb8000000 0x08000000
587 2 0 0xc0000000 0x08000000
588 3 0 0xc8000000 0x04000000
589 4 0 0xcc000000 0x02000000
590 5 0 0xce000000 0x02000000
591 >;
592 status = "disabled";
593 };
594
595 nfc: nand@83fdb000 {
596 #address-cells = <1>;
597 #size-cells = <1>;
598 compatible = "fsl,imx51-nand";
599 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
600 interrupts = <8>;
601 clocks = <&clks IMX5_CLK_NFC_GATE>;
602 status = "disabled";
603 };
604
605 pata: pata@83fe0000 {
606 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
607 reg = <0x83fe0000 0x4000>;
608 interrupts = <70>;
609 clocks = <&clks IMX5_CLK_PATA_GATE>;
610 status = "disabled";
611 };
612
613 ssi3: ssi@83fe8000 {
614 #sound-dai-cells = <0>;
615 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
616 reg = <0x83fe8000 0x4000>;
617 interrupts = <96>;
618 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
619 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
620 clock-names = "ipg", "baud";
621 dmas = <&sdma 46 0 0>,
622 <&sdma 47 0 0>;
623 dma-names = "rx", "tx";
624 fsl,fifo-depth = <15>;
625 status = "disabled";
626 };
627
628 fec: ethernet@83fec000 {
629 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
630 reg = <0x83fec000 0x4000>;
631 interrupts = <87>;
632 clocks = <&clks IMX5_CLK_FEC_GATE>,
633 <&clks IMX5_CLK_FEC_GATE>,
634 <&clks IMX5_CLK_FEC_GATE>;
635 clock-names = "ipg", "ahb", "ptp";
636 status = "disabled";
637 };
638
639 vpu: vpu@83ff4000 {
640 compatible = "fsl,imx51-vpu", "cnm,codahx4";
641 reg = <0x83ff4000 0x1000>;
642 interrupts = <9>;
643 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
644 <&clks IMX5_CLK_VPU_GATE>;
645 clock-names = "per", "ahb";
646 resets = <&src 1>;
647 iram = <&iram>;
648 };
649
650 sahara: crypto@83ff8000 {
651 compatible = "fsl,imx53-sahara", "fsl,imx51-sahara";
652 reg = <0x83ff8000 0x4000>;
653 interrupts = <19 20>;
654 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
655 <&clks IMX5_CLK_SAHARA_IPG_GATE>;
656 clock-names = "ipg", "ahb";
657 };
658 };
659 };
660};
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 };
21
22 tzic: tz-interrupt-controller@e0000000 {
23 compatible = "fsl,imx51-tzic", "fsl,tzic";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 reg = <0xe0000000 0x4000>;
27 };
28
29 clocks {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 ckil {
34 compatible = "fsl,imx-ckil", "fixed-clock";
35 clock-frequency = <32768>;
36 };
37
38 ckih1 {
39 compatible = "fsl,imx-ckih1", "fixed-clock";
40 clock-frequency = <22579200>;
41 };
42
43 ckih2 {
44 compatible = "fsl,imx-ckih2", "fixed-clock";
45 clock-frequency = <0>;
46 };
47
48 osc {
49 compatible = "fsl,imx-osc", "fixed-clock";
50 clock-frequency = <24000000>;
51 };
52 };
53
54 soc {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "simple-bus";
58 interrupt-parent = <&tzic>;
59 ranges;
60
61 aips@70000000 { /* AIPS1 */
62 compatible = "fsl,aips-bus", "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x70000000 0x10000000>;
66 ranges;
67
68 spba@70000000 {
69 compatible = "fsl,spba-bus", "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x70000000 0x40000>;
73 ranges;
74
75 esdhc@70004000 { /* ESDHC1 */
76 compatible = "fsl,imx51-esdhc";
77 reg = <0x70004000 0x4000>;
78 interrupts = <1>;
79 status = "disabled";
80 };
81
82 esdhc@70008000 { /* ESDHC2 */
83 compatible = "fsl,imx51-esdhc";
84 reg = <0x70008000 0x4000>;
85 interrupts = <2>;
86 status = "disabled";
87 };
88
89 uart3: serial@7000c000 {
90 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
91 reg = <0x7000c000 0x4000>;
92 interrupts = <33>;
93 status = "disabled";
94 };
95
96 ecspi@70010000 { /* ECSPI1 */
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "fsl,imx51-ecspi";
100 reg = <0x70010000 0x4000>;
101 interrupts = <36>;
102 status = "disabled";
103 };
104
105 ssi2: ssi@70014000 {
106 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
107 reg = <0x70014000 0x4000>;
108 interrupts = <30>;
109 fsl,fifo-depth = <15>;
110 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
111 status = "disabled";
112 };
113
114 esdhc@70020000 { /* ESDHC3 */
115 compatible = "fsl,imx51-esdhc";
116 reg = <0x70020000 0x4000>;
117 interrupts = <3>;
118 status = "disabled";
119 };
120
121 esdhc@70024000 { /* ESDHC4 */
122 compatible = "fsl,imx51-esdhc";
123 reg = <0x70024000 0x4000>;
124 interrupts = <4>;
125 status = "disabled";
126 };
127 };
128
129 gpio1: gpio@73f84000 {
130 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
131 reg = <0x73f84000 0x4000>;
132 interrupts = <50 51>;
133 gpio-controller;
134 #gpio-cells = <2>;
135 interrupt-controller;
136 #interrupt-cells = <1>;
137 };
138
139 gpio2: gpio@73f88000 {
140 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
141 reg = <0x73f88000 0x4000>;
142 interrupts = <52 53>;
143 gpio-controller;
144 #gpio-cells = <2>;
145 interrupt-controller;
146 #interrupt-cells = <1>;
147 };
148
149 gpio3: gpio@73f8c000 {
150 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
151 reg = <0x73f8c000 0x4000>;
152 interrupts = <54 55>;
153 gpio-controller;
154 #gpio-cells = <2>;
155 interrupt-controller;
156 #interrupt-cells = <1>;
157 };
158
159 gpio4: gpio@73f90000 {
160 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
161 reg = <0x73f90000 0x4000>;
162 interrupts = <56 57>;
163 gpio-controller;
164 #gpio-cells = <2>;
165 interrupt-controller;
166 #interrupt-cells = <1>;
167 };
168
169 wdog@73f98000 { /* WDOG1 */
170 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
171 reg = <0x73f98000 0x4000>;
172 interrupts = <58>;
173 status = "disabled";
174 };
175
176 wdog@73f9c000 { /* WDOG2 */
177 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
178 reg = <0x73f9c000 0x4000>;
179 interrupts = <59>;
180 status = "disabled";
181 };
182
183 uart1: serial@73fbc000 {
184 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
185 reg = <0x73fbc000 0x4000>;
186 interrupts = <31>;
187 status = "disabled";
188 };
189
190 uart2: serial@73fc0000 {
191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
192 reg = <0x73fc0000 0x4000>;
193 interrupts = <32>;
194 status = "disabled";
195 };
196 };
197
198 aips@80000000 { /* AIPS2 */
199 compatible = "fsl,aips-bus", "simple-bus";
200 #address-cells = <1>;
201 #size-cells = <1>;
202 reg = <0x80000000 0x10000000>;
203 ranges;
204
205 ecspi@83fac000 { /* ECSPI2 */
206 #address-cells = <1>;
207 #size-cells = <0>;
208 compatible = "fsl,imx51-ecspi";
209 reg = <0x83fac000 0x4000>;
210 interrupts = <37>;
211 status = "disabled";
212 };
213
214 sdma@83fb0000 {
215 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
216 reg = <0x83fb0000 0x4000>;
217 interrupts = <6>;
218 };
219
220 cspi@83fc0000 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
224 reg = <0x83fc0000 0x4000>;
225 interrupts = <38>;
226 status = "disabled";
227 };
228
229 i2c@83fc4000 { /* I2C2 */
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
233 reg = <0x83fc4000 0x4000>;
234 interrupts = <63>;
235 status = "disabled";
236 };
237
238 i2c@83fc8000 { /* I2C1 */
239 #address-cells = <1>;
240 #size-cells = <0>;
241 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
242 reg = <0x83fc8000 0x4000>;
243 interrupts = <62>;
244 status = "disabled";
245 };
246
247 ssi1: ssi@83fcc000 {
248 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
249 reg = <0x83fcc000 0x4000>;
250 interrupts = <29>;
251 fsl,fifo-depth = <15>;
252 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
253 status = "disabled";
254 };
255
256 audmux@83fd0000 {
257 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
258 reg = <0x83fd0000 0x4000>;
259 status = "disabled";
260 };
261
262 ssi3: ssi@83fe8000 {
263 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
264 reg = <0x83fe8000 0x4000>;
265 interrupts = <96>;
266 fsl,fifo-depth = <15>;
267 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
268 status = "disabled";
269 };
270
271 ethernet@83fec000 {
272 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
273 reg = <0x83fec000 0x4000>;
274 interrupts = <87>;
275 status = "disabled";
276 };
277 };
278 };
279};