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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * IOMMU API for Graphics Address Relocation Table on Tegra20
4 *
5 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
6 *
7 * Author: Hiroshi DOYU <hdoyu@nvidia.com>
8 */
9
10#define dev_fmt(fmt) "gart: " fmt
11
12#include <linux/io.h>
13#include <linux/iommu.h>
14#include <linux/moduleparam.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18#include <linux/vmalloc.h>
19
20#include <soc/tegra/mc.h>
21
22#define GART_REG_BASE 0x24
23#define GART_CONFIG (0x24 - GART_REG_BASE)
24#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
25#define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
26
27#define GART_ENTRY_PHYS_ADDR_VALID BIT(31)
28
29#define GART_PAGE_SHIFT 12
30#define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT)
31#define GART_PAGE_MASK GENMASK(30, GART_PAGE_SHIFT)
32
33/* bitmap of the page sizes currently supported */
34#define GART_IOMMU_PGSIZES (GART_PAGE_SIZE)
35
36struct gart_device {
37 void __iomem *regs;
38 u32 *savedata;
39 unsigned long iovmm_base; /* offset to vmm_area start */
40 unsigned long iovmm_end; /* offset to vmm_area end */
41 spinlock_t pte_lock; /* for pagetable */
42 spinlock_t dom_lock; /* for active domain */
43 unsigned int active_devices; /* number of active devices */
44 struct iommu_domain *active_domain; /* current active domain */
45 struct iommu_device iommu; /* IOMMU Core handle */
46 struct device *dev;
47};
48
49static struct gart_device *gart_handle; /* unique for a system */
50
51static bool gart_debug;
52
53/*
54 * Any interaction between any block on PPSB and a block on APB or AHB
55 * must have these read-back to ensure the APB/AHB bus transaction is
56 * complete before initiating activity on the PPSB block.
57 */
58#define FLUSH_GART_REGS(gart) readl_relaxed((gart)->regs + GART_CONFIG)
59
60#define for_each_gart_pte(gart, iova) \
61 for (iova = gart->iovmm_base; \
62 iova < gart->iovmm_end; \
63 iova += GART_PAGE_SIZE)
64
65static inline void gart_set_pte(struct gart_device *gart,
66 unsigned long iova, unsigned long pte)
67{
68 writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR);
69 writel_relaxed(pte, gart->regs + GART_ENTRY_DATA);
70}
71
72static inline unsigned long gart_read_pte(struct gart_device *gart,
73 unsigned long iova)
74{
75 unsigned long pte;
76
77 writel_relaxed(iova, gart->regs + GART_ENTRY_ADDR);
78 pte = readl_relaxed(gart->regs + GART_ENTRY_DATA);
79
80 return pte;
81}
82
83static void do_gart_setup(struct gart_device *gart, const u32 *data)
84{
85 unsigned long iova;
86
87 for_each_gart_pte(gart, iova)
88 gart_set_pte(gart, iova, data ? *(data++) : 0);
89
90 writel_relaxed(1, gart->regs + GART_CONFIG);
91 FLUSH_GART_REGS(gart);
92}
93
94static inline bool gart_iova_range_invalid(struct gart_device *gart,
95 unsigned long iova, size_t bytes)
96{
97 return unlikely(iova < gart->iovmm_base || bytes != GART_PAGE_SIZE ||
98 iova + bytes > gart->iovmm_end);
99}
100
101static inline bool gart_pte_valid(struct gart_device *gart, unsigned long iova)
102{
103 return !!(gart_read_pte(gart, iova) & GART_ENTRY_PHYS_ADDR_VALID);
104}
105
106static int gart_iommu_attach_dev(struct iommu_domain *domain,
107 struct device *dev)
108{
109 struct gart_device *gart = gart_handle;
110 int ret = 0;
111
112 spin_lock(&gart->dom_lock);
113
114 if (gart->active_domain && gart->active_domain != domain) {
115 ret = -EINVAL;
116 } else if (dev_iommu_priv_get(dev) != domain) {
117 dev_iommu_priv_set(dev, domain);
118 gart->active_domain = domain;
119 gart->active_devices++;
120 }
121
122 spin_unlock(&gart->dom_lock);
123
124 return ret;
125}
126
127static void gart_iommu_detach_dev(struct iommu_domain *domain,
128 struct device *dev)
129{
130 struct gart_device *gart = gart_handle;
131
132 spin_lock(&gart->dom_lock);
133
134 if (dev_iommu_priv_get(dev) == domain) {
135 dev_iommu_priv_set(dev, NULL);
136
137 if (--gart->active_devices == 0)
138 gart->active_domain = NULL;
139 }
140
141 spin_unlock(&gart->dom_lock);
142}
143
144static struct iommu_domain *gart_iommu_domain_alloc(unsigned type)
145{
146 struct iommu_domain *domain;
147
148 if (type != IOMMU_DOMAIN_UNMANAGED)
149 return NULL;
150
151 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
152 if (domain) {
153 domain->geometry.aperture_start = gart_handle->iovmm_base;
154 domain->geometry.aperture_end = gart_handle->iovmm_end - 1;
155 domain->geometry.force_aperture = true;
156 }
157
158 return domain;
159}
160
161static void gart_iommu_domain_free(struct iommu_domain *domain)
162{
163 WARN_ON(gart_handle->active_domain == domain);
164 kfree(domain);
165}
166
167static inline int __gart_iommu_map(struct gart_device *gart, unsigned long iova,
168 unsigned long pa)
169{
170 if (unlikely(gart_debug && gart_pte_valid(gart, iova))) {
171 dev_err(gart->dev, "Page entry is in-use\n");
172 return -EINVAL;
173 }
174
175 gart_set_pte(gart, iova, GART_ENTRY_PHYS_ADDR_VALID | pa);
176
177 return 0;
178}
179
180static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
181 phys_addr_t pa, size_t bytes, int prot, gfp_t gfp)
182{
183 struct gart_device *gart = gart_handle;
184 int ret;
185
186 if (gart_iova_range_invalid(gart, iova, bytes))
187 return -EINVAL;
188
189 spin_lock(&gart->pte_lock);
190 ret = __gart_iommu_map(gart, iova, (unsigned long)pa);
191 spin_unlock(&gart->pte_lock);
192
193 return ret;
194}
195
196static inline int __gart_iommu_unmap(struct gart_device *gart,
197 unsigned long iova)
198{
199 if (unlikely(gart_debug && !gart_pte_valid(gart, iova))) {
200 dev_err(gart->dev, "Page entry is invalid\n");
201 return -EINVAL;
202 }
203
204 gart_set_pte(gart, iova, 0);
205
206 return 0;
207}
208
209static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
210 size_t bytes, struct iommu_iotlb_gather *gather)
211{
212 struct gart_device *gart = gart_handle;
213 int err;
214
215 if (gart_iova_range_invalid(gart, iova, bytes))
216 return 0;
217
218 spin_lock(&gart->pte_lock);
219 err = __gart_iommu_unmap(gart, iova);
220 spin_unlock(&gart->pte_lock);
221
222 return err ? 0 : bytes;
223}
224
225static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
226 dma_addr_t iova)
227{
228 struct gart_device *gart = gart_handle;
229 unsigned long pte;
230
231 if (gart_iova_range_invalid(gart, iova, GART_PAGE_SIZE))
232 return -EINVAL;
233
234 spin_lock(&gart->pte_lock);
235 pte = gart_read_pte(gart, iova);
236 spin_unlock(&gart->pte_lock);
237
238 return pte & GART_PAGE_MASK;
239}
240
241static struct iommu_device *gart_iommu_probe_device(struct device *dev)
242{
243 if (!dev_iommu_fwspec_get(dev))
244 return ERR_PTR(-ENODEV);
245
246 return &gart_handle->iommu;
247}
248
249static int gart_iommu_of_xlate(struct device *dev,
250 struct of_phandle_args *args)
251{
252 return 0;
253}
254
255static void gart_iommu_sync_map(struct iommu_domain *domain, unsigned long iova,
256 size_t size)
257{
258 FLUSH_GART_REGS(gart_handle);
259}
260
261static void gart_iommu_sync(struct iommu_domain *domain,
262 struct iommu_iotlb_gather *gather)
263{
264 size_t length = gather->end - gather->start + 1;
265
266 gart_iommu_sync_map(domain, gather->start, length);
267}
268
269static const struct iommu_ops gart_iommu_ops = {
270 .domain_alloc = gart_iommu_domain_alloc,
271 .probe_device = gart_iommu_probe_device,
272 .device_group = generic_device_group,
273 .pgsize_bitmap = GART_IOMMU_PGSIZES,
274 .of_xlate = gart_iommu_of_xlate,
275 .default_domain_ops = &(const struct iommu_domain_ops) {
276 .attach_dev = gart_iommu_attach_dev,
277 .detach_dev = gart_iommu_detach_dev,
278 .map = gart_iommu_map,
279 .unmap = gart_iommu_unmap,
280 .iova_to_phys = gart_iommu_iova_to_phys,
281 .iotlb_sync_map = gart_iommu_sync_map,
282 .iotlb_sync = gart_iommu_sync,
283 .free = gart_iommu_domain_free,
284 }
285};
286
287int tegra_gart_suspend(struct gart_device *gart)
288{
289 u32 *data = gart->savedata;
290 unsigned long iova;
291
292 /*
293 * All GART users shall be suspended at this point. Disable
294 * address translation to trap all GART accesses as invalid
295 * memory accesses.
296 */
297 writel_relaxed(0, gart->regs + GART_CONFIG);
298 FLUSH_GART_REGS(gart);
299
300 for_each_gart_pte(gart, iova)
301 *(data++) = gart_read_pte(gart, iova);
302
303 return 0;
304}
305
306int tegra_gart_resume(struct gart_device *gart)
307{
308 do_gart_setup(gart, gart->savedata);
309
310 return 0;
311}
312
313struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
314{
315 struct gart_device *gart;
316 struct resource *res;
317 int err;
318
319 BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
320
321 /* the GART memory aperture is required */
322 res = platform_get_resource(to_platform_device(dev), IORESOURCE_MEM, 1);
323 if (!res) {
324 dev_err(dev, "Memory aperture resource unavailable\n");
325 return ERR_PTR(-ENXIO);
326 }
327
328 gart = kzalloc(sizeof(*gart), GFP_KERNEL);
329 if (!gart)
330 return ERR_PTR(-ENOMEM);
331
332 gart_handle = gart;
333
334 gart->dev = dev;
335 gart->regs = mc->regs + GART_REG_BASE;
336 gart->iovmm_base = res->start;
337 gart->iovmm_end = res->end + 1;
338 spin_lock_init(&gart->pte_lock);
339 spin_lock_init(&gart->dom_lock);
340
341 do_gart_setup(gart, NULL);
342
343 err = iommu_device_sysfs_add(&gart->iommu, dev, NULL, "gart");
344 if (err)
345 goto free_gart;
346
347 err = iommu_device_register(&gart->iommu, &gart_iommu_ops, dev);
348 if (err)
349 goto remove_sysfs;
350
351 gart->savedata = vmalloc(resource_size(res) / GART_PAGE_SIZE *
352 sizeof(u32));
353 if (!gart->savedata) {
354 err = -ENOMEM;
355 goto unregister_iommu;
356 }
357
358 return gart;
359
360unregister_iommu:
361 iommu_device_unregister(&gart->iommu);
362remove_sysfs:
363 iommu_device_sysfs_remove(&gart->iommu);
364free_gart:
365 kfree(gart);
366
367 return ERR_PTR(err);
368}
369
370module_param(gart_debug, bool, 0644);
371MODULE_PARM_DESC(gart_debug, "Enable GART debugging");
1/*
2 * IOMMU API for GART in Tegra20
3 *
4 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#define pr_fmt(fmt) "%s(): " fmt, __func__
21
22#include <linux/module.h>
23#include <linux/platform_device.h>
24#include <linux/spinlock.h>
25#include <linux/slab.h>
26#include <linux/vmalloc.h>
27#include <linux/mm.h>
28#include <linux/list.h>
29#include <linux/device.h>
30#include <linux/io.h>
31#include <linux/iommu.h>
32#include <linux/of.h>
33
34#include <asm/cacheflush.h>
35
36/* bitmap of the page sizes currently supported */
37#define GART_IOMMU_PGSIZES (SZ_4K)
38
39#define GART_REG_BASE 0x24
40#define GART_CONFIG (0x24 - GART_REG_BASE)
41#define GART_ENTRY_ADDR (0x28 - GART_REG_BASE)
42#define GART_ENTRY_DATA (0x2c - GART_REG_BASE)
43#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31)
44
45#define GART_PAGE_SHIFT 12
46#define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT)
47#define GART_PAGE_MASK \
48 (~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID)
49
50struct gart_client {
51 struct device *dev;
52 struct list_head list;
53};
54
55struct gart_device {
56 void __iomem *regs;
57 u32 *savedata;
58 u32 page_count; /* total remappable size */
59 dma_addr_t iovmm_base; /* offset to vmm_area */
60 spinlock_t pte_lock; /* for pagetable */
61 struct list_head client;
62 spinlock_t client_lock; /* for client list */
63 struct device *dev;
64};
65
66static struct gart_device *gart_handle; /* unique for a system */
67
68#define GART_PTE(_pfn) \
69 (GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT))
70
71/*
72 * Any interaction between any block on PPSB and a block on APB or AHB
73 * must have these read-back to ensure the APB/AHB bus transaction is
74 * complete before initiating activity on the PPSB block.
75 */
76#define FLUSH_GART_REGS(gart) ((void)readl((gart)->regs + GART_CONFIG))
77
78#define for_each_gart_pte(gart, iova) \
79 for (iova = gart->iovmm_base; \
80 iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \
81 iova += GART_PAGE_SIZE)
82
83static inline void gart_set_pte(struct gart_device *gart,
84 unsigned long offs, u32 pte)
85{
86 writel(offs, gart->regs + GART_ENTRY_ADDR);
87 writel(pte, gart->regs + GART_ENTRY_DATA);
88
89 dev_dbg(gart->dev, "%s %08lx:%08x\n",
90 pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK);
91}
92
93static inline unsigned long gart_read_pte(struct gart_device *gart,
94 unsigned long offs)
95{
96 unsigned long pte;
97
98 writel(offs, gart->regs + GART_ENTRY_ADDR);
99 pte = readl(gart->regs + GART_ENTRY_DATA);
100
101 return pte;
102}
103
104static void do_gart_setup(struct gart_device *gart, const u32 *data)
105{
106 unsigned long iova;
107
108 for_each_gart_pte(gart, iova)
109 gart_set_pte(gart, iova, data ? *(data++) : 0);
110
111 writel(1, gart->regs + GART_CONFIG);
112 FLUSH_GART_REGS(gart);
113}
114
115#ifdef DEBUG
116static void gart_dump_table(struct gart_device *gart)
117{
118 unsigned long iova;
119 unsigned long flags;
120
121 spin_lock_irqsave(&gart->pte_lock, flags);
122 for_each_gart_pte(gart, iova) {
123 unsigned long pte;
124
125 pte = gart_read_pte(gart, iova);
126
127 dev_dbg(gart->dev, "%s %08lx:%08lx\n",
128 (GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ",
129 iova, pte & GART_PAGE_MASK);
130 }
131 spin_unlock_irqrestore(&gart->pte_lock, flags);
132}
133#else
134static inline void gart_dump_table(struct gart_device *gart)
135{
136}
137#endif
138
139static inline bool gart_iova_range_valid(struct gart_device *gart,
140 unsigned long iova, size_t bytes)
141{
142 unsigned long iova_start, iova_end, gart_start, gart_end;
143
144 iova_start = iova;
145 iova_end = iova_start + bytes - 1;
146 gart_start = gart->iovmm_base;
147 gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1;
148
149 if (iova_start < gart_start)
150 return false;
151 if (iova_end > gart_end)
152 return false;
153 return true;
154}
155
156static int gart_iommu_attach_dev(struct iommu_domain *domain,
157 struct device *dev)
158{
159 struct gart_device *gart;
160 struct gart_client *client, *c;
161 int err = 0;
162
163 gart = gart_handle;
164 if (!gart)
165 return -EINVAL;
166 domain->priv = gart;
167
168 client = devm_kzalloc(gart->dev, sizeof(*c), GFP_KERNEL);
169 if (!client)
170 return -ENOMEM;
171 client->dev = dev;
172
173 spin_lock(&gart->client_lock);
174 list_for_each_entry(c, &gart->client, list) {
175 if (c->dev == dev) {
176 dev_err(gart->dev,
177 "%s is already attached\n", dev_name(dev));
178 err = -EINVAL;
179 goto fail;
180 }
181 }
182 list_add(&client->list, &gart->client);
183 spin_unlock(&gart->client_lock);
184 dev_dbg(gart->dev, "Attached %s\n", dev_name(dev));
185 return 0;
186
187fail:
188 devm_kfree(gart->dev, client);
189 spin_unlock(&gart->client_lock);
190 return err;
191}
192
193static void gart_iommu_detach_dev(struct iommu_domain *domain,
194 struct device *dev)
195{
196 struct gart_device *gart = domain->priv;
197 struct gart_client *c;
198
199 spin_lock(&gart->client_lock);
200
201 list_for_each_entry(c, &gart->client, list) {
202 if (c->dev == dev) {
203 list_del(&c->list);
204 devm_kfree(gart->dev, c);
205 dev_dbg(gart->dev, "Detached %s\n", dev_name(dev));
206 goto out;
207 }
208 }
209 dev_err(gart->dev, "Couldn't find\n");
210out:
211 spin_unlock(&gart->client_lock);
212}
213
214static int gart_iommu_domain_init(struct iommu_domain *domain)
215{
216 return 0;
217}
218
219static void gart_iommu_domain_destroy(struct iommu_domain *domain)
220{
221 struct gart_device *gart = domain->priv;
222
223 if (!gart)
224 return;
225
226 spin_lock(&gart->client_lock);
227 if (!list_empty(&gart->client)) {
228 struct gart_client *c;
229
230 list_for_each_entry(c, &gart->client, list)
231 gart_iommu_detach_dev(domain, c->dev);
232 }
233 spin_unlock(&gart->client_lock);
234 domain->priv = NULL;
235}
236
237static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
238 phys_addr_t pa, size_t bytes, int prot)
239{
240 struct gart_device *gart = domain->priv;
241 unsigned long flags;
242 unsigned long pfn;
243
244 if (!gart_iova_range_valid(gart, iova, bytes))
245 return -EINVAL;
246
247 spin_lock_irqsave(&gart->pte_lock, flags);
248 pfn = __phys_to_pfn(pa);
249 if (!pfn_valid(pfn)) {
250 dev_err(gart->dev, "Invalid page: %08x\n", pa);
251 spin_unlock_irqrestore(&gart->pte_lock, flags);
252 return -EINVAL;
253 }
254 gart_set_pte(gart, iova, GART_PTE(pfn));
255 FLUSH_GART_REGS(gart);
256 spin_unlock_irqrestore(&gart->pte_lock, flags);
257 return 0;
258}
259
260static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
261 size_t bytes)
262{
263 struct gart_device *gart = domain->priv;
264 unsigned long flags;
265
266 if (!gart_iova_range_valid(gart, iova, bytes))
267 return 0;
268
269 spin_lock_irqsave(&gart->pte_lock, flags);
270 gart_set_pte(gart, iova, 0);
271 FLUSH_GART_REGS(gart);
272 spin_unlock_irqrestore(&gart->pte_lock, flags);
273 return 0;
274}
275
276static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
277 unsigned long iova)
278{
279 struct gart_device *gart = domain->priv;
280 unsigned long pte;
281 phys_addr_t pa;
282 unsigned long flags;
283
284 if (!gart_iova_range_valid(gart, iova, 0))
285 return -EINVAL;
286
287 spin_lock_irqsave(&gart->pte_lock, flags);
288 pte = gart_read_pte(gart, iova);
289 spin_unlock_irqrestore(&gart->pte_lock, flags);
290
291 pa = (pte & GART_PAGE_MASK);
292 if (!pfn_valid(__phys_to_pfn(pa))) {
293 dev_err(gart->dev, "No entry for %08lx:%08x\n", iova, pa);
294 gart_dump_table(gart);
295 return -EINVAL;
296 }
297 return pa;
298}
299
300static int gart_iommu_domain_has_cap(struct iommu_domain *domain,
301 unsigned long cap)
302{
303 return 0;
304}
305
306static struct iommu_ops gart_iommu_ops = {
307 .domain_init = gart_iommu_domain_init,
308 .domain_destroy = gart_iommu_domain_destroy,
309 .attach_dev = gart_iommu_attach_dev,
310 .detach_dev = gart_iommu_detach_dev,
311 .map = gart_iommu_map,
312 .unmap = gart_iommu_unmap,
313 .iova_to_phys = gart_iommu_iova_to_phys,
314 .domain_has_cap = gart_iommu_domain_has_cap,
315 .pgsize_bitmap = GART_IOMMU_PGSIZES,
316};
317
318static int tegra_gart_suspend(struct device *dev)
319{
320 struct gart_device *gart = dev_get_drvdata(dev);
321 unsigned long iova;
322 u32 *data = gart->savedata;
323 unsigned long flags;
324
325 spin_lock_irqsave(&gart->pte_lock, flags);
326 for_each_gart_pte(gart, iova)
327 *(data++) = gart_read_pte(gart, iova);
328 spin_unlock_irqrestore(&gart->pte_lock, flags);
329 return 0;
330}
331
332static int tegra_gart_resume(struct device *dev)
333{
334 struct gart_device *gart = dev_get_drvdata(dev);
335 unsigned long flags;
336
337 spin_lock_irqsave(&gart->pte_lock, flags);
338 do_gart_setup(gart, gart->savedata);
339 spin_unlock_irqrestore(&gart->pte_lock, flags);
340 return 0;
341}
342
343static int tegra_gart_probe(struct platform_device *pdev)
344{
345 struct gart_device *gart;
346 struct resource *res, *res_remap;
347 void __iomem *gart_regs;
348 int err;
349 struct device *dev = &pdev->dev;
350
351 if (gart_handle)
352 return -EIO;
353
354 BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
355
356 /* the GART memory aperture is required */
357 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
358 res_remap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
359 if (!res || !res_remap) {
360 dev_err(dev, "GART memory aperture expected\n");
361 return -ENXIO;
362 }
363
364 gart = devm_kzalloc(dev, sizeof(*gart), GFP_KERNEL);
365 if (!gart) {
366 dev_err(dev, "failed to allocate gart_device\n");
367 return -ENOMEM;
368 }
369
370 gart_regs = devm_ioremap(dev, res->start, resource_size(res));
371 if (!gart_regs) {
372 dev_err(dev, "failed to remap GART registers\n");
373 err = -ENXIO;
374 goto fail;
375 }
376
377 gart->dev = &pdev->dev;
378 spin_lock_init(&gart->pte_lock);
379 spin_lock_init(&gart->client_lock);
380 INIT_LIST_HEAD(&gart->client);
381 gart->regs = gart_regs;
382 gart->iovmm_base = (dma_addr_t)res_remap->start;
383 gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT);
384
385 gart->savedata = vmalloc(sizeof(u32) * gart->page_count);
386 if (!gart->savedata) {
387 dev_err(dev, "failed to allocate context save area\n");
388 err = -ENOMEM;
389 goto fail;
390 }
391
392 platform_set_drvdata(pdev, gart);
393 do_gart_setup(gart, NULL);
394
395 gart_handle = gart;
396 return 0;
397
398fail:
399 if (gart_regs)
400 devm_iounmap(dev, gart_regs);
401 if (gart && gart->savedata)
402 vfree(gart->savedata);
403 devm_kfree(dev, gart);
404 return err;
405}
406
407static int tegra_gart_remove(struct platform_device *pdev)
408{
409 struct gart_device *gart = platform_get_drvdata(pdev);
410 struct device *dev = gart->dev;
411
412 writel(0, gart->regs + GART_CONFIG);
413 if (gart->savedata)
414 vfree(gart->savedata);
415 if (gart->regs)
416 devm_iounmap(dev, gart->regs);
417 devm_kfree(dev, gart);
418 gart_handle = NULL;
419 return 0;
420}
421
422const struct dev_pm_ops tegra_gart_pm_ops = {
423 .suspend = tegra_gart_suspend,
424 .resume = tegra_gart_resume,
425};
426
427#ifdef CONFIG_OF
428static struct of_device_id tegra_gart_of_match[] __devinitdata = {
429 { .compatible = "nvidia,tegra20-gart", },
430 { },
431};
432MODULE_DEVICE_TABLE(of, tegra_gart_of_match);
433#endif
434
435static struct platform_driver tegra_gart_driver = {
436 .probe = tegra_gart_probe,
437 .remove = tegra_gart_remove,
438 .driver = {
439 .owner = THIS_MODULE,
440 .name = "tegra-gart",
441 .pm = &tegra_gart_pm_ops,
442 .of_match_table = of_match_ptr(tegra_gart_of_match),
443 },
444};
445
446static int __devinit tegra_gart_init(void)
447{
448 bus_set_iommu(&platform_bus_type, &gart_iommu_ops);
449 return platform_driver_register(&tegra_gart_driver);
450}
451
452static void __exit tegra_gart_exit(void)
453{
454 platform_driver_unregister(&tegra_gart_driver);
455}
456
457subsys_initcall(tegra_gart_init);
458module_exit(tegra_gart_exit);
459
460MODULE_DESCRIPTION("IOMMU API for GART in Tegra20");
461MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
462MODULE_ALIAS("platform:tegra-gart");
463MODULE_LICENSE("GPL v2");