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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Generic EP93xx GPIO handling
4 *
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
7 *
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/slab.h>
18#include <linux/gpio/driver.h>
19#include <linux/bitops.h>
20#include <linux/seq_file.h>
21
22#define EP93XX_GPIO_F_INT_STATUS 0x5c
23#define EP93XX_GPIO_A_INT_STATUS 0xa0
24#define EP93XX_GPIO_B_INT_STATUS 0xbc
25
26/* Maximum value for gpio line identifiers */
27#define EP93XX_GPIO_LINE_MAX 63
28
29/* Number of GPIO chips in EP93XX */
30#define EP93XX_GPIO_CHIP_NUM 8
31
32/* Maximum value for irq capable line identifiers */
33#define EP93XX_GPIO_LINE_MAX_IRQ 23
34
35#define EP93XX_GPIO_A_IRQ_BASE 64
36#define EP93XX_GPIO_B_IRQ_BASE 72
37/*
38 * Static mapping of GPIO bank F IRQS:
39 * F0..F7 (16..24) to irq 80..87.
40 */
41#define EP93XX_GPIO_F_IRQ_BASE 80
42
43struct ep93xx_gpio_irq_chip {
44 u8 irq_offset;
45 u8 int_unmasked;
46 u8 int_enabled;
47 u8 int_type1;
48 u8 int_type2;
49 u8 int_debounce;
50};
51
52struct ep93xx_gpio_chip {
53 struct gpio_chip gc;
54 struct ep93xx_gpio_irq_chip *eic;
55};
56
57struct ep93xx_gpio {
58 void __iomem *base;
59 struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
60};
61
62#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
63
64static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
65{
66 struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
67
68 return egc->eic;
69}
70
71/*************************************************************************
72 * Interrupt handling for EP93xx on-chip GPIOs
73 *************************************************************************/
74#define EP93XX_INT_TYPE1_OFFSET 0x00
75#define EP93XX_INT_TYPE2_OFFSET 0x04
76#define EP93XX_INT_EOI_OFFSET 0x08
77#define EP93XX_INT_EN_OFFSET 0x0c
78#define EP93XX_INT_STATUS_OFFSET 0x10
79#define EP93XX_INT_RAW_STATUS_OFFSET 0x14
80#define EP93XX_INT_DEBOUNCE_OFFSET 0x18
81
82static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
83 struct ep93xx_gpio_irq_chip *eic)
84{
85 writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
86
87 writeb_relaxed(eic->int_type2,
88 epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
89
90 writeb_relaxed(eic->int_type1,
91 epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
92
93 writeb_relaxed(eic->int_unmasked & eic->int_enabled,
94 epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
95}
96
97static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
98 unsigned int offset, bool enable)
99{
100 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
101 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
102 int port_mask = BIT(offset);
103
104 if (enable)
105 eic->int_debounce |= port_mask;
106 else
107 eic->int_debounce &= ~port_mask;
108
109 writeb(eic->int_debounce,
110 epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
111}
112
113static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
114{
115 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
116 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
117 struct irq_chip *irqchip = irq_desc_get_chip(desc);
118 unsigned long stat;
119 int offset;
120
121 chained_irq_enter(irqchip, desc);
122
123 /*
124 * Dispatch the IRQs to the irqdomain of each A and B
125 * gpiochip irqdomains depending on what has fired.
126 * The tricky part is that the IRQ line is shared
127 * between bank A and B and each has their own gpiochip.
128 */
129 stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
130 for_each_set_bit(offset, &stat, 8)
131 generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
132 offset);
133
134 stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
135 for_each_set_bit(offset, &stat, 8)
136 generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
137 offset);
138
139 chained_irq_exit(irqchip, desc);
140}
141
142static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
143{
144 /*
145 * map discontiguous hw irq range to continuous sw irq range:
146 *
147 * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
148 */
149 struct irq_chip *irqchip = irq_desc_get_chip(desc);
150 unsigned int irq = irq_desc_get_irq(desc);
151 int port_f_idx = (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */
152 int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
153
154 chained_irq_enter(irqchip, desc);
155 generic_handle_irq(gpio_irq);
156 chained_irq_exit(irqchip, desc);
157}
158
159static void ep93xx_gpio_irq_ack(struct irq_data *d)
160{
161 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
162 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
163 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
164 int port_mask = BIT(d->irq & 7);
165
166 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
167 eic->int_type2 ^= port_mask; /* switch edge direction */
168 ep93xx_gpio_update_int_params(epg, eic);
169 }
170
171 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
172}
173
174static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
175{
176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
177 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
178 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
179 int port_mask = BIT(d->irq & 7);
180
181 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
182 eic->int_type2 ^= port_mask; /* switch edge direction */
183
184 eic->int_unmasked &= ~port_mask;
185 ep93xx_gpio_update_int_params(epg, eic);
186
187 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
188 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
189}
190
191static void ep93xx_gpio_irq_mask(struct irq_data *d)
192{
193 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
194 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
195 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
196
197 eic->int_unmasked &= ~BIT(d->irq & 7);
198 ep93xx_gpio_update_int_params(epg, eic);
199 gpiochip_disable_irq(gc, irqd_to_hwirq(d));
200}
201
202static void ep93xx_gpio_irq_unmask(struct irq_data *d)
203{
204 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
205 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
206 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
207
208 gpiochip_enable_irq(gc, irqd_to_hwirq(d));
209 eic->int_unmasked |= BIT(d->irq & 7);
210 ep93xx_gpio_update_int_params(epg, eic);
211}
212
213/*
214 * gpio_int_type1 controls whether the interrupt is level (0) or
215 * edge (1) triggered, while gpio_int_type2 controls whether it
216 * triggers on low/falling (0) or high/rising (1).
217 */
218static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
219{
220 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
221 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
222 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
223 int offset = d->irq & 7;
224 int port_mask = BIT(offset);
225 irq_flow_handler_t handler;
226
227 gc->direction_input(gc, offset);
228
229 switch (type) {
230 case IRQ_TYPE_EDGE_RISING:
231 eic->int_type1 |= port_mask;
232 eic->int_type2 |= port_mask;
233 handler = handle_edge_irq;
234 break;
235 case IRQ_TYPE_EDGE_FALLING:
236 eic->int_type1 |= port_mask;
237 eic->int_type2 &= ~port_mask;
238 handler = handle_edge_irq;
239 break;
240 case IRQ_TYPE_LEVEL_HIGH:
241 eic->int_type1 &= ~port_mask;
242 eic->int_type2 |= port_mask;
243 handler = handle_level_irq;
244 break;
245 case IRQ_TYPE_LEVEL_LOW:
246 eic->int_type1 &= ~port_mask;
247 eic->int_type2 &= ~port_mask;
248 handler = handle_level_irq;
249 break;
250 case IRQ_TYPE_EDGE_BOTH:
251 eic->int_type1 |= port_mask;
252 /* set initial polarity based on current input level */
253 if (gc->get(gc, offset))
254 eic->int_type2 &= ~port_mask; /* falling */
255 else
256 eic->int_type2 |= port_mask; /* rising */
257 handler = handle_edge_irq;
258 break;
259 default:
260 return -EINVAL;
261 }
262
263 irq_set_handler_locked(d, handler);
264
265 eic->int_enabled |= port_mask;
266
267 ep93xx_gpio_update_int_params(epg, eic);
268
269 return 0;
270}
271
272/*************************************************************************
273 * gpiolib interface for EP93xx on-chip GPIOs
274 *************************************************************************/
275struct ep93xx_gpio_bank {
276 const char *label;
277 int data;
278 int dir;
279 int irq;
280 int base;
281 bool has_irq;
282 bool has_hierarchical_irq;
283 unsigned int irq_base;
284};
285
286#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
287 { \
288 .label = _label, \
289 .data = _data, \
290 .dir = _dir, \
291 .irq = _irq, \
292 .base = _base, \
293 .has_irq = _has_irq, \
294 .has_hierarchical_irq = _has_hier, \
295 .irq_base = _irq_base, \
296 }
297
298static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
299 /* Bank A has 8 IRQs */
300 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ_BASE),
301 /* Bank B has 8 IRQs */
302 EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ_BASE),
303 EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
304 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
305 EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
306 /* Bank F has 8 IRQs */
307 EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IRQ_BASE),
308 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
309 EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
310};
311
312static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
313 unsigned long config)
314{
315 u32 debounce;
316
317 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
318 return -ENOTSUPP;
319
320 debounce = pinconf_to_config_argument(config);
321 ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
322
323 return 0;
324}
325
326static void ep93xx_irq_print_chip(struct irq_data *data, struct seq_file *p)
327{
328 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
329
330 seq_printf(p, dev_name(gc->parent));
331}
332
333static const struct irq_chip gpio_eic_irq_chip = {
334 .name = "ep93xx-gpio-eic",
335 .irq_ack = ep93xx_gpio_irq_ack,
336 .irq_mask = ep93xx_gpio_irq_mask,
337 .irq_unmask = ep93xx_gpio_irq_unmask,
338 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
339 .irq_set_type = ep93xx_gpio_irq_type,
340 .irq_print_chip = ep93xx_irq_print_chip,
341 .flags = IRQCHIP_IMMUTABLE,
342 GPIOCHIP_IRQ_RESOURCE_HELPERS,
343};
344
345static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
346 struct platform_device *pdev,
347 struct ep93xx_gpio *epg,
348 struct ep93xx_gpio_bank *bank)
349{
350 void __iomem *data = epg->base + bank->data;
351 void __iomem *dir = epg->base + bank->dir;
352 struct gpio_chip *gc = &egc->gc;
353 struct device *dev = &pdev->dev;
354 struct gpio_irq_chip *girq;
355 int err;
356
357 err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
358 if (err)
359 return err;
360
361 gc->label = bank->label;
362 gc->base = bank->base;
363
364 girq = &gc->irq;
365 if (bank->has_irq || bank->has_hierarchical_irq) {
366 gc->set_config = ep93xx_gpio_set_config;
367 egc->eic = devm_kcalloc(dev, 1,
368 sizeof(*egc->eic),
369 GFP_KERNEL);
370 if (!egc->eic)
371 return -ENOMEM;
372 egc->eic->irq_offset = bank->irq;
373 gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
374 }
375
376 if (bank->has_irq) {
377 int ab_parent_irq = platform_get_irq(pdev, 0);
378
379 girq->parent_handler = ep93xx_gpio_ab_irq_handler;
380 girq->num_parents = 1;
381 girq->parents = devm_kcalloc(dev, girq->num_parents,
382 sizeof(*girq->parents),
383 GFP_KERNEL);
384 if (!girq->parents)
385 return -ENOMEM;
386 girq->default_type = IRQ_TYPE_NONE;
387 girq->handler = handle_level_irq;
388 girq->parents[0] = ab_parent_irq;
389 girq->first = bank->irq_base;
390 }
391
392 /* Only bank F has especially funky IRQ handling */
393 if (bank->has_hierarchical_irq) {
394 int gpio_irq;
395 int i;
396
397 /*
398 * FIXME: convert this to use hierarchical IRQ support!
399 * this requires fixing the root irqchip to be hierarchical.
400 */
401 girq->parent_handler = ep93xx_gpio_f_irq_handler;
402 girq->num_parents = 8;
403 girq->parents = devm_kcalloc(dev, girq->num_parents,
404 sizeof(*girq->parents),
405 GFP_KERNEL);
406 if (!girq->parents)
407 return -ENOMEM;
408 /* Pick resources 1..8 for these IRQs */
409 for (i = 0; i < girq->num_parents; i++) {
410 girq->parents[i] = platform_get_irq(pdev, i + 1);
411 gpio_irq = bank->irq_base + i;
412 irq_set_chip_data(gpio_irq, &epg->gc[5]);
413 irq_set_chip_and_handler(gpio_irq,
414 girq->chip,
415 handle_level_irq);
416 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
417 }
418 girq->default_type = IRQ_TYPE_NONE;
419 girq->handler = handle_level_irq;
420 girq->first = bank->irq_base;
421 }
422
423 return devm_gpiochip_add_data(dev, gc, epg);
424}
425
426static int ep93xx_gpio_probe(struct platform_device *pdev)
427{
428 struct ep93xx_gpio *epg;
429 int i;
430
431 epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
432 if (!epg)
433 return -ENOMEM;
434
435 epg->base = devm_platform_ioremap_resource(pdev, 0);
436 if (IS_ERR(epg->base))
437 return PTR_ERR(epg->base);
438
439 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
440 struct ep93xx_gpio_chip *gc = &epg->gc[i];
441 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
442
443 if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
444 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
445 bank->label);
446 }
447
448 return 0;
449}
450
451static struct platform_driver ep93xx_gpio_driver = {
452 .driver = {
453 .name = "gpio-ep93xx",
454 },
455 .probe = ep93xx_gpio_probe,
456};
457
458static int __init ep93xx_gpio_init(void)
459{
460 return platform_driver_register(&ep93xx_gpio_driver);
461}
462postcore_initcall(ep93xx_gpio_init);
463
464MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
465 "H Hartley Sweeten <hsweeten@visionengravers.com>");
466MODULE_DESCRIPTION("EP93XX GPIO driver");
467MODULE_LICENSE("GPL");
1/*
2 * Generic EP93xx GPIO handling
3 *
4 * Copyright (c) 2008 Ryan Mallon
5 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
6 *
7 * Based on code originally from:
8 * linux/arch/arm/mach-ep93xx/core.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/gpio.h>
20#include <linux/irq.h>
21#include <linux/slab.h>
22#include <linux/basic_mmio_gpio.h>
23
24#include <mach/hardware.h>
25#include <mach/gpio-ep93xx.h>
26
27#define irq_to_gpio(irq) ((irq) - gpio_to_irq(0))
28
29struct ep93xx_gpio {
30 void __iomem *mmio_base;
31 struct bgpio_chip bgc[8];
32};
33
34/*************************************************************************
35 * Interrupt handling for EP93xx on-chip GPIOs
36 *************************************************************************/
37static unsigned char gpio_int_unmasked[3];
38static unsigned char gpio_int_enabled[3];
39static unsigned char gpio_int_type1[3];
40static unsigned char gpio_int_type2[3];
41static unsigned char gpio_int_debounce[3];
42
43/* Port ordering is: A B F */
44static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
45static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
46static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
47static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
48static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
49
50static void ep93xx_gpio_update_int_params(unsigned port)
51{
52 BUG_ON(port > 2);
53
54 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
55
56 __raw_writeb(gpio_int_type2[port],
57 EP93XX_GPIO_REG(int_type2_register_offset[port]));
58
59 __raw_writeb(gpio_int_type1[port],
60 EP93XX_GPIO_REG(int_type1_register_offset[port]));
61
62 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
63 EP93XX_GPIO_REG(int_en_register_offset[port]));
64}
65
66static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
67{
68 int line = irq_to_gpio(irq);
69 int port = line >> 3;
70 int port_mask = 1 << (line & 7);
71
72 if (enable)
73 gpio_int_debounce[port] |= port_mask;
74 else
75 gpio_int_debounce[port] &= ~port_mask;
76
77 __raw_writeb(gpio_int_debounce[port],
78 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
79}
80
81static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
82{
83 unsigned char status;
84 int i;
85
86 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
87 for (i = 0; i < 8; i++) {
88 if (status & (1 << i)) {
89 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
90 generic_handle_irq(gpio_irq);
91 }
92 }
93
94 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
95 for (i = 0; i < 8; i++) {
96 if (status & (1 << i)) {
97 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
98 generic_handle_irq(gpio_irq);
99 }
100 }
101}
102
103static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
104{
105 /*
106 * map discontiguous hw irq range to continuous sw irq range:
107 *
108 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
109 */
110 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
111 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
112
113 generic_handle_irq(gpio_irq);
114}
115
116static void ep93xx_gpio_irq_ack(struct irq_data *d)
117{
118 int line = irq_to_gpio(d->irq);
119 int port = line >> 3;
120 int port_mask = 1 << (line & 7);
121
122 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
123 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
124 ep93xx_gpio_update_int_params(port);
125 }
126
127 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
128}
129
130static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
131{
132 int line = irq_to_gpio(d->irq);
133 int port = line >> 3;
134 int port_mask = 1 << (line & 7);
135
136 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
137 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
138
139 gpio_int_unmasked[port] &= ~port_mask;
140 ep93xx_gpio_update_int_params(port);
141
142 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
143}
144
145static void ep93xx_gpio_irq_mask(struct irq_data *d)
146{
147 int line = irq_to_gpio(d->irq);
148 int port = line >> 3;
149
150 gpio_int_unmasked[port] &= ~(1 << (line & 7));
151 ep93xx_gpio_update_int_params(port);
152}
153
154static void ep93xx_gpio_irq_unmask(struct irq_data *d)
155{
156 int line = irq_to_gpio(d->irq);
157 int port = line >> 3;
158
159 gpio_int_unmasked[port] |= 1 << (line & 7);
160 ep93xx_gpio_update_int_params(port);
161}
162
163/*
164 * gpio_int_type1 controls whether the interrupt is level (0) or
165 * edge (1) triggered, while gpio_int_type2 controls whether it
166 * triggers on low/falling (0) or high/rising (1).
167 */
168static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
169{
170 const int gpio = irq_to_gpio(d->irq);
171 const int port = gpio >> 3;
172 const int port_mask = 1 << (gpio & 7);
173 irq_flow_handler_t handler;
174
175 gpio_direction_input(gpio);
176
177 switch (type) {
178 case IRQ_TYPE_EDGE_RISING:
179 gpio_int_type1[port] |= port_mask;
180 gpio_int_type2[port] |= port_mask;
181 handler = handle_edge_irq;
182 break;
183 case IRQ_TYPE_EDGE_FALLING:
184 gpio_int_type1[port] |= port_mask;
185 gpio_int_type2[port] &= ~port_mask;
186 handler = handle_edge_irq;
187 break;
188 case IRQ_TYPE_LEVEL_HIGH:
189 gpio_int_type1[port] &= ~port_mask;
190 gpio_int_type2[port] |= port_mask;
191 handler = handle_level_irq;
192 break;
193 case IRQ_TYPE_LEVEL_LOW:
194 gpio_int_type1[port] &= ~port_mask;
195 gpio_int_type2[port] &= ~port_mask;
196 handler = handle_level_irq;
197 break;
198 case IRQ_TYPE_EDGE_BOTH:
199 gpio_int_type1[port] |= port_mask;
200 /* set initial polarity based on current input level */
201 if (gpio_get_value(gpio))
202 gpio_int_type2[port] &= ~port_mask; /* falling */
203 else
204 gpio_int_type2[port] |= port_mask; /* rising */
205 handler = handle_edge_irq;
206 break;
207 default:
208 return -EINVAL;
209 }
210
211 __irq_set_handler_locked(d->irq, handler);
212
213 gpio_int_enabled[port] |= port_mask;
214
215 ep93xx_gpio_update_int_params(port);
216
217 return 0;
218}
219
220static struct irq_chip ep93xx_gpio_irq_chip = {
221 .name = "GPIO",
222 .irq_ack = ep93xx_gpio_irq_ack,
223 .irq_mask_ack = ep93xx_gpio_irq_mask_ack,
224 .irq_mask = ep93xx_gpio_irq_mask,
225 .irq_unmask = ep93xx_gpio_irq_unmask,
226 .irq_set_type = ep93xx_gpio_irq_type,
227};
228
229static void ep93xx_gpio_init_irq(void)
230{
231 int gpio_irq;
232
233 for (gpio_irq = gpio_to_irq(0);
234 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
235 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
236 handle_level_irq);
237 set_irq_flags(gpio_irq, IRQF_VALID);
238 }
239
240 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
241 ep93xx_gpio_ab_irq_handler);
242 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
243 ep93xx_gpio_f_irq_handler);
244 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
245 ep93xx_gpio_f_irq_handler);
246 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
247 ep93xx_gpio_f_irq_handler);
248 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
249 ep93xx_gpio_f_irq_handler);
250 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
251 ep93xx_gpio_f_irq_handler);
252 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
253 ep93xx_gpio_f_irq_handler);
254 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
255 ep93xx_gpio_f_irq_handler);
256 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
257 ep93xx_gpio_f_irq_handler);
258}
259
260
261/*************************************************************************
262 * gpiolib interface for EP93xx on-chip GPIOs
263 *************************************************************************/
264struct ep93xx_gpio_bank {
265 const char *label;
266 int data;
267 int dir;
268 int base;
269 bool has_debounce;
270};
271
272#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \
273 { \
274 .label = _label, \
275 .data = _data, \
276 .dir = _dir, \
277 .base = _base, \
278 .has_debounce = _debounce, \
279 }
280
281static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
282 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true),
283 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true),
284 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false),
285 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false),
286 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false),
287 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true),
288 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false),
289 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false),
290};
291
292static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
293 unsigned offset, unsigned debounce)
294{
295 int gpio = chip->base + offset;
296 int irq = gpio_to_irq(gpio);
297
298 if (irq < 0)
299 return -EINVAL;
300
301 ep93xx_gpio_int_debounce(irq, debounce ? true : false);
302
303 return 0;
304}
305
306/*
307 * Map GPIO A0..A7 (0..7) to irq 64..71,
308 * B0..B7 (7..15) to irq 72..79, and
309 * F0..F7 (16..24) to irq 80..87.
310 */
311static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
312{
313 int gpio = chip->base + offset;
314
315 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ)
316 return -EINVAL;
317
318 return 64 + gpio;
319}
320
321static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev,
322 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank)
323{
324 void __iomem *data = mmio_base + bank->data;
325 void __iomem *dir = mmio_base + bank->dir;
326 int err;
327
328 err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0);
329 if (err)
330 return err;
331
332 bgc->gc.label = bank->label;
333 bgc->gc.base = bank->base;
334
335 if (bank->has_debounce) {
336 bgc->gc.set_debounce = ep93xx_gpio_set_debounce;
337 bgc->gc.to_irq = ep93xx_gpio_to_irq;
338 }
339
340 return gpiochip_add(&bgc->gc);
341}
342
343static int __devinit ep93xx_gpio_probe(struct platform_device *pdev)
344{
345 struct ep93xx_gpio *ep93xx_gpio;
346 struct resource *res;
347 void __iomem *mmio;
348 int i;
349 int ret;
350
351 ep93xx_gpio = kzalloc(sizeof(*ep93xx_gpio), GFP_KERNEL);
352 if (!ep93xx_gpio)
353 return -ENOMEM;
354
355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
356 if (!res) {
357 ret = -ENXIO;
358 goto exit_free;
359 }
360
361 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
362 ret = -EBUSY;
363 goto exit_free;
364 }
365
366 mmio = ioremap(res->start, resource_size(res));
367 if (!mmio) {
368 ret = -ENXIO;
369 goto exit_release;
370 }
371 ep93xx_gpio->mmio_base = mmio;
372
373 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
374 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i];
375 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
376
377 if (ep93xx_gpio_add_bank(bgc, &pdev->dev, mmio, bank))
378 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
379 bank->label);
380 }
381
382 ep93xx_gpio_init_irq();
383
384 return 0;
385
386exit_release:
387 release_mem_region(res->start, resource_size(res));
388exit_free:
389 kfree(ep93xx_gpio);
390 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, ret);
391 return ret;
392}
393
394static struct platform_driver ep93xx_gpio_driver = {
395 .driver = {
396 .name = "gpio-ep93xx",
397 .owner = THIS_MODULE,
398 },
399 .probe = ep93xx_gpio_probe,
400};
401
402static int __init ep93xx_gpio_init(void)
403{
404 return platform_driver_register(&ep93xx_gpio_driver);
405}
406postcore_initcall(ep93xx_gpio_init);
407
408MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
409 "H Hartley Sweeten <hsweeten@visionengravers.com>");
410MODULE_DESCRIPTION("EP93XX GPIO driver");
411MODULE_LICENSE("GPL");