1#include <linux/gfp.h>
   2#include <linux/initrd.h>
   3#include <linux/ioport.h>
   4#include <linux/swap.h>
   5#include <linux/memblock.h>
   6#include <linux/swapfile.h>
   7#include <linux/swapops.h>
   8#include <linux/kmemleak.h>
   9#include <linux/sched/task.h>
  10
  11#include <asm/set_memory.h>
  12#include <asm/e820/api.h>
  13#include <asm/init.h>
  14#include <asm/page.h>
  15#include <asm/page_types.h>
  16#include <asm/sections.h>
  17#include <asm/setup.h>
  18#include <asm/tlbflush.h>
  19#include <asm/tlb.h>
  20#include <asm/proto.h>
  21#include <asm/dma.h>		/* for MAX_DMA_PFN */
  22#include <asm/microcode.h>
  23#include <asm/kaslr.h>
  24#include <asm/hypervisor.h>
  25#include <asm/cpufeature.h>
  26#include <asm/pti.h>
  27#include <asm/text-patching.h>
  28#include <asm/memtype.h>
  29#include <asm/paravirt.h>
  30
  31/*
  32 * We need to define the tracepoints somewhere, and tlb.c
  33 * is only compiled when SMP=y.
  34 */
  35#include <trace/events/tlb.h>
  36
  37#include "mm_internal.h"
  38
  39/*
  40 * Tables translating between page_cache_type_t and pte encoding.
  41 *
  42 * The default values are defined statically as minimal supported mode;
  43 * WC and WT fall back to UC-.  pat_init() updates these values to support
  44 * more cache modes, WC and WT, when it is safe to do so.  See pat_init()
  45 * for the details.  Note, __early_ioremap() used during early boot-time
  46 * takes pgprot_t (pte encoding) and does not use these tables.
  47 *
  48 *   Index into __cachemode2pte_tbl[] is the cachemode.
  49 *
  50 *   Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte
  51 *   (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.
  52 */
  53static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {
  54	[_PAGE_CACHE_MODE_WB      ]	= 0         | 0        ,
  55	[_PAGE_CACHE_MODE_WC      ]	= 0         | _PAGE_PCD,
  56	[_PAGE_CACHE_MODE_UC_MINUS]	= 0         | _PAGE_PCD,
  57	[_PAGE_CACHE_MODE_UC      ]	= _PAGE_PWT | _PAGE_PCD,
  58	[_PAGE_CACHE_MODE_WT      ]	= 0         | _PAGE_PCD,
  59	[_PAGE_CACHE_MODE_WP      ]	= 0         | _PAGE_PCD,
  60};
  61
  62unsigned long cachemode2protval(enum page_cache_mode pcm)
  63{
  64	if (likely(pcm == 0))
  65		return 0;
  66	return __cachemode2pte_tbl[pcm];
  67}
  68EXPORT_SYMBOL(cachemode2protval);
  69
  70static uint8_t __pte2cachemode_tbl[8] = {
  71	[__pte2cm_idx( 0        | 0         | 0        )] = _PAGE_CACHE_MODE_WB,
  72	[__pte2cm_idx(_PAGE_PWT | 0         | 0        )] = _PAGE_CACHE_MODE_UC_MINUS,
  73	[__pte2cm_idx( 0        | _PAGE_PCD | 0        )] = _PAGE_CACHE_MODE_UC_MINUS,
  74	[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | 0        )] = _PAGE_CACHE_MODE_UC,
  75	[__pte2cm_idx( 0        | 0         | _PAGE_PAT)] = _PAGE_CACHE_MODE_WB,
  76	[__pte2cm_idx(_PAGE_PWT | 0         | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
  77	[__pte2cm_idx(0         | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC_MINUS,
  78	[__pte2cm_idx(_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)] = _PAGE_CACHE_MODE_UC,
  79};
  80
  81/*
  82 * Check that the write-protect PAT entry is set for write-protect.
  83 * To do this without making assumptions how PAT has been set up (Xen has
  84 * another layout than the kernel), translate the _PAGE_CACHE_MODE_WP cache
  85 * mode via the __cachemode2pte_tbl[] into protection bits (those protection
  86 * bits will select a cache mode of WP or better), and then translate the
  87 * protection bits back into the cache mode using __pte2cm_idx() and the
  88 * __pte2cachemode_tbl[] array. This will return the really used cache mode.
  89 */
  90bool x86_has_pat_wp(void)
  91{
  92	uint16_t prot = __cachemode2pte_tbl[_PAGE_CACHE_MODE_WP];
  93
  94	return __pte2cachemode_tbl[__pte2cm_idx(prot)] == _PAGE_CACHE_MODE_WP;
  95}
  96
  97enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
  98{
  99	unsigned long masked;
 100
 101	masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
 102	if (likely(masked == 0))
 103		return 0;
 104	return __pte2cachemode_tbl[__pte2cm_idx(masked)];
 105}
 106
 107static unsigned long __initdata pgt_buf_start;
 108static unsigned long __initdata pgt_buf_end;
 109static unsigned long __initdata pgt_buf_top;
 110
 111static unsigned long min_pfn_mapped;
 112
 113static bool __initdata can_use_brk_pgt = true;
 114
 115/*
 116 * Pages returned are already directly mapped.
 117 *
 118 * Changing that is likely to break Xen, see commit:
 119 *
 120 *    279b706 x86,xen: introduce x86_init.mapping.pagetable_reserve
 121 *
 122 * for detailed information.
 123 */
 124__ref void *alloc_low_pages(unsigned int num)
 125{
 126	unsigned long pfn;
 127	int i;
 128
 129	if (after_bootmem) {
 130		unsigned int order;
 131
 132		order = get_order((unsigned long)num << PAGE_SHIFT);
 133		return (void *)__get_free_pages(GFP_ATOMIC | __GFP_ZERO, order);
 134	}
 135
 136	if ((pgt_buf_end + num) > pgt_buf_top || !can_use_brk_pgt) {
 137		unsigned long ret = 0;
 138
 139		if (min_pfn_mapped < max_pfn_mapped) {
 140			ret = memblock_phys_alloc_range(
 141					PAGE_SIZE * num, PAGE_SIZE,
 142					min_pfn_mapped << PAGE_SHIFT,
 143					max_pfn_mapped << PAGE_SHIFT);
 144		}
 145		if (!ret && can_use_brk_pgt)
 146			ret = __pa(extend_brk(PAGE_SIZE * num, PAGE_SIZE));
 147
 148		if (!ret)
 149			panic("alloc_low_pages: can not alloc memory");
 150
 151		pfn = ret >> PAGE_SHIFT;
 152	} else {
 153		pfn = pgt_buf_end;
 154		pgt_buf_end += num;
 155	}
 156
 157	for (i = 0; i < num; i++) {
 158		void *adr;
 159
 160		adr = __va((pfn + i) << PAGE_SHIFT);
 161		clear_page(adr);
 162	}
 163
 164	return __va(pfn << PAGE_SHIFT);
 165}
 
 
 
 
 
 166
 167/*
 168 * By default need to be able to allocate page tables below PGD firstly for
 169 * the 0-ISA_END_ADDRESS range and secondly for the initial PMD_SIZE mapping.
 170 * With KASLR memory randomization, depending on the machine e820 memory and the
 171 * PUD alignment, twice that many pages may be needed when KASLR memory
 172 * randomization is enabled.
 173 */
 174
 175#ifndef CONFIG_X86_5LEVEL
 176#define INIT_PGD_PAGE_TABLES    3
 177#else
 178#define INIT_PGD_PAGE_TABLES    4
 179#endif
 180
 181#ifndef CONFIG_RANDOMIZE_MEMORY
 182#define INIT_PGD_PAGE_COUNT      (2 * INIT_PGD_PAGE_TABLES)
 183#else
 184#define INIT_PGD_PAGE_COUNT      (4 * INIT_PGD_PAGE_TABLES)
 185#endif
 
 186
 187#define INIT_PGT_BUF_SIZE	(INIT_PGD_PAGE_COUNT * PAGE_SIZE)
 188RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE);
 189void  __init early_alloc_pgt_buf(void)
 190{
 191	unsigned long tables = INIT_PGT_BUF_SIZE;
 192	phys_addr_t base;
 193
 194	base = __pa(extend_brk(tables, PAGE_SIZE));
 195
 196	pgt_buf_start = base >> PAGE_SHIFT;
 197	pgt_buf_end = pgt_buf_start;
 198	pgt_buf_top = pgt_buf_start + (tables >> PAGE_SHIFT);
 199}
 200
 201int after_bootmem;
 202
 203early_param_on_off("gbpages", "nogbpages", direct_gbpages, CONFIG_X86_DIRECT_GBPAGES);
 204
 205struct map_range {
 206	unsigned long start;
 207	unsigned long end;
 208	unsigned page_size_mask;
 209};
 210
 211static int page_size_mask;
 212
 213/*
 214 * Save some of cr4 feature set we're using (e.g.  Pentium 4MB
 215 * enable and PPro Global page enable), so that any CPU's that boot
 216 * up after us can get the correct flags. Invoked on the boot CPU.
 217 */
 218static inline void cr4_set_bits_and_update_boot(unsigned long mask)
 219{
 220	mmu_cr4_features |= mask;
 221	if (trampoline_cr4_features)
 222		*trampoline_cr4_features = mmu_cr4_features;
 223	cr4_set_bits(mask);
 224}
 225
 226static void __init probe_page_size_mask(void)
 227{
 228	/*
 229	 * For pagealloc debugging, identity mapping will use small pages.
 230	 * This will simplify cpa(), which otherwise needs to support splitting
 231	 * large pages into small in interrupt context, etc.
 232	 */
 233	if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
 234		page_size_mask |= 1 << PG_LEVEL_2M;
 235	else
 236		direct_gbpages = 0;
 237
 238	/* Enable PSE if available */
 239	if (boot_cpu_has(X86_FEATURE_PSE))
 240		cr4_set_bits_and_update_boot(X86_CR4_PSE);
 241
 242	/* Enable PGE if available */
 243	__supported_pte_mask &= ~_PAGE_GLOBAL;
 244	if (boot_cpu_has(X86_FEATURE_PGE)) {
 245		cr4_set_bits_and_update_boot(X86_CR4_PGE);
 246		__supported_pte_mask |= _PAGE_GLOBAL;
 247	}
 248
 249	/* By the default is everything supported: */
 250	__default_kernel_pte_mask = __supported_pte_mask;
 251	/* Except when with PTI where the kernel is mostly non-Global: */
 252	if (cpu_feature_enabled(X86_FEATURE_PTI))
 253		__default_kernel_pte_mask &= ~_PAGE_GLOBAL;
 254
 255	/* Enable 1 GB linear kernel mappings if available: */
 256	if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) {
 257		printk(KERN_INFO "Using GB pages for direct mapping\n");
 258		page_size_mask |= 1 << PG_LEVEL_1G;
 259	} else {
 260		direct_gbpages = 0;
 261	}
 262}
 263
 264static void setup_pcid(void)
 265{
 266	if (!IS_ENABLED(CONFIG_X86_64))
 267		return;
 268
 269	if (!boot_cpu_has(X86_FEATURE_PCID))
 270		return;
 271
 272	if (boot_cpu_has(X86_FEATURE_PGE)) {
 273		/*
 274		 * This can't be cr4_set_bits_and_update_boot() -- the
 275		 * trampoline code can't handle CR4.PCIDE and it wouldn't
 276		 * do any good anyway.  Despite the name,
 277		 * cr4_set_bits_and_update_boot() doesn't actually cause
 278		 * the bits in question to remain set all the way through
 279		 * the secondary boot asm.
 280		 *
 281		 * Instead, we brute-force it and set CR4.PCIDE manually in
 282		 * start_secondary().
 283		 */
 284		cr4_set_bits(X86_CR4_PCIDE);
 285
 286		/*
 287		 * INVPCID's single-context modes (2/3) only work if we set
 288		 * X86_CR4_PCIDE, *and* we INVPCID support.  It's unusable
 289		 * on systems that have X86_CR4_PCIDE clear, or that have
 290		 * no INVPCID support at all.
 291		 */
 292		if (boot_cpu_has(X86_FEATURE_INVPCID))
 293			setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE);
 294	} else {
 295		/*
 296		 * flush_tlb_all(), as currently implemented, won't work if
 297		 * PCID is on but PGE is not.  Since that combination
 298		 * doesn't exist on real hardware, there's no reason to try
 299		 * to fully support it, but it's polite to avoid corrupting
 300		 * data if we're on an improperly configured VM.
 301		 */
 302		setup_clear_cpu_cap(X86_FEATURE_PCID);
 303	}
 304}
 305
 306#ifdef CONFIG_X86_32
 307#define NR_RANGE_MR 3
 308#else /* CONFIG_X86_64 */
 309#define NR_RANGE_MR 5
 310#endif
 311
 312static int __meminit save_mr(struct map_range *mr, int nr_range,
 313			     unsigned long start_pfn, unsigned long end_pfn,
 314			     unsigned long page_size_mask)
 315{
 316	if (start_pfn < end_pfn) {
 317		if (nr_range >= NR_RANGE_MR)
 318			panic("run out of range for init_memory_mapping\n");
 319		mr[nr_range].start = start_pfn<<PAGE_SHIFT;
 320		mr[nr_range].end   = end_pfn<<PAGE_SHIFT;
 321		mr[nr_range].page_size_mask = page_size_mask;
 322		nr_range++;
 323	}
 324
 325	return nr_range;
 326}
 327
 328/*
 329 * adjust the page_size_mask for small range to go with
 330 *	big page size instead small one if nearby are ram too.
 
 331 */
 332static void __ref adjust_range_page_size_mask(struct map_range *mr,
 333							 int nr_range)
 334{
 335	int i;
 336
 337	for (i = 0; i < nr_range; i++) {
 338		if ((page_size_mask & (1<<PG_LEVEL_2M)) &&
 339		    !(mr[i].page_size_mask & (1<<PG_LEVEL_2M))) {
 340			unsigned long start = round_down(mr[i].start, PMD_SIZE);
 341			unsigned long end = round_up(mr[i].end, PMD_SIZE);
 342
 343#ifdef CONFIG_X86_32
 344			if ((end >> PAGE_SHIFT) > max_low_pfn)
 345				continue;
 346#endif
 347
 348			if (memblock_is_region_memory(start, end - start))
 349				mr[i].page_size_mask |= 1<<PG_LEVEL_2M;
 350		}
 351		if ((page_size_mask & (1<<PG_LEVEL_1G)) &&
 352		    !(mr[i].page_size_mask & (1<<PG_LEVEL_1G))) {
 353			unsigned long start = round_down(mr[i].start, PUD_SIZE);
 354			unsigned long end = round_up(mr[i].end, PUD_SIZE);
 355
 356			if (memblock_is_region_memory(start, end - start))
 357				mr[i].page_size_mask |= 1<<PG_LEVEL_1G;
 358		}
 359	}
 360}
 361
 362static const char *page_size_string(struct map_range *mr)
 363{
 364	static const char str_1g[] = "1G";
 365	static const char str_2m[] = "2M";
 366	static const char str_4m[] = "4M";
 367	static const char str_4k[] = "4k";
 368
 369	if (mr->page_size_mask & (1<<PG_LEVEL_1G))
 370		return str_1g;
 371	/*
 372	 * 32-bit without PAE has a 4M large page size.
 373	 * PG_LEVEL_2M is misnamed, but we can at least
 374	 * print out the right size in the string.
 375	 */
 376	if (IS_ENABLED(CONFIG_X86_32) &&
 377	    !IS_ENABLED(CONFIG_X86_PAE) &&
 378	    mr->page_size_mask & (1<<PG_LEVEL_2M))
 379		return str_4m;
 
 380
 381	if (mr->page_size_mask & (1<<PG_LEVEL_2M))
 382		return str_2m;
 
 383
 384	return str_4k;
 385}
 
 
 
 386
 387static int __meminit split_mem_range(struct map_range *mr, int nr_range,
 388				     unsigned long start,
 389				     unsigned long end)
 390{
 391	unsigned long start_pfn, end_pfn, limit_pfn;
 392	unsigned long pfn;
 393	int i;
 394
 395	limit_pfn = PFN_DOWN(end);
 
 396
 397	/* head if not big page alignment ? */
 398	pfn = start_pfn = PFN_DOWN(start);
 
 399#ifdef CONFIG_X86_32
 400	/*
 401	 * Don't use a large page for the first 2/4MB of memory
 402	 * because there are often fixed size MTRRs in there
 403	 * and overlapping MTRRs into large pages can cause
 404	 * slowdowns.
 405	 */
 406	if (pfn == 0)
 407		end_pfn = PFN_DOWN(PMD_SIZE);
 408	else
 409		end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
 
 410#else /* CONFIG_X86_64 */
 411	end_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
 
 412#endif
 413	if (end_pfn > limit_pfn)
 414		end_pfn = limit_pfn;
 415	if (start_pfn < end_pfn) {
 416		nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
 417		pfn = end_pfn;
 418	}
 419
 420	/* big page (2M) range */
 421	start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
 
 422#ifdef CONFIG_X86_32
 423	end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
 424#else /* CONFIG_X86_64 */
 425	end_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
 426	if (end_pfn > round_down(limit_pfn, PFN_DOWN(PMD_SIZE)))
 427		end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
 
 428#endif
 429
 430	if (start_pfn < end_pfn) {
 431		nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
 432				page_size_mask & (1<<PG_LEVEL_2M));
 433		pfn = end_pfn;
 434	}
 435
 436#ifdef CONFIG_X86_64
 437	/* big page (1G) range */
 438	start_pfn = round_up(pfn, PFN_DOWN(PUD_SIZE));
 439	end_pfn = round_down(limit_pfn, PFN_DOWN(PUD_SIZE));
 
 440	if (start_pfn < end_pfn) {
 441		nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
 442				page_size_mask &
 443				 ((1<<PG_LEVEL_2M)|(1<<PG_LEVEL_1G)));
 444		pfn = end_pfn;
 445	}
 446
 447	/* tail is not big page (1G) alignment */
 448	start_pfn = round_up(pfn, PFN_DOWN(PMD_SIZE));
 449	end_pfn = round_down(limit_pfn, PFN_DOWN(PMD_SIZE));
 
 450	if (start_pfn < end_pfn) {
 451		nr_range = save_mr(mr, nr_range, start_pfn, end_pfn,
 452				page_size_mask & (1<<PG_LEVEL_2M));
 453		pfn = end_pfn;
 454	}
 455#endif
 456
 457	/* tail is not big page (2M) alignment */
 458	start_pfn = pfn;
 459	end_pfn = limit_pfn;
 460	nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
 461
 462	if (!after_bootmem)
 463		adjust_range_page_size_mask(mr, nr_range);
 464
 465	/* try to merge same page size and continuous */
 466	for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
 467		unsigned long old_start;
 468		if (mr[i].end != mr[i+1].start ||
 469		    mr[i].page_size_mask != mr[i+1].page_size_mask)
 470			continue;
 471		/* move it */
 472		old_start = mr[i].start;
 473		memmove(&mr[i], &mr[i+1],
 474			(nr_range - 1 - i) * sizeof(struct map_range));
 475		mr[i--].start = old_start;
 476		nr_range--;
 477	}
 478
 479	for (i = 0; i < nr_range; i++)
 480		pr_debug(" [mem %#010lx-%#010lx] page %s\n",
 481				mr[i].start, mr[i].end - 1,
 482				page_size_string(&mr[i]));
 483
 484	return nr_range;
 485}
 486
 487struct range pfn_mapped[E820_MAX_ENTRIES];
 488int nr_pfn_mapped;
 489
 490static void add_pfn_range_mapped(unsigned long start_pfn, unsigned long end_pfn)
 491{
 492	nr_pfn_mapped = add_range_with_merge(pfn_mapped, E820_MAX_ENTRIES,
 493					     nr_pfn_mapped, start_pfn, end_pfn);
 494	nr_pfn_mapped = clean_sort_range(pfn_mapped, E820_MAX_ENTRIES);
 495
 496	max_pfn_mapped = max(max_pfn_mapped, end_pfn);
 497
 498	if (start_pfn < (1UL<<(32-PAGE_SHIFT)))
 499		max_low_pfn_mapped = max(max_low_pfn_mapped,
 500					 min(end_pfn, 1UL<<(32-PAGE_SHIFT)));
 501}
 502
 503bool pfn_range_is_mapped(unsigned long start_pfn, unsigned long end_pfn)
 504{
 505	int i;
 506
 507	for (i = 0; i < nr_pfn_mapped; i++)
 508		if ((start_pfn >= pfn_mapped[i].start) &&
 509		    (end_pfn <= pfn_mapped[i].end))
 510			return true;
 511
 512	return false;
 513}
 514
 515/*
 516 * Setup the direct mapping of the physical memory at PAGE_OFFSET.
 517 * This runs before bootmem is initialized and gets pages directly from
 518 * the physical memory. To access them they are temporarily mapped.
 519 */
 520unsigned long __ref init_memory_mapping(unsigned long start,
 521					unsigned long end, pgprot_t prot)
 522{
 523	struct map_range mr[NR_RANGE_MR];
 524	unsigned long ret = 0;
 525	int nr_range, i;
 526
 527	pr_debug("init_memory_mapping: [mem %#010lx-%#010lx]\n",
 528	       start, end - 1);
 529
 530	memset(mr, 0, sizeof(mr));
 531	nr_range = split_mem_range(mr, 0, start, end);
 532
 533	for (i = 0; i < nr_range; i++)
 534		ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
 535						   mr[i].page_size_mask,
 536						   prot);
 537
 538	add_pfn_range_mapped(start >> PAGE_SHIFT, ret >> PAGE_SHIFT);
 539
 540	return ret >> PAGE_SHIFT;
 541}
 542
 543/*
 544 * We need to iterate through the E820 memory map and create direct mappings
 545 * for only E820_TYPE_RAM and E820_KERN_RESERVED regions. We cannot simply
 546 * create direct mappings for all pfns from [0 to max_low_pfn) and
 547 * [4GB to max_pfn) because of possible memory holes in high addresses
 548 * that cannot be marked as UC by fixed/variable range MTRRs.
 549 * Depending on the alignment of E820 ranges, this may possibly result
 550 * in using smaller size (i.e. 4K instead of 2M or 1G) page tables.
 551 *
 552 * init_mem_mapping() calls init_range_memory_mapping() with big range.
 553 * That range would have hole in the middle or ends, and only ram parts
 554 * will be mapped in init_range_memory_mapping().
 555 */
 556static unsigned long __init init_range_memory_mapping(
 557					   unsigned long r_start,
 558					   unsigned long r_end)
 559{
 560	unsigned long start_pfn, end_pfn;
 561	unsigned long mapped_ram_size = 0;
 562	int i;
 563
 564	for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
 565		u64 start = clamp_val(PFN_PHYS(start_pfn), r_start, r_end);
 566		u64 end = clamp_val(PFN_PHYS(end_pfn), r_start, r_end);
 567		if (start >= end)
 568			continue;
 569
 570		/*
 571		 * if it is overlapping with brk pgt, we need to
 572		 * alloc pgt buf from memblock instead.
 573		 */
 574		can_use_brk_pgt = max(start, (u64)pgt_buf_end<<PAGE_SHIFT) >=
 575				    min(end, (u64)pgt_buf_top<<PAGE_SHIFT);
 576		init_memory_mapping(start, end, PAGE_KERNEL);
 577		mapped_ram_size += end - start;
 578		can_use_brk_pgt = true;
 579	}
 580
 581	return mapped_ram_size;
 582}
 583
 584static unsigned long __init get_new_step_size(unsigned long step_size)
 585{
 586	/*
 587	 * Initial mapped size is PMD_SIZE (2M).
 588	 * We can not set step_size to be PUD_SIZE (1G) yet.
 589	 * In worse case, when we cross the 1G boundary, and
 590	 * PG_LEVEL_2M is not set, we will need 1+1+512 pages (2M + 8k)
 591	 * to map 1G range with PTE. Hence we use one less than the
 592	 * difference of page table level shifts.
 593	 *
 594	 * Don't need to worry about overflow in the top-down case, on 32bit,
 595	 * when step_size is 0, round_down() returns 0 for start, and that
 596	 * turns it into 0x100000000ULL.
 597	 * In the bottom-up case, round_up(x, 0) returns 0 though too, which
 598	 * needs to be taken into consideration by the code below.
 599	 */
 600	return step_size << (PMD_SHIFT - PAGE_SHIFT - 1);
 601}
 602
 603/**
 604 * memory_map_top_down - Map [map_start, map_end) top down
 605 * @map_start: start address of the target memory range
 606 * @map_end: end address of the target memory range
 607 *
 608 * This function will setup direct mapping for memory range
 609 * [map_start, map_end) in top-down. That said, the page tables
 610 * will be allocated at the end of the memory, and we map the
 611 * memory in top-down.
 612 */
 613static void __init memory_map_top_down(unsigned long map_start,
 614				       unsigned long map_end)
 615{
 616	unsigned long real_end, last_start;
 617	unsigned long step_size;
 618	unsigned long addr;
 619	unsigned long mapped_ram_size = 0;
 620
 621	/*
 622	 * Systems that have many reserved areas near top of the memory,
 623	 * e.g. QEMU with less than 1G RAM and EFI enabled, or Xen, will
 624	 * require lots of 4K mappings which may exhaust pgt_buf.
 625	 * Start with top-most PMD_SIZE range aligned at PMD_SIZE to ensure
 626	 * there is enough mapped memory that can be allocated from
 627	 * memblock.
 628	 */
 629	addr = memblock_phys_alloc_range(PMD_SIZE, PMD_SIZE, map_start,
 630					 map_end);
 631	memblock_phys_free(addr, PMD_SIZE);
 632	real_end = addr + PMD_SIZE;
 633
 634	/* step_size need to be small so pgt_buf from BRK could cover it */
 635	step_size = PMD_SIZE;
 636	max_pfn_mapped = 0; /* will get exact value next */
 637	min_pfn_mapped = real_end >> PAGE_SHIFT;
 638	last_start = real_end;
 639
 640	/*
 641	 * We start from the top (end of memory) and go to the bottom.
 642	 * The memblock_find_in_range() gets us a block of RAM from the
 643	 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
 644	 * for page table.
 645	 */
 646	while (last_start > map_start) {
 647		unsigned long start;
 648
 649		if (last_start > step_size) {
 650			start = round_down(last_start - 1, step_size);
 651			if (start < map_start)
 652				start = map_start;
 653		} else
 654			start = map_start;
 655		mapped_ram_size += init_range_memory_mapping(start,
 656							last_start);
 657		last_start = start;
 658		min_pfn_mapped = last_start >> PAGE_SHIFT;
 659		if (mapped_ram_size >= step_size)
 660			step_size = get_new_step_size(step_size);
 661	}
 662
 663	if (real_end < map_end)
 664		init_range_memory_mapping(real_end, map_end);
 665}
 666
 667/**
 668 * memory_map_bottom_up - Map [map_start, map_end) bottom up
 669 * @map_start: start address of the target memory range
 670 * @map_end: end address of the target memory range
 671 *
 672 * This function will setup direct mapping for memory range
 673 * [map_start, map_end) in bottom-up. Since we have limited the
 674 * bottom-up allocation above the kernel, the page tables will
 675 * be allocated just above the kernel and we map the memory
 676 * in [map_start, map_end) in bottom-up.
 677 */
 678static void __init memory_map_bottom_up(unsigned long map_start,
 679					unsigned long map_end)
 680{
 681	unsigned long next, start;
 682	unsigned long mapped_ram_size = 0;
 683	/* step_size need to be small so pgt_buf from BRK could cover it */
 684	unsigned long step_size = PMD_SIZE;
 685
 686	start = map_start;
 687	min_pfn_mapped = start >> PAGE_SHIFT;
 688
 689	/*
 690	 * We start from the bottom (@map_start) and go to the top (@map_end).
 691	 * The memblock_find_in_range() gets us a block of RAM from the
 692	 * end of RAM in [min_pfn_mapped, max_pfn_mapped) used as new pages
 693	 * for page table.
 694	 */
 695	while (start < map_end) {
 696		if (step_size && map_end - start > step_size) {
 697			next = round_up(start + 1, step_size);
 698			if (next > map_end)
 699				next = map_end;
 700		} else {
 701			next = map_end;
 702		}
 703
 704		mapped_ram_size += init_range_memory_mapping(start, next);
 705		start = next;
 706
 707		if (mapped_ram_size >= step_size)
 708			step_size = get_new_step_size(step_size);
 709	}
 710}
 711
 712/*
 713 * The real mode trampoline, which is required for bootstrapping CPUs
 714 * occupies only a small area under the low 1MB.  See reserve_real_mode()
 715 * for details.
 716 *
 717 * If KASLR is disabled the first PGD entry of the direct mapping is copied
 718 * to map the real mode trampoline.
 719 *
 720 * If KASLR is enabled, copy only the PUD which covers the low 1MB
 721 * area. This limits the randomization granularity to 1GB for both 4-level
 722 * and 5-level paging.
 723 */
 724static void __init init_trampoline(void)
 725{
 726#ifdef CONFIG_X86_64
 727	/*
 728	 * The code below will alias kernel page-tables in the user-range of the
 729	 * address space, including the Global bit. So global TLB entries will
 730	 * be created when using the trampoline page-table.
 731	 */
 732	if (!kaslr_memory_enabled())
 733		trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)];
 734	else
 735		init_trampoline_kaslr();
 736#endif
 737}
 738
 739void __init init_mem_mapping(void)
 740{
 741	unsigned long end;
 742
 743	pti_check_boottime_disable();
 744	probe_page_size_mask();
 745	setup_pcid();
 746
 747#ifdef CONFIG_X86_64
 748	end = max_pfn << PAGE_SHIFT;
 749#else
 750	end = max_low_pfn << PAGE_SHIFT;
 751#endif
 752
 753	/* the ISA range is always mapped regardless of memory holes */
 754	init_memory_mapping(0, ISA_END_ADDRESS, PAGE_KERNEL);
 755
 756	/* Init the trampoline, possibly with KASLR memory offset */
 757	init_trampoline();
 758
 759	/*
 760	 * If the allocation is in bottom-up direction, we setup direct mapping
 761	 * in bottom-up, otherwise we setup direct mapping in top-down.
 762	 */
 763	if (memblock_bottom_up()) {
 764		unsigned long kernel_end = __pa_symbol(_end);
 765
 766		/*
 767		 * we need two separate calls here. This is because we want to
 768		 * allocate page tables above the kernel. So we first map
 769		 * [kernel_end, end) to make memory above the kernel be mapped
 770		 * as soon as possible. And then use page tables allocated above
 771		 * the kernel to map [ISA_END_ADDRESS, kernel_end).
 772		 */
 773		memory_map_bottom_up(kernel_end, end);
 774		memory_map_bottom_up(ISA_END_ADDRESS, kernel_end);
 775	} else {
 776		memory_map_top_down(ISA_END_ADDRESS, end);
 777	}
 778
 779#ifdef CONFIG_X86_64
 780	if (max_pfn > max_low_pfn) {
 781		/* can we preserve max_low_pfn ?*/
 782		max_low_pfn = max_pfn;
 783	}
 784#else
 785	early_ioremap_page_table_range_init();
 786#endif
 787
 788	load_cr3(swapper_pg_dir);
 789	__flush_tlb_all();
 790
 791	x86_init.hyper.init_mem_mapping();
 792
 793	early_memtest(0, max_pfn_mapped << PAGE_SHIFT);
 794}
 795
 796/*
 797 * Initialize an mm_struct to be used during poking and a pointer to be used
 798 * during patching.
 799 */
 800void __init poking_init(void)
 801{
 802	spinlock_t *ptl;
 803	pte_t *ptep;
 804
 805	poking_mm = mm_alloc();
 806	BUG_ON(!poking_mm);
 807
 808	/* Xen PV guests need the PGD to be pinned. */
 809	paravirt_arch_dup_mmap(NULL, poking_mm);
 810
 811	/*
 812	 * Randomize the poking address, but make sure that the following page
 813	 * will be mapped at the same PMD. We need 2 pages, so find space for 3,
 814	 * and adjust the address if the PMD ends after the first one.
 815	 */
 816	poking_addr = TASK_UNMAPPED_BASE;
 817	if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
 818		poking_addr += (kaslr_get_random_long("Poking") & PAGE_MASK) %
 819			(TASK_SIZE - TASK_UNMAPPED_BASE - 3 * PAGE_SIZE);
 
 
 
 
 
 
 
 
 
 820
 821	if (((poking_addr + PAGE_SIZE) & ~PMD_MASK) == 0)
 822		poking_addr += PAGE_SIZE;
 823
 824	/*
 825	 * We need to trigger the allocation of the page-tables that will be
 826	 * needed for poking now. Later, poking may be performed in an atomic
 827	 * section, which might cause allocation to fail.
 828	 */
 829	ptep = get_locked_pte(poking_mm, poking_addr, &ptl);
 830	BUG_ON(!ptep);
 831	pte_unmap_unlock(ptep, ptl);
 832}
 833
 
 834/*
 835 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
 836 * is valid. The argument is a physical page number.
 837 *
 838 * On x86, access has to be given to the first megabyte of RAM because that
 839 * area traditionally contains BIOS code and data regions used by X, dosemu,
 840 * and similar apps. Since they map the entire memory range, the whole range
 841 * must be allowed (for mapping), but any areas that would otherwise be
 842 * disallowed are flagged as being "zero filled" instead of rejected.
 843 * Access has to be given to non-kernel-ram areas as well, these contain the
 844 * PCI mmio resources as well as potential bios/acpi data regions.
 845 */
 846int devmem_is_allowed(unsigned long pagenr)
 847{
 848	if (region_intersects(PFN_PHYS(pagenr), PAGE_SIZE,
 849				IORESOURCE_SYSTEM_RAM, IORES_DESC_NONE)
 850			!= REGION_DISJOINT) {
 851		/*
 852		 * For disallowed memory regions in the low 1MB range,
 853		 * request that the page be shown as all zeros.
 854		 */
 855		if (pagenr < 256)
 856			return 2;
 857
 858		return 0;
 859	}
 860
 861	/*
 862	 * This must follow RAM test, since System RAM is considered a
 863	 * restricted resource under CONFIG_STRICT_DEVMEM.
 864	 */
 865	if (iomem_is_exclusive(pagenr << PAGE_SHIFT)) {
 866		/* Low 1MB bypasses iomem restrictions. */
 867		if (pagenr < 256)
 868			return 1;
 869
 870		return 0;
 871	}
 872
 873	return 1;
 874}
 875
 876void free_init_pages(const char *what, unsigned long begin, unsigned long end)
 877{
 
 878	unsigned long begin_aligned, end_aligned;
 879
 880	/* Make sure boundaries are page aligned */
 881	begin_aligned = PAGE_ALIGN(begin);
 882	end_aligned   = end & PAGE_MASK;
 883
 884	if (WARN_ON(begin_aligned != begin || end_aligned != end)) {
 885		begin = begin_aligned;
 886		end   = end_aligned;
 887	}
 888
 889	if (begin >= end)
 890		return;
 891
 
 
 892	/*
 893	 * If debugging page accesses then do not free this memory but
 894	 * mark them not present - any buggy init-section access will
 895	 * create a kernel page fault:
 896	 */
 897	if (debug_pagealloc_enabled()) {
 898		pr_info("debug: unmapping init [mem %#010lx-%#010lx]\n",
 899			begin, end - 1);
 900		/*
 901		 * Inform kmemleak about the hole in the memory since the
 902		 * corresponding pages will be unmapped.
 903		 */
 904		kmemleak_free_part((void *)begin, end - begin);
 905		set_memory_np(begin, (end - begin) >> PAGE_SHIFT);
 906	} else {
 907		/*
 908		 * We just marked the kernel text read only above, now that
 909		 * we are going to free part of that, we need to make that
 910		 * writeable and non-executable first.
 911		 */
 912		set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
 913		set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
 914
 915		free_reserved_area((void *)begin, (void *)end,
 916				   POISON_FREE_INITMEM, what);
 917	}
 918}
 919
 920/*
 921 * begin/end can be in the direct map or the "high kernel mapping"
 922 * used for the kernel image only.  free_init_pages() will do the
 923 * right thing for either kind of address.
 924 */
 925void free_kernel_image_pages(const char *what, void *begin, void *end)
 926{
 927	unsigned long begin_ul = (unsigned long)begin;
 928	unsigned long end_ul = (unsigned long)end;
 929	unsigned long len_pages = (end_ul - begin_ul) >> PAGE_SHIFT;
 930
 931	free_init_pages(what, begin_ul, end_ul);
 932
 933	/*
 934	 * PTI maps some of the kernel into userspace.  For performance,
 935	 * this includes some kernel areas that do not contain secrets.
 936	 * Those areas might be adjacent to the parts of the kernel image
 937	 * being freed, which may contain secrets.  Remove the "high kernel
 938	 * image mapping" for these freed areas, ensuring they are not even
 939	 * potentially vulnerable to Meltdown regardless of the specific
 940	 * optimizations PTI is currently using.
 941	 *
 942	 * The "noalias" prevents unmapping the direct map alias which is
 943	 * needed to access the freed pages.
 944	 *
 945	 * This is only valid for 64bit kernels. 32bit has only one mapping
 946	 * which can't be treated in this way for obvious reasons.
 947	 */
 948	if (IS_ENABLED(CONFIG_X86_64) && cpu_feature_enabled(X86_FEATURE_PTI))
 949		set_memory_np_noalias(begin_ul, len_pages);
 950}
 951
 952void __ref free_initmem(void)
 953{
 954	e820__reallocate_tables();
 955
 956	mem_encrypt_free_decrypted_mem();
 
 
 
 
 
 
 
 
 957
 958	free_kernel_image_pages("unused kernel image (initmem)",
 959				&__init_begin, &__init_end);
 
 
 
 960}
 961
 962#ifdef CONFIG_BLK_DEV_INITRD
 963void __init free_initrd_mem(unsigned long start, unsigned long end)
 964{
 965	/*
 966	 * end could be not aligned, and We can not align that,
 967	 * decompressor could be confused by aligned initrd_end
 968	 * We already reserve the end partial page before in
 969	 *   - i386_start_kernel()
 970	 *   - x86_64_start_kernel()
 971	 *   - relocate_initrd()
 972	 * So here We can do PAGE_ALIGN() safely to get partial page to be freed
 973	 */
 974	free_init_pages("initrd", start, PAGE_ALIGN(end));
 975}
 976#endif
 977
 978/*
 979 * Calculate the precise size of the DMA zone (first 16 MB of RAM),
 980 * and pass it to the MM layer - to help it set zone watermarks more
 981 * accurately.
 982 *
 983 * Done on 64-bit systems only for the time being, although 32-bit systems
 984 * might benefit from this as well.
 985 */
 986void __init memblock_find_dma_reserve(void)
 987{
 988#ifdef CONFIG_X86_64
 989	u64 nr_pages = 0, nr_free_pages = 0;
 990	unsigned long start_pfn, end_pfn;
 991	phys_addr_t start_addr, end_addr;
 992	int i;
 993	u64 u;
 994
 995	/*
 996	 * Iterate over all memory ranges (free and reserved ones alike),
 997	 * to calculate the total number of pages in the first 16 MB of RAM:
 998	 */
 999	nr_pages = 0;
1000	for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
1001		start_pfn = min(start_pfn, MAX_DMA_PFN);
1002		end_pfn   = min(end_pfn,   MAX_DMA_PFN);
1003
1004		nr_pages += end_pfn - start_pfn;
1005	}
1006
1007	/*
1008	 * Iterate over free memory ranges to calculate the number of free
1009	 * pages in the DMA zone, while not counting potential partial
1010	 * pages at the beginning or the end of the range:
1011	 */
1012	nr_free_pages = 0;
1013	for_each_free_mem_range(u, NUMA_NO_NODE, MEMBLOCK_NONE, &start_addr, &end_addr, NULL) {
1014		start_pfn = min_t(unsigned long, PFN_UP(start_addr), MAX_DMA_PFN);
1015		end_pfn   = min_t(unsigned long, PFN_DOWN(end_addr), MAX_DMA_PFN);
1016
1017		if (start_pfn < end_pfn)
1018			nr_free_pages += end_pfn - start_pfn;
1019	}
1020
1021	set_dma_reserve(nr_pages - nr_free_pages);
1022#endif
1023}
1024
1025void __init zone_sizes_init(void)
1026{
1027	unsigned long max_zone_pfns[MAX_NR_ZONES];
1028
1029	memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1030
1031#ifdef CONFIG_ZONE_DMA
1032	max_zone_pfns[ZONE_DMA]		= min(MAX_DMA_PFN, max_low_pfn);
1033#endif
1034#ifdef CONFIG_ZONE_DMA32
1035	max_zone_pfns[ZONE_DMA32]	= min(MAX_DMA32_PFN, max_low_pfn);
1036#endif
1037	max_zone_pfns[ZONE_NORMAL]	= max_low_pfn;
1038#ifdef CONFIG_HIGHMEM
1039	max_zone_pfns[ZONE_HIGHMEM]	= max_pfn;
1040#endif
1041
1042	free_area_init(max_zone_pfns);
1043}
1044
1045__visible DEFINE_PER_CPU_ALIGNED(struct tlb_state, cpu_tlbstate) = {
1046	.loaded_mm = &init_mm,
1047	.next_asid = 1,
1048	.cr4 = ~0UL,	/* fail hard if we screw up cr4 shadow initialization */
1049};
1050
1051void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
1052{
1053	/* entry 0 MUST be WB (hardwired to speed up translations) */
1054	BUG_ON(!entry && cache != _PAGE_CACHE_MODE_WB);
1055
1056	__cachemode2pte_tbl[cache] = __cm_idx2pte(entry);
1057	__pte2cachemode_tbl[entry] = cache;
1058}
1059
1060#ifdef CONFIG_SWAP
1061unsigned long arch_max_swapfile_size(void)
1062{
1063	unsigned long pages;
1064
1065	pages = generic_max_swapfile_size();
1066
1067	if (boot_cpu_has_bug(X86_BUG_L1TF) && l1tf_mitigation != L1TF_MITIGATION_OFF) {
1068		/* Limit the swap file size to MAX_PA/2 for L1TF workaround */
1069		unsigned long long l1tf_limit = l1tf_pfn_limit();
1070		/*
1071		 * We encode swap offsets also with 3 bits below those for pfn
1072		 * which makes the usable limit higher.
1073		 */
1074#if CONFIG_PGTABLE_LEVELS > 2
1075		l1tf_limit <<= PAGE_SHIFT - SWP_OFFSET_FIRST_BIT;
1076#endif
1077		pages = min_t(unsigned long long, l1tf_limit, pages);
1078	}
1079	return pages;
1080}
1081#endif