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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8377E MDS Device Tree Source
4 *
5 * Copyright 2007 Freescale Semiconductor Inc.
6 */
7
8/dts-v1/;
9
10/ {
11 model = "fsl,mpc8377emds";
12 compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet1;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 pci0 = &pci0;
22 pci1 = &pci1;
23 pci2 = &pci2;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 PowerPC,8377@0 {
31 device_type = "cpu";
32 reg = <0x0>;
33 d-cache-line-size = <32>;
34 i-cache-line-size = <32>;
35 d-cache-size = <32768>;
36 i-cache-size = <32768>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0x00000000 0x20000000>; // 512MB at 0
46 };
47
48 localbus@e0005000 {
49 #address-cells = <2>;
50 #size-cells = <1>;
51 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
54 interrupt-parent = <&ipic>;
55
56 // booting from NOR flash
57 ranges = <0 0x0 0xfe000000 0x02000000
58 1 0x0 0xf8000000 0x00008000
59 3 0x0 0xe0600000 0x00008000>;
60
61 flash@0,0 {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
65 reg = <0 0x0 0x2000000>;
66 bank-width = <2>;
67 device-width = <1>;
68
69 u-boot@0 {
70 reg = <0x0 0x100000>;
71 read-only;
72 };
73
74 fs@100000 {
75 reg = <0x100000 0x800000>;
76 };
77
78 kernel@1d00000 {
79 reg = <0x1d00000 0x200000>;
80 };
81
82 dtb@1f00000 {
83 reg = <0x1f00000 0x100000>;
84 };
85 };
86
87 bcsr@1,0 {
88 reg = <1 0x0 0x8000>;
89 compatible = "fsl,mpc837xmds-bcsr";
90 };
91
92 nand@3,0 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 compatible = "fsl,mpc8377-fcm-nand",
96 "fsl,elbc-fcm-nand";
97 reg = <3 0x0 0x8000>;
98
99 u-boot@0 {
100 reg = <0x0 0x100000>;
101 read-only;
102 };
103
104 kernel@100000 {
105 reg = <0x100000 0x300000>;
106 };
107
108 fs@400000 {
109 reg = <0x400000 0x1c00000>;
110 };
111 };
112 };
113
114 soc@e0000000 {
115 #address-cells = <1>;
116 #size-cells = <1>;
117 device_type = "soc";
118 compatible = "simple-bus";
119 ranges = <0x0 0xe0000000 0x00100000>;
120 reg = <0xe0000000 0x00000200>;
121 bus-frequency = <0>;
122
123 wdt@200 {
124 compatible = "mpc83xx_wdt";
125 reg = <0x200 0x100>;
126 };
127
128 sleep-nexus {
129 #address-cells = <1>;
130 #size-cells = <1>;
131 compatible = "simple-bus";
132 sleep = <&pmc 0x0c000000>;
133 ranges;
134
135 i2c@3000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 cell-index = <0>;
139 compatible = "fsl-i2c";
140 reg = <0x3000 0x100>;
141 interrupts = <14 0x8>;
142 interrupt-parent = <&ipic>;
143 dfsrr;
144
145 rtc@68 {
146 compatible = "dallas,ds1374";
147 reg = <0x68>;
148 interrupts = <19 0x8>;
149 interrupt-parent = <&ipic>;
150 };
151 };
152
153 sdhci@2e000 {
154 compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
155 reg = <0x2e000 0x1000>;
156 interrupts = <42 0x8>;
157 interrupt-parent = <&ipic>;
158 sdhci,wp-inverted;
159 /* Filled in by U-Boot */
160 clock-frequency = <0>;
161 };
162 };
163
164 i2c@3100 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 cell-index = <1>;
168 compatible = "fsl-i2c";
169 reg = <0x3100 0x100>;
170 interrupts = <15 0x8>;
171 interrupt-parent = <&ipic>;
172 dfsrr;
173 };
174
175 spi@7000 {
176 cell-index = <0>;
177 compatible = "fsl,spi";
178 reg = <0x7000 0x1000>;
179 interrupts = <16 0x8>;
180 interrupt-parent = <&ipic>;
181 mode = "cpu";
182 };
183
184 usb@23000 {
185 compatible = "fsl-usb2-dr";
186 reg = <0x23000 0x1000>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189 interrupt-parent = <&ipic>;
190 interrupts = <38 0x8>;
191 dr_mode = "host";
192 phy_type = "ulpi";
193 sleep = <&pmc 0x00c00000>;
194 };
195
196 enet0: ethernet@24000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 cell-index = <0>;
200 device_type = "network";
201 model = "eTSEC";
202 compatible = "gianfar";
203 reg = <0x24000 0x1000>;
204 ranges = <0x0 0x24000 0x1000>;
205 local-mac-address = [ 00 00 00 00 00 00 ];
206 interrupts = <32 0x8 33 0x8 34 0x8>;
207 phy-connection-type = "mii";
208 interrupt-parent = <&ipic>;
209 tbi-handle = <&tbi0>;
210 phy-handle = <&phy2>;
211 sleep = <&pmc 0xc0000000>;
212 fsl,magic-packet;
213
214 mdio@520 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,gianfar-mdio";
218 reg = <0x520 0x20>;
219
220 phy2: ethernet-phy@2 {
221 interrupt-parent = <&ipic>;
222 interrupts = <17 0x8>;
223 reg = <0x2>;
224 };
225
226 phy3: ethernet-phy@3 {
227 interrupt-parent = <&ipic>;
228 interrupts = <18 0x8>;
229 reg = <0x3>;
230 };
231
232 tbi0: tbi-phy@11 {
233 reg = <0x11>;
234 device_type = "tbi-phy";
235 };
236 };
237 };
238
239 enet1: ethernet@25000 {
240 #address-cells = <1>;
241 #size-cells = <1>;
242 cell-index = <1>;
243 device_type = "network";
244 model = "eTSEC";
245 compatible = "gianfar";
246 reg = <0x25000 0x1000>;
247 ranges = <0x0 0x25000 0x1000>;
248 local-mac-address = [ 00 00 00 00 00 00 ];
249 interrupts = <35 0x8 36 0x8 37 0x8>;
250 phy-connection-type = "mii";
251 interrupt-parent = <&ipic>;
252 tbi-handle = <&tbi1>;
253 phy-handle = <&phy3>;
254 sleep = <&pmc 0x30000000>;
255 fsl,magic-packet;
256
257 mdio@520 {
258 #address-cells = <1>;
259 #size-cells = <0>;
260 compatible = "fsl,gianfar-tbi";
261 reg = <0x520 0x20>;
262
263 tbi1: tbi-phy@11 {
264 reg = <0x11>;
265 device_type = "tbi-phy";
266 };
267 };
268 };
269
270 serial0: serial@4500 {
271 cell-index = <0>;
272 device_type = "serial";
273 compatible = "fsl,ns16550", "ns16550";
274 reg = <0x4500 0x100>;
275 clock-frequency = <0>;
276 interrupts = <9 0x8>;
277 interrupt-parent = <&ipic>;
278 };
279
280 serial1: serial@4600 {
281 cell-index = <1>;
282 device_type = "serial";
283 compatible = "fsl,ns16550", "ns16550";
284 reg = <0x4600 0x100>;
285 clock-frequency = <0>;
286 interrupts = <10 0x8>;
287 interrupt-parent = <&ipic>;
288 };
289
290 dma@82a8 {
291 #address-cells = <1>;
292 #size-cells = <1>;
293 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
294 reg = <0x82a8 4>;
295 ranges = <0 0x8100 0x1a8>;
296 interrupt-parent = <&ipic>;
297 interrupts = <0x47 8>;
298 cell-index = <0>;
299 dma-channel@0 {
300 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
301 reg = <0 0x80>;
302 cell-index = <0>;
303 interrupt-parent = <&ipic>;
304 interrupts = <0x47 8>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
308 reg = <0x80 0x80>;
309 cell-index = <1>;
310 interrupt-parent = <&ipic>;
311 interrupts = <0x47 8>;
312 };
313 dma-channel@100 {
314 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
315 reg = <0x100 0x80>;
316 cell-index = <2>;
317 interrupt-parent = <&ipic>;
318 interrupts = <0x47 8>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
322 reg = <0x180 0x28>;
323 cell-index = <3>;
324 interrupt-parent = <&ipic>;
325 interrupts = <0x47 8>;
326 };
327 };
328
329 crypto@30000 {
330 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
331 "fsl,sec2.1", "fsl,sec2.0";
332 reg = <0x30000 0x10000>;
333 interrupts = <11 0x8>;
334 interrupt-parent = <&ipic>;
335 fsl,num-channels = <4>;
336 fsl,channel-fifo-len = <24>;
337 fsl,exec-units-mask = <0x9fe>;
338 fsl,descriptor-types-mask = <0x3ab0ebf>;
339 sleep = <&pmc 0x03000000>;
340 };
341
342 sata@18000 {
343 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
344 reg = <0x18000 0x1000>;
345 interrupts = <44 0x8>;
346 interrupt-parent = <&ipic>;
347 sleep = <&pmc 0x000000c0>;
348 };
349
350 sata@19000 {
351 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
352 reg = <0x19000 0x1000>;
353 interrupts = <45 0x8>;
354 interrupt-parent = <&ipic>;
355 sleep = <&pmc 0x00000030>;
356 };
357
358 /* IPIC
359 * interrupts cell = <intr #, sense>
360 * sense values match linux IORESOURCE_IRQ_* defines:
361 * sense == 8: Level, low assertion
362 * sense == 2: Edge, high-to-low change
363 */
364 ipic: pic@700 {
365 compatible = "fsl,ipic";
366 interrupt-controller;
367 #address-cells = <0>;
368 #interrupt-cells = <2>;
369 reg = <0x700 0x100>;
370 };
371
372 pmc: power@b00 {
373 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
374 reg = <0xb00 0x100 0xa00 0x100>;
375 interrupts = <80 0x8>;
376 interrupt-parent = <&ipic>;
377 };
378 };
379
380 pci0: pci@e0008500 {
381 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
382 interrupt-map = <
383
384 /* IDSEL 0x11 */
385 0x8800 0x0 0x0 0x1 &ipic 20 0x8
386 0x8800 0x0 0x0 0x2 &ipic 21 0x8
387 0x8800 0x0 0x0 0x3 &ipic 22 0x8
388 0x8800 0x0 0x0 0x4 &ipic 23 0x8
389
390 /* IDSEL 0x12 */
391 0x9000 0x0 0x0 0x1 &ipic 22 0x8
392 0x9000 0x0 0x0 0x2 &ipic 23 0x8
393 0x9000 0x0 0x0 0x3 &ipic 20 0x8
394 0x9000 0x0 0x0 0x4 &ipic 21 0x8
395
396 /* IDSEL 0x13 */
397 0x9800 0x0 0x0 0x1 &ipic 23 0x8
398 0x9800 0x0 0x0 0x2 &ipic 20 0x8
399 0x9800 0x0 0x0 0x3 &ipic 21 0x8
400 0x9800 0x0 0x0 0x4 &ipic 22 0x8
401
402 /* IDSEL 0x15 */
403 0xa800 0x0 0x0 0x1 &ipic 20 0x8
404 0xa800 0x0 0x0 0x2 &ipic 21 0x8
405 0xa800 0x0 0x0 0x3 &ipic 22 0x8
406 0xa800 0x0 0x0 0x4 &ipic 23 0x8
407
408 /* IDSEL 0x16 */
409 0xb000 0x0 0x0 0x1 &ipic 23 0x8
410 0xb000 0x0 0x0 0x2 &ipic 20 0x8
411 0xb000 0x0 0x0 0x3 &ipic 21 0x8
412 0xb000 0x0 0x0 0x4 &ipic 22 0x8
413
414 /* IDSEL 0x17 */
415 0xb800 0x0 0x0 0x1 &ipic 22 0x8
416 0xb800 0x0 0x0 0x2 &ipic 23 0x8
417 0xb800 0x0 0x0 0x3 &ipic 20 0x8
418 0xb800 0x0 0x0 0x4 &ipic 21 0x8
419
420 /* IDSEL 0x18 */
421 0xc000 0x0 0x0 0x1 &ipic 21 0x8
422 0xc000 0x0 0x0 0x2 &ipic 22 0x8
423 0xc000 0x0 0x0 0x3 &ipic 23 0x8
424 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
425 interrupt-parent = <&ipic>;
426 interrupts = <66 0x8>;
427 bus-range = <0x0 0x0>;
428 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
429 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
430 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
431 sleep = <&pmc 0x00010000>;
432 clock-frequency = <0>;
433 #interrupt-cells = <1>;
434 #size-cells = <2>;
435 #address-cells = <3>;
436 reg = <0xe0008500 0x100 /* internal registers */
437 0xe0008300 0x8>; /* config space access registers */
438 compatible = "fsl,mpc8349-pci";
439 device_type = "pci";
440 };
441
442 pci1: pcie@e0009000 {
443 #address-cells = <3>;
444 #size-cells = <2>;
445 #interrupt-cells = <1>;
446 device_type = "pci";
447 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
448 reg = <0xe0009000 0x00001000>;
449 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
450 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
451 bus-range = <0 255>;
452 interrupt-map-mask = <0xf800 0 0 7>;
453 interrupt-map = <0 0 0 1 &ipic 1 8
454 0 0 0 2 &ipic 1 8
455 0 0 0 3 &ipic 1 8
456 0 0 0 4 &ipic 1 8>;
457 sleep = <&pmc 0x00300000>;
458 clock-frequency = <0>;
459
460 pcie@0 {
461 #address-cells = <3>;
462 #size-cells = <2>;
463 device_type = "pci";
464 reg = <0 0 0 0 0>;
465 ranges = <0x02000000 0 0xa8000000
466 0x02000000 0 0xa8000000
467 0 0x10000000
468 0x01000000 0 0x00000000
469 0x01000000 0 0x00000000
470 0 0x00800000>;
471 };
472 };
473
474 pci2: pcie@e000a000 {
475 #address-cells = <3>;
476 #size-cells = <2>;
477 #interrupt-cells = <1>;
478 device_type = "pci";
479 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
480 reg = <0xe000a000 0x00001000>;
481 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
482 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
483 bus-range = <0 255>;
484 interrupt-map-mask = <0xf800 0 0 7>;
485 interrupt-map = <0 0 0 1 &ipic 2 8
486 0 0 0 2 &ipic 2 8
487 0 0 0 3 &ipic 2 8
488 0 0 0 4 &ipic 2 8>;
489 sleep = <&pmc 0x000c0000>;
490 clock-frequency = <0>;
491
492 pcie@0 {
493 #address-cells = <3>;
494 #size-cells = <2>;
495 device_type = "pci";
496 reg = <0 0 0 0 0>;
497 ranges = <0x02000000 0 0xc8000000
498 0x02000000 0 0xc8000000
499 0 0x10000000
500 0x01000000 0 0x00000000
501 0x01000000 0 0x00000000
502 0 0x00800000>;
503 };
504 };
505};
1/*
2 * MPC8377E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "fsl,mpc8377emds";
16 compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8377@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 };
45 };
46
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x20000000>; // 512MB at 0
50 };
51
52 localbus@e0005000 {
53 #address-cells = <2>;
54 #size-cells = <1>;
55 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
56 reg = <0xe0005000 0x1000>;
57 interrupts = <77 0x8>;
58 interrupt-parent = <&ipic>;
59
60 // booting from NOR flash
61 ranges = <0 0x0 0xfe000000 0x02000000
62 1 0x0 0xf8000000 0x00008000
63 3 0x0 0xe0600000 0x00008000>;
64
65 flash@0,0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "cfi-flash";
69 reg = <0 0x0 0x2000000>;
70 bank-width = <2>;
71 device-width = <1>;
72
73 u-boot@0 {
74 reg = <0x0 0x100000>;
75 read-only;
76 };
77
78 fs@100000 {
79 reg = <0x100000 0x800000>;
80 };
81
82 kernel@1d00000 {
83 reg = <0x1d00000 0x200000>;
84 };
85
86 dtb@1f00000 {
87 reg = <0x1f00000 0x100000>;
88 };
89 };
90
91 bcsr@1,0 {
92 reg = <1 0x0 0x8000>;
93 compatible = "fsl,mpc837xmds-bcsr";
94 };
95
96 nand@3,0 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "fsl,mpc8377-fcm-nand",
100 "fsl,elbc-fcm-nand";
101 reg = <3 0x0 0x8000>;
102
103 u-boot@0 {
104 reg = <0x0 0x100000>;
105 read-only;
106 };
107
108 kernel@100000 {
109 reg = <0x100000 0x300000>;
110 };
111
112 fs@400000 {
113 reg = <0x400000 0x1c00000>;
114 };
115 };
116 };
117
118 soc@e0000000 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 device_type = "soc";
122 compatible = "simple-bus";
123 ranges = <0x0 0xe0000000 0x00100000>;
124 reg = <0xe0000000 0x00000200>;
125 bus-frequency = <0>;
126
127 wdt@200 {
128 compatible = "mpc83xx_wdt";
129 reg = <0x200 0x100>;
130 };
131
132 sleep-nexus {
133 #address-cells = <1>;
134 #size-cells = <1>;
135 compatible = "simple-bus";
136 sleep = <&pmc 0x0c000000>;
137 ranges;
138
139 i2c@3000 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 cell-index = <0>;
143 compatible = "fsl-i2c";
144 reg = <0x3000 0x100>;
145 interrupts = <14 0x8>;
146 interrupt-parent = <&ipic>;
147 dfsrr;
148
149 rtc@68 {
150 compatible = "dallas,ds1374";
151 reg = <0x68>;
152 interrupts = <19 0x8>;
153 interrupt-parent = <&ipic>;
154 };
155 };
156
157 sdhci@2e000 {
158 compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
159 reg = <0x2e000 0x1000>;
160 interrupts = <42 0x8>;
161 interrupt-parent = <&ipic>;
162 sdhci,wp-inverted;
163 /* Filled in by U-Boot */
164 clock-frequency = <0>;
165 };
166 };
167
168 i2c@3100 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 cell-index = <1>;
172 compatible = "fsl-i2c";
173 reg = <0x3100 0x100>;
174 interrupts = <15 0x8>;
175 interrupt-parent = <&ipic>;
176 dfsrr;
177 };
178
179 spi@7000 {
180 cell-index = <0>;
181 compatible = "fsl,spi";
182 reg = <0x7000 0x1000>;
183 interrupts = <16 0x8>;
184 interrupt-parent = <&ipic>;
185 mode = "cpu";
186 };
187
188 usb@23000 {
189 compatible = "fsl-usb2-dr";
190 reg = <0x23000 0x1000>;
191 #address-cells = <1>;
192 #size-cells = <0>;
193 interrupt-parent = <&ipic>;
194 interrupts = <38 0x8>;
195 dr_mode = "host";
196 phy_type = "ulpi";
197 sleep = <&pmc 0x00c00000>;
198 };
199
200 enet0: ethernet@24000 {
201 #address-cells = <1>;
202 #size-cells = <1>;
203 cell-index = <0>;
204 device_type = "network";
205 model = "eTSEC";
206 compatible = "gianfar";
207 reg = <0x24000 0x1000>;
208 ranges = <0x0 0x24000 0x1000>;
209 local-mac-address = [ 00 00 00 00 00 00 ];
210 interrupts = <32 0x8 33 0x8 34 0x8>;
211 phy-connection-type = "mii";
212 interrupt-parent = <&ipic>;
213 tbi-handle = <&tbi0>;
214 phy-handle = <&phy2>;
215 sleep = <&pmc 0xc0000000>;
216 fsl,magic-packet;
217
218 mdio@520 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl,gianfar-mdio";
222 reg = <0x520 0x20>;
223
224 phy2: ethernet-phy@2 {
225 interrupt-parent = <&ipic>;
226 interrupts = <17 0x8>;
227 reg = <0x2>;
228 device_type = "ethernet-phy";
229 };
230
231 phy3: ethernet-phy@3 {
232 interrupt-parent = <&ipic>;
233 interrupts = <18 0x8>;
234 reg = <0x3>;
235 device_type = "ethernet-phy";
236 };
237
238 tbi0: tbi-phy@11 {
239 reg = <0x11>;
240 device_type = "tbi-phy";
241 };
242 };
243 };
244
245 enet1: ethernet@25000 {
246 #address-cells = <1>;
247 #size-cells = <1>;
248 cell-index = <1>;
249 device_type = "network";
250 model = "eTSEC";
251 compatible = "gianfar";
252 reg = <0x25000 0x1000>;
253 ranges = <0x0 0x25000 0x1000>;
254 local-mac-address = [ 00 00 00 00 00 00 ];
255 interrupts = <35 0x8 36 0x8 37 0x8>;
256 phy-connection-type = "mii";
257 interrupt-parent = <&ipic>;
258 tbi-handle = <&tbi1>;
259 phy-handle = <&phy3>;
260 sleep = <&pmc 0x30000000>;
261 fsl,magic-packet;
262
263 mdio@520 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,gianfar-tbi";
267 reg = <0x520 0x20>;
268
269 tbi1: tbi-phy@11 {
270 reg = <0x11>;
271 device_type = "tbi-phy";
272 };
273 };
274 };
275
276 serial0: serial@4500 {
277 cell-index = <0>;
278 device_type = "serial";
279 compatible = "fsl,ns16550", "ns16550";
280 reg = <0x4500 0x100>;
281 clock-frequency = <0>;
282 interrupts = <9 0x8>;
283 interrupt-parent = <&ipic>;
284 };
285
286 serial1: serial@4600 {
287 cell-index = <1>;
288 device_type = "serial";
289 compatible = "fsl,ns16550", "ns16550";
290 reg = <0x4600 0x100>;
291 clock-frequency = <0>;
292 interrupts = <10 0x8>;
293 interrupt-parent = <&ipic>;
294 };
295
296 dma@82a8 {
297 #address-cells = <1>;
298 #size-cells = <1>;
299 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
300 reg = <0x82a8 4>;
301 ranges = <0 0x8100 0x1a8>;
302 interrupt-parent = <&ipic>;
303 interrupts = <0x47 8>;
304 cell-index = <0>;
305 dma-channel@0 {
306 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
307 reg = <0 0x80>;
308 cell-index = <0>;
309 interrupt-parent = <&ipic>;
310 interrupts = <0x47 8>;
311 };
312 dma-channel@80 {
313 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
314 reg = <0x80 0x80>;
315 cell-index = <1>;
316 interrupt-parent = <&ipic>;
317 interrupts = <0x47 8>;
318 };
319 dma-channel@100 {
320 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
321 reg = <0x100 0x80>;
322 cell-index = <2>;
323 interrupt-parent = <&ipic>;
324 interrupts = <0x47 8>;
325 };
326 dma-channel@180 {
327 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
328 reg = <0x180 0x28>;
329 cell-index = <3>;
330 interrupt-parent = <&ipic>;
331 interrupts = <0x47 8>;
332 };
333 };
334
335 crypto@30000 {
336 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
337 "fsl,sec2.1", "fsl,sec2.0";
338 reg = <0x30000 0x10000>;
339 interrupts = <11 0x8>;
340 interrupt-parent = <&ipic>;
341 fsl,num-channels = <4>;
342 fsl,channel-fifo-len = <24>;
343 fsl,exec-units-mask = <0x9fe>;
344 fsl,descriptor-types-mask = <0x3ab0ebf>;
345 sleep = <&pmc 0x03000000>;
346 };
347
348 sata@18000 {
349 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
350 reg = <0x18000 0x1000>;
351 interrupts = <44 0x8>;
352 interrupt-parent = <&ipic>;
353 sleep = <&pmc 0x000000c0>;
354 };
355
356 sata@19000 {
357 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
358 reg = <0x19000 0x1000>;
359 interrupts = <45 0x8>;
360 interrupt-parent = <&ipic>;
361 sleep = <&pmc 0x00000030>;
362 };
363
364 /* IPIC
365 * interrupts cell = <intr #, sense>
366 * sense values match linux IORESOURCE_IRQ_* defines:
367 * sense == 8: Level, low assertion
368 * sense == 2: Edge, high-to-low change
369 */
370 ipic: pic@700 {
371 compatible = "fsl,ipic";
372 interrupt-controller;
373 #address-cells = <0>;
374 #interrupt-cells = <2>;
375 reg = <0x700 0x100>;
376 };
377
378 pmc: power@b00 {
379 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
380 reg = <0xb00 0x100 0xa00 0x100>;
381 interrupts = <80 0x8>;
382 interrupt-parent = <&ipic>;
383 };
384 };
385
386 pci0: pci@e0008500 {
387 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
388 interrupt-map = <
389
390 /* IDSEL 0x11 */
391 0x8800 0x0 0x0 0x1 &ipic 20 0x8
392 0x8800 0x0 0x0 0x2 &ipic 21 0x8
393 0x8800 0x0 0x0 0x3 &ipic 22 0x8
394 0x8800 0x0 0x0 0x4 &ipic 23 0x8
395
396 /* IDSEL 0x12 */
397 0x9000 0x0 0x0 0x1 &ipic 22 0x8
398 0x9000 0x0 0x0 0x2 &ipic 23 0x8
399 0x9000 0x0 0x0 0x3 &ipic 20 0x8
400 0x9000 0x0 0x0 0x4 &ipic 21 0x8
401
402 /* IDSEL 0x13 */
403 0x9800 0x0 0x0 0x1 &ipic 23 0x8
404 0x9800 0x0 0x0 0x2 &ipic 20 0x8
405 0x9800 0x0 0x0 0x3 &ipic 21 0x8
406 0x9800 0x0 0x0 0x4 &ipic 22 0x8
407
408 /* IDSEL 0x15 */
409 0xa800 0x0 0x0 0x1 &ipic 20 0x8
410 0xa800 0x0 0x0 0x2 &ipic 21 0x8
411 0xa800 0x0 0x0 0x3 &ipic 22 0x8
412 0xa800 0x0 0x0 0x4 &ipic 23 0x8
413
414 /* IDSEL 0x16 */
415 0xb000 0x0 0x0 0x1 &ipic 23 0x8
416 0xb000 0x0 0x0 0x2 &ipic 20 0x8
417 0xb000 0x0 0x0 0x3 &ipic 21 0x8
418 0xb000 0x0 0x0 0x4 &ipic 22 0x8
419
420 /* IDSEL 0x17 */
421 0xb800 0x0 0x0 0x1 &ipic 22 0x8
422 0xb800 0x0 0x0 0x2 &ipic 23 0x8
423 0xb800 0x0 0x0 0x3 &ipic 20 0x8
424 0xb800 0x0 0x0 0x4 &ipic 21 0x8
425
426 /* IDSEL 0x18 */
427 0xc000 0x0 0x0 0x1 &ipic 21 0x8
428 0xc000 0x0 0x0 0x2 &ipic 22 0x8
429 0xc000 0x0 0x0 0x3 &ipic 23 0x8
430 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
431 interrupt-parent = <&ipic>;
432 interrupts = <66 0x8>;
433 bus-range = <0x0 0x0>;
434 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
435 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
436 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
437 sleep = <&pmc 0x00010000>;
438 clock-frequency = <0>;
439 #interrupt-cells = <1>;
440 #size-cells = <2>;
441 #address-cells = <3>;
442 reg = <0xe0008500 0x100 /* internal registers */
443 0xe0008300 0x8>; /* config space access registers */
444 compatible = "fsl,mpc8349-pci";
445 device_type = "pci";
446 };
447
448 pci1: pcie@e0009000 {
449 #address-cells = <3>;
450 #size-cells = <2>;
451 #interrupt-cells = <1>;
452 device_type = "pci";
453 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
454 reg = <0xe0009000 0x00001000>;
455 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
456 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
457 bus-range = <0 255>;
458 interrupt-map-mask = <0xf800 0 0 7>;
459 interrupt-map = <0 0 0 1 &ipic 1 8
460 0 0 0 2 &ipic 1 8
461 0 0 0 3 &ipic 1 8
462 0 0 0 4 &ipic 1 8>;
463 sleep = <&pmc 0x00300000>;
464 clock-frequency = <0>;
465
466 pcie@0 {
467 #address-cells = <3>;
468 #size-cells = <2>;
469 device_type = "pci";
470 reg = <0 0 0 0 0>;
471 ranges = <0x02000000 0 0xa8000000
472 0x02000000 0 0xa8000000
473 0 0x10000000
474 0x01000000 0 0x00000000
475 0x01000000 0 0x00000000
476 0 0x00800000>;
477 };
478 };
479
480 pci2: pcie@e000a000 {
481 #address-cells = <3>;
482 #size-cells = <2>;
483 #interrupt-cells = <1>;
484 device_type = "pci";
485 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
486 reg = <0xe000a000 0x00001000>;
487 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
488 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
489 bus-range = <0 255>;
490 interrupt-map-mask = <0xf800 0 0 7>;
491 interrupt-map = <0 0 0 1 &ipic 2 8
492 0 0 0 2 &ipic 2 8
493 0 0 0 3 &ipic 2 8
494 0 0 0 4 &ipic 2 8>;
495 sleep = <&pmc 0x000c0000>;
496 clock-frequency = <0>;
497
498 pcie@0 {
499 #address-cells = <3>;
500 #size-cells = <2>;
501 device_type = "pci";
502 reg = <0 0 0 0 0>;
503 ranges = <0x02000000 0 0xc8000000
504 0x02000000 0 0xc8000000
505 0 0x10000000
506 0x01000000 0 0x00000000
507 0x01000000 0 0x00000000
508 0 0x00800000>;
509 };
510 };
511};