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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * S3C2443 clock register definitions
8 */
9
10#ifndef __ASM_ARM_REGS_S3C2443_CLOCK
11#define __ASM_ARM_REGS_S3C2443_CLOCK
12
13#include <linux/delay.h>
14#include "map-s3c.h"
15
16#define S3C2443_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
17
18#define S3C2443_PLLCON_MDIVSHIFT 16
19#define S3C2443_PLLCON_PDIVSHIFT 8
20#define S3C2443_PLLCON_SDIVSHIFT 0
21#define S3C2443_PLLCON_MDIVMASK ((1<<(1+(23-16)))-1)
22#define S3C2443_PLLCON_PDIVMASK ((1<<(1+(9-8)))-1)
23#define S3C2443_PLLCON_SDIVMASK (3)
24
25#define S3C2443_MPLLCON S3C2443_CLKREG(0x10)
26#define S3C2443_EPLLCON S3C2443_CLKREG(0x18)
27#define S3C2443_CLKSRC S3C2443_CLKREG(0x20)
28#define S3C2443_CLKDIV0 S3C2443_CLKREG(0x24)
29#define S3C2443_CLKDIV1 S3C2443_CLKREG(0x28)
30#define S3C2443_HCLKCON S3C2443_CLKREG(0x30)
31#define S3C2443_PCLKCON S3C2443_CLKREG(0x34)
32#define S3C2443_SCLKCON S3C2443_CLKREG(0x38)
33#define S3C2443_PWRMODE S3C2443_CLKREG(0x40)
34#define S3C2443_SWRST S3C2443_CLKREG(0x44)
35#define S3C2443_BUSPRI0 S3C2443_CLKREG(0x50)
36#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
37#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
38#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
39#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
40#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
41#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
42#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
43
44#define S3C2443_PLLCON_OFF (1<<24)
45
46#define S3C2443_CLKSRC_EPLLREF_XTAL (2<<7)
47#define S3C2443_CLKSRC_EPLLREF_EXTCLK (3<<7)
48#define S3C2443_CLKSRC_EPLLREF_MPLLREF (0<<7)
49#define S3C2443_CLKSRC_EPLLREF_MPLLREF2 (1<<7)
50#define S3C2443_CLKSRC_EPLLREF_MASK (3<<7)
51
52#define S3C2443_CLKSRC_EXTCLK_DIV (1<<3)
53
54#define S3C2443_CLKDIV0_HALF_HCLK (1<<3)
55#define S3C2443_CLKDIV0_HALF_PCLK (1<<2)
56
57#define S3C2443_CLKDIV0_HCLKDIV_MASK (3<<0)
58
59#define S3C2443_CLKDIV0_EXTDIV_MASK (3<<6)
60#define S3C2443_CLKDIV0_EXTDIV_SHIFT (6)
61
62#define S3C2443_CLKDIV0_PREDIV_MASK (3<<4)
63#define S3C2443_CLKDIV0_PREDIV_SHIFT (4)
64
65#define S3C2416_CLKDIV0_ARMDIV_MASK (7 << 9)
66#define S3C2443_CLKDIV0_ARMDIV_MASK (15<<9)
67#define S3C2443_CLKDIV0_ARMDIV_SHIFT (9)
68#define S3C2443_CLKDIV0_ARMDIV_1 (0<<9)
69#define S3C2443_CLKDIV0_ARMDIV_2 (8<<9)
70#define S3C2443_CLKDIV0_ARMDIV_3 (2<<9)
71#define S3C2443_CLKDIV0_ARMDIV_4 (9<<9)
72#define S3C2443_CLKDIV0_ARMDIV_6 (10<<9)
73#define S3C2443_CLKDIV0_ARMDIV_8 (11<<9)
74#define S3C2443_CLKDIV0_ARMDIV_12 (13<<9)
75#define S3C2443_CLKDIV0_ARMDIV_16 (15<<9)
76
77/* S3C2443_CLKDIV1 removed, only used in clock.c code */
78
79#define S3C2443_CLKCON_NAND
80
81#define S3C2443_HCLKCON_DMA0 (1<<0)
82#define S3C2443_HCLKCON_DMA1 (1<<1)
83#define S3C2443_HCLKCON_DMA2 (1<<2)
84#define S3C2443_HCLKCON_DMA3 (1<<3)
85#define S3C2443_HCLKCON_DMA4 (1<<4)
86#define S3C2443_HCLKCON_DMA5 (1<<5)
87#define S3C2443_HCLKCON_CAMIF (1<<8)
88#define S3C2443_HCLKCON_LCDC (1<<9)
89#define S3C2443_HCLKCON_USBH (1<<11)
90#define S3C2443_HCLKCON_USBD (1<<12)
91#define S3C2416_HCLKCON_HSMMC0 (1<<15)
92#define S3C2443_HCLKCON_HSMMC (1<<16)
93#define S3C2443_HCLKCON_CFC (1<<17)
94#define S3C2443_HCLKCON_SSMC (1<<18)
95#define S3C2443_HCLKCON_DRAMC (1<<19)
96
97#define S3C2443_PCLKCON_UART0 (1<<0)
98#define S3C2443_PCLKCON_UART1 (1<<1)
99#define S3C2443_PCLKCON_UART2 (1<<2)
100#define S3C2443_PCLKCON_UART3 (1<<3)
101#define S3C2443_PCLKCON_IIC (1<<4)
102#define S3C2443_PCLKCON_SDI (1<<5)
103#define S3C2443_PCLKCON_HSSPI (1<<6)
104#define S3C2443_PCLKCON_ADC (1<<7)
105#define S3C2443_PCLKCON_AC97 (1<<8)
106#define S3C2443_PCLKCON_IIS (1<<9)
107#define S3C2443_PCLKCON_PWMT (1<<10)
108#define S3C2443_PCLKCON_WDT (1<<11)
109#define S3C2443_PCLKCON_RTC (1<<12)
110#define S3C2443_PCLKCON_GPIO (1<<13)
111#define S3C2443_PCLKCON_SPI0 (1<<14)
112#define S3C2443_PCLKCON_SPI1 (1<<15)
113
114#define S3C2443_SCLKCON_DDRCLK (1<<16)
115#define S3C2443_SCLKCON_SSMCCLK (1<<15)
116#define S3C2443_SCLKCON_HSSPICLK (1<<14)
117#define S3C2443_SCLKCON_HSMMCCLK_EXT (1<<13)
118#define S3C2443_SCLKCON_HSMMCCLK_EPLL (1<<12)
119#define S3C2443_SCLKCON_CAMCLK (1<<11)
120#define S3C2443_SCLKCON_DISPCLK (1<<10)
121#define S3C2443_SCLKCON_I2SCLK (1<<9)
122#define S3C2443_SCLKCON_UARTCLK (1<<8)
123#define S3C2443_SCLKCON_USBHOST (1<<1)
124
125#define S3C2443_PWRCFG_SLEEP (1<<15)
126
127#define S3C2443_PWRCFG_USBPHY (1 << 4)
128
129#define S3C2443_URSTCON_FUNCRST (1 << 2)
130#define S3C2443_URSTCON_PHYRST (1 << 0)
131
132#define S3C2443_PHYCTRL_CLKSEL (1 << 3)
133#define S3C2443_PHYCTRL_EXTCLK (1 << 2)
134#define S3C2443_PHYCTRL_PLLSEL (1 << 1)
135#define S3C2443_PHYCTRL_DSPORT (1 << 0)
136
137#define S3C2443_PHYPWR_COMMON_ON (1 << 31)
138#define S3C2443_PHYPWR_ANALOG_PD (1 << 4)
139#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3)
140#define S3C2443_PHYPWR_XO_ON (1 << 2)
141#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1)
142#define S3C2443_PHYPWR_FSUSPEND (1 << 0)
143
144#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
145#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2)
146#define S3C2443_UCLKCON_TCLKEN (1 << 0)
147
148#include <asm/div64.h>
149
150static inline unsigned int
151s3c2443_get_mpll(unsigned int pllval, unsigned int baseclk)
152{
153 unsigned int mdiv, pdiv, sdiv;
154 uint64_t fvco;
155
156 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
157 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
158 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
159
160 mdiv &= S3C2443_PLLCON_MDIVMASK;
161 pdiv &= S3C2443_PLLCON_PDIVMASK;
162 sdiv &= S3C2443_PLLCON_SDIVMASK;
163
164 fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
165 do_div(fvco, pdiv << sdiv);
166
167 return (unsigned int)fvco;
168}
169
170static inline unsigned int
171s3c2443_get_epll(unsigned int pllval, unsigned int baseclk)
172{
173 unsigned int mdiv, pdiv, sdiv;
174 uint64_t fvco;
175
176 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT;
177 pdiv = pllval >> S3C2443_PLLCON_PDIVSHIFT;
178 sdiv = pllval >> S3C2443_PLLCON_SDIVSHIFT;
179
180 mdiv &= S3C2443_PLLCON_MDIVMASK;
181 pdiv &= S3C2443_PLLCON_PDIVMASK;
182 sdiv &= S3C2443_PLLCON_SDIVMASK;
183
184 fvco = (uint64_t)baseclk * (mdiv + 8);
185 do_div(fvco, (pdiv + 2) << sdiv);
186
187 return (unsigned int)fvco;
188}
189
190static inline void s3c_hsudc_init_phy(void)
191{
192 u32 cfg;
193
194 cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
195 writel(cfg, S3C2443_PWRCFG);
196
197 cfg = readl(S3C2443_URSTCON);
198 cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
199 writel(cfg, S3C2443_URSTCON);
200 mdelay(1);
201
202 cfg = readl(S3C2443_URSTCON);
203 cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
204 writel(cfg, S3C2443_URSTCON);
205
206 cfg = readl(S3C2443_PHYCTRL);
207 cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
208 cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
209 writel(cfg, S3C2443_PHYCTRL);
210
211 cfg = readl(S3C2443_PHYPWR);
212 cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
213 S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
214 S3C2443_PHYPWR_ANALOG_PD);
215 cfg |= S3C2443_PHYPWR_COMMON_ON;
216 writel(cfg, S3C2443_PHYPWR);
217
218 cfg = readl(S3C2443_UCLKCON);
219 cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
220 S3C2443_UCLKCON_TCLKEN);
221 writel(cfg, S3C2443_UCLKCON);
222}
223
224static inline void s3c_hsudc_uninit_phy(void)
225{
226 u32 cfg;
227
228 cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
229 writel(cfg, S3C2443_PWRCFG);
230
231 writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
232
233 cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
234 writel(cfg, S3C2443_UCLKCON);
235}
236
237#endif /* __ASM_ARM_REGS_S3C2443_CLOCK */
238