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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the Renesas RZ/V2M I2C unit
4 *
5 * Copyright (C) 2016-2022 Renesas Electronics Corporation
6 */
7
8#include <linux/bits.h>
9#include <linux/clk.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/i2c.h>
16#include <linux/jiffies.h>
17#include <linux/kernel.h>
18#include <linux/math64.h>
19#include <linux/module.h>
20#include <linux/mod_devicetable.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/reset.h>
24
25/* Register offsets */
26#define IICB0DAT 0x00 /* Data Register */
27#define IICB0CTL0 0x08 /* Control Register 0 */
28#define IICB0TRG 0x0C /* Trigger Register */
29#define IICB0STR0 0x10 /* Status Register 0 */
30#define IICB0CTL1 0x20 /* Control Register 1 */
31#define IICB0WL 0x24 /* Low Level Width Setting Reg */
32#define IICB0WH 0x28 /* How Level Width Setting Reg */
33
34/* IICB0CTL0 */
35#define IICB0IICE BIT(7) /* I2C Enable */
36#define IICB0SLWT BIT(1) /* Interrupt Request Timing */
37#define IICB0SLAC BIT(0) /* Acknowledge */
38
39/* IICB0TRG */
40#define IICB0WRET BIT(2) /* Quit Wait Trigger */
41#define IICB0STT BIT(1) /* Create Start Condition Trigger */
42#define IICB0SPT BIT(0) /* Create Stop Condition Trigger */
43
44/* IICB0STR0 */
45#define IICB0SSAC BIT(8) /* Ack Flag */
46#define IICB0SSBS BIT(6) /* Bus Flag */
47#define IICB0SSSP BIT(4) /* Stop Condition Flag */
48
49/* IICB0CTL1 */
50#define IICB0MDSC BIT(7) /* Bus Mode */
51#define IICB0SLSE BIT(1) /* Start condition output */
52
53#define bit_setl(addr, val) writel(readl(addr) | (val), (addr))
54#define bit_clrl(addr, val) writel(readl(addr) & ~(val), (addr))
55
56struct rzv2m_i2c_priv {
57 void __iomem *base;
58 struct i2c_adapter adap;
59 struct clk *clk;
60 int bus_mode;
61 struct completion msg_tia_done;
62 u32 iicb0wl;
63 u32 iicb0wh;
64};
65
66enum bcr_index {
67 RZV2M_I2C_100K = 0,
68 RZV2M_I2C_400K,
69};
70
71struct bitrate_config {
72 unsigned int percent_low;
73 unsigned int min_hold_time_ns;
74};
75
76static const struct bitrate_config bitrate_configs[] = {
77 [RZV2M_I2C_100K] = { 47, 3450 },
78 [RZV2M_I2C_400K] = { 52, 900 },
79};
80
81static irqreturn_t rzv2m_i2c_tia_irq_handler(int this_irq, void *dev_id)
82{
83 struct rzv2m_i2c_priv *priv = dev_id;
84
85 complete(&priv->msg_tia_done);
86
87 return IRQ_HANDLED;
88}
89
90/* Calculate IICB0WL and IICB0WH */
91static int rzv2m_i2c_clock_calculate(struct device *dev,
92 struct rzv2m_i2c_priv *priv)
93{
94 const struct bitrate_config *config;
95 unsigned int hold_time_ns;
96 unsigned int total_pclks;
97 unsigned int trf_pclks;
98 unsigned long pclk_hz;
99 struct i2c_timings t;
100 u32 trf_ns;
101
102 i2c_parse_fw_timings(dev, &t, true);
103
104 pclk_hz = clk_get_rate(priv->clk);
105 total_pclks = pclk_hz / t.bus_freq_hz;
106
107 trf_ns = t.scl_rise_ns + t.scl_fall_ns;
108 trf_pclks = mul_u64_u32_div(pclk_hz, trf_ns, NSEC_PER_SEC);
109
110 /* Config setting */
111 switch (t.bus_freq_hz) {
112 case I2C_MAX_FAST_MODE_FREQ:
113 priv->bus_mode = RZV2M_I2C_400K;
114 break;
115 case I2C_MAX_STANDARD_MODE_FREQ:
116 priv->bus_mode = RZV2M_I2C_100K;
117 break;
118 default:
119 dev_err(dev, "transfer speed is invalid\n");
120 return -EINVAL;
121 }
122 config = &bitrate_configs[priv->bus_mode];
123
124 /* IICB0WL = (percent_low / Transfer clock) x PCLK */
125 priv->iicb0wl = total_pclks * config->percent_low / 100;
126 if (priv->iicb0wl > (BIT(10) - 1))
127 return -EINVAL;
128
129 /* IICB0WH = ((percent_high / Transfer clock) x PCLK) - (tR + tF) */
130 priv->iicb0wh = total_pclks - priv->iicb0wl - trf_pclks;
131 if (priv->iicb0wh > (BIT(10) - 1))
132 return -EINVAL;
133
134 /*
135 * Data hold time must be less than 0.9us in fast mode and
136 * 3.45us in standard mode.
137 * Data hold time = IICB0WL[9:2] / PCLK
138 */
139 hold_time_ns = div64_ul((u64)(priv->iicb0wl >> 2) * NSEC_PER_SEC, pclk_hz);
140 if (hold_time_ns > config->min_hold_time_ns) {
141 dev_err(dev, "data hold time %dns is over %dns\n",
142 hold_time_ns, config->min_hold_time_ns);
143 return -EINVAL;
144 }
145
146 return 0;
147}
148
149static void rzv2m_i2c_init(struct rzv2m_i2c_priv *priv)
150{
151 u32 i2c_ctl0;
152 u32 i2c_ctl1;
153
154 /* i2c disable */
155 writel(0, priv->base + IICB0CTL0);
156
157 /* IICB0CTL1 setting */
158 i2c_ctl1 = IICB0SLSE;
159 if (priv->bus_mode == RZV2M_I2C_400K)
160 i2c_ctl1 |= IICB0MDSC;
161 writel(i2c_ctl1, priv->base + IICB0CTL1);
162
163 /* IICB0WL IICB0WH setting */
164 writel(priv->iicb0wl, priv->base + IICB0WL);
165 writel(priv->iicb0wh, priv->base + IICB0WH);
166
167 /* i2c enable after setting */
168 i2c_ctl0 = IICB0SLWT | IICB0SLAC | IICB0IICE;
169 writel(i2c_ctl0, priv->base + IICB0CTL0);
170}
171
172static int rzv2m_i2c_write_with_ack(struct rzv2m_i2c_priv *priv, u32 data)
173{
174 unsigned long time_left;
175
176 reinit_completion(&priv->msg_tia_done);
177
178 writel(data, priv->base + IICB0DAT);
179
180 time_left = wait_for_completion_timeout(&priv->msg_tia_done,
181 priv->adap.timeout);
182 if (!time_left)
183 return -ETIMEDOUT;
184
185 /* Confirm ACK */
186 if ((readl(priv->base + IICB0STR0) & IICB0SSAC) != IICB0SSAC)
187 return -ENXIO;
188
189 return 0;
190}
191
192static int rzv2m_i2c_read_with_ack(struct rzv2m_i2c_priv *priv, u8 *data,
193 bool last)
194{
195 unsigned long time_left;
196 u32 data_tmp;
197
198 reinit_completion(&priv->msg_tia_done);
199
200 /* Interrupt request timing : 8th clock */
201 bit_clrl(priv->base + IICB0CTL0, IICB0SLWT);
202
203 /* Exit the wait state */
204 writel(IICB0WRET, priv->base + IICB0TRG);
205
206 /* Wait for transaction */
207 time_left = wait_for_completion_timeout(&priv->msg_tia_done,
208 priv->adap.timeout);
209 if (!time_left)
210 return -ETIMEDOUT;
211
212 if (last) {
213 /* Disable ACK */
214 bit_clrl(priv->base + IICB0CTL0, IICB0SLAC);
215
216 /* Read data*/
217 data_tmp = readl(priv->base + IICB0DAT);
218
219 /* Interrupt request timing : 9th clock */
220 bit_setl(priv->base + IICB0CTL0, IICB0SLWT);
221
222 /* Exit the wait state */
223 writel(IICB0WRET, priv->base + IICB0TRG);
224
225 /* Wait for transaction */
226 time_left = wait_for_completion_timeout(&priv->msg_tia_done,
227 priv->adap.timeout);
228 if (!time_left)
229 return -ETIMEDOUT;
230
231 /* Enable ACK */
232 bit_setl(priv->base + IICB0CTL0, IICB0SLAC);
233 } else {
234 /* Read data */
235 data_tmp = readl(priv->base + IICB0DAT);
236 }
237
238 *data = data_tmp;
239
240 return 0;
241}
242
243static int rzv2m_i2c_send(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
244 unsigned int *count)
245{
246 unsigned int i;
247 int ret;
248
249 for (i = 0; i < msg->len; i++) {
250 ret = rzv2m_i2c_write_with_ack(priv, msg->buf[i]);
251 if (ret < 0)
252 return ret;
253 }
254 *count = i;
255
256 return 0;
257}
258
259static int rzv2m_i2c_receive(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
260 unsigned int *count)
261{
262 unsigned int i;
263 int ret;
264
265 for (i = 0; i < msg->len; i++) {
266 ret = rzv2m_i2c_read_with_ack(priv, &msg->buf[i],
267 (msg->len - 1) == i);
268 if (ret < 0)
269 return ret;
270 }
271 *count = i;
272
273 return 0;
274}
275
276static int rzv2m_i2c_send_address(struct rzv2m_i2c_priv *priv,
277 struct i2c_msg *msg)
278{
279 u32 addr;
280 int ret;
281
282 if (msg->flags & I2C_M_TEN) {
283 /*
284 * 10-bit address
285 * addr_1: 5'b11110 | addr[9:8] | (R/nW)
286 * addr_2: addr[7:0]
287 */
288 addr = 0xf0 | ((msg->addr & GENMASK(9, 8)) >> 7);
289 addr |= !!(msg->flags & I2C_M_RD);
290 /* Send 1st address(extend code) */
291 ret = rzv2m_i2c_write_with_ack(priv, addr);
292 if (ret)
293 return ret;
294
295 /* Send 2nd address */
296 ret = rzv2m_i2c_write_with_ack(priv, msg->addr & 0xff);
297 } else {
298 /* 7-bit address */
299 addr = i2c_8bit_addr_from_msg(msg);
300 ret = rzv2m_i2c_write_with_ack(priv, addr);
301 }
302
303 return ret;
304}
305
306static int rzv2m_i2c_stop_condition(struct rzv2m_i2c_priv *priv)
307{
308 u32 value;
309
310 /* Send stop condition */
311 writel(IICB0SPT, priv->base + IICB0TRG);
312 return readl_poll_timeout(priv->base + IICB0STR0,
313 value, value & IICB0SSSP,
314 100, jiffies_to_usecs(priv->adap.timeout));
315}
316
317static int rzv2m_i2c_master_xfer_msg(struct rzv2m_i2c_priv *priv,
318 struct i2c_msg *msg, int stop)
319{
320 unsigned int count = 0;
321 int ret, read = !!(msg->flags & I2C_M_RD);
322
323 /* Send start condition */
324 writel(IICB0STT, priv->base + IICB0TRG);
325
326 ret = rzv2m_i2c_send_address(priv, msg);
327 if (!ret) {
328 if (read)
329 ret = rzv2m_i2c_receive(priv, msg, &count);
330 else
331 ret = rzv2m_i2c_send(priv, msg, &count);
332
333 if (!ret && stop)
334 ret = rzv2m_i2c_stop_condition(priv);
335 }
336
337 if (ret == -ENXIO)
338 rzv2m_i2c_stop_condition(priv);
339 else if (ret < 0)
340 rzv2m_i2c_init(priv);
341 else
342 ret = count;
343
344 return ret;
345}
346
347static int rzv2m_i2c_master_xfer(struct i2c_adapter *adap,
348 struct i2c_msg *msgs, int num)
349{
350 struct rzv2m_i2c_priv *priv = i2c_get_adapdata(adap);
351 struct device *dev = priv->adap.dev.parent;
352 unsigned int i;
353 int ret;
354
355 ret = pm_runtime_resume_and_get(dev);
356 if (ret < 0)
357 return ret;
358
359 if (readl(priv->base + IICB0STR0) & IICB0SSBS) {
360 ret = -EAGAIN;
361 goto out;
362 }
363
364 /* I2C main transfer */
365 for (i = 0; i < num; i++) {
366 ret = rzv2m_i2c_master_xfer_msg(priv, &msgs[i], i == (num - 1));
367 if (ret < 0)
368 goto out;
369 }
370 ret = num;
371
372out:
373 pm_runtime_mark_last_busy(dev);
374 pm_runtime_put_autosuspend(dev);
375
376 return ret;
377}
378
379static u32 rzv2m_i2c_func(struct i2c_adapter *adap)
380{
381 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
382 I2C_FUNC_10BIT_ADDR;
383}
384
385static const struct i2c_adapter_quirks rzv2m_i2c_quirks = {
386 .flags = I2C_AQ_NO_ZERO_LEN,
387};
388
389static struct i2c_algorithm rzv2m_i2c_algo = {
390 .master_xfer = rzv2m_i2c_master_xfer,
391 .functionality = rzv2m_i2c_func,
392};
393
394static int rzv2m_i2c_probe(struct platform_device *pdev)
395{
396 struct device *dev = &pdev->dev;
397 struct rzv2m_i2c_priv *priv;
398 struct reset_control *rstc;
399 struct i2c_adapter *adap;
400 struct resource *res;
401 int irq, ret;
402
403 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
404 if (!priv)
405 return -ENOMEM;
406
407 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
408 if (IS_ERR(priv->base))
409 return PTR_ERR(priv->base);
410
411 priv->clk = devm_clk_get(dev, NULL);
412 if (IS_ERR(priv->clk))
413 return dev_err_probe(dev, PTR_ERR(priv->clk), "Can't get clock\n");
414
415 rstc = devm_reset_control_get_shared(dev, NULL);
416 if (IS_ERR(rstc))
417 return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n");
418 /*
419 * The reset also affects other HW that is not under the control
420 * of Linux. Therefore, all we can do is deassert the reset.
421 */
422 reset_control_deassert(rstc);
423
424 irq = platform_get_irq(pdev, 0);
425 if (irq < 0)
426 return irq;
427
428 ret = devm_request_irq(dev, irq, rzv2m_i2c_tia_irq_handler, 0,
429 dev_name(dev), priv);
430 if (ret < 0)
431 return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);
432
433 adap = &priv->adap;
434 adap->nr = pdev->id;
435 adap->algo = &rzv2m_i2c_algo;
436 adap->quirks = &rzv2m_i2c_quirks;
437 adap->dev.parent = dev;
438 adap->owner = THIS_MODULE;
439 device_set_node(&adap->dev, dev_fwnode(dev));
440 i2c_set_adapdata(adap, priv);
441 strscpy(adap->name, pdev->name, sizeof(adap->name));
442 init_completion(&priv->msg_tia_done);
443
444 ret = rzv2m_i2c_clock_calculate(dev, priv);
445 if (ret < 0)
446 return ret;
447
448 pm_runtime_enable(dev);
449
450 pm_runtime_get_sync(dev);
451 rzv2m_i2c_init(priv);
452 pm_runtime_put(dev);
453
454 platform_set_drvdata(pdev, priv);
455
456 ret = i2c_add_numbered_adapter(adap);
457 if (ret < 0)
458 pm_runtime_disable(dev);
459
460 return ret;
461}
462
463static int rzv2m_i2c_remove(struct platform_device *pdev)
464{
465 struct rzv2m_i2c_priv *priv = platform_get_drvdata(pdev);
466 struct device *dev = priv->adap.dev.parent;
467
468 i2c_del_adapter(&priv->adap);
469 bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
470 pm_runtime_disable(dev);
471
472 return 0;
473}
474
475static int rzv2m_i2c_suspend(struct device *dev)
476{
477 struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
478 int ret;
479
480 ret = pm_runtime_resume_and_get(dev);
481 if (ret < 0)
482 return ret;
483
484 bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
485 pm_runtime_put(dev);
486
487 return 0;
488}
489
490static int rzv2m_i2c_resume(struct device *dev)
491{
492 struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
493 int ret;
494
495 ret = rzv2m_i2c_clock_calculate(dev, priv);
496 if (ret < 0)
497 return ret;
498
499 ret = pm_runtime_resume_and_get(dev);
500 if (ret < 0)
501 return ret;
502
503 rzv2m_i2c_init(priv);
504 pm_runtime_put(dev);
505
506 return 0;
507}
508
509static const struct of_device_id rzv2m_i2c_ids[] = {
510 { .compatible = "renesas,rzv2m-i2c" },
511 { }
512};
513MODULE_DEVICE_TABLE(of, rzv2m_i2c_ids);
514
515static const struct dev_pm_ops rzv2m_i2c_pm_ops = {
516 SYSTEM_SLEEP_PM_OPS(rzv2m_i2c_suspend, rzv2m_i2c_resume)
517};
518
519static struct platform_driver rzv2m_i2c_driver = {
520 .driver = {
521 .name = "rzv2m-i2c",
522 .of_match_table = rzv2m_i2c_ids,
523 .pm = pm_sleep_ptr(&rzv2m_i2c_pm_ops),
524 },
525 .probe = rzv2m_i2c_probe,
526 .remove = rzv2m_i2c_remove,
527};
528module_platform_driver(rzv2m_i2c_driver);
529
530MODULE_DESCRIPTION("RZ/V2M I2C bus driver");
531MODULE_AUTHOR("Renesas Electronics Corporation");
532MODULE_LICENSE("GPL");