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1/*
2 * Synopsys DesignWare I2C adapter driver (master only).
3 *
4 * Based on the TI DAVINCI I2C adapter driver.
5 *
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
9 *
10 * ----------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ----------------------------------------------------------------------------
26 *
27 */
28#include <linux/export.h>
29#include <linux/errno.h>
30#include <linux/err.h>
31#include <linux/i2c.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/pm_runtime.h>
35#include <linux/delay.h>
36#include <linux/module.h>
37#include "i2c-designware-core.h"
38
39/*
40 * Registers offset
41 */
42#define DW_IC_CON 0x0
43#define DW_IC_TAR 0x4
44#define DW_IC_DATA_CMD 0x10
45#define DW_IC_SS_SCL_HCNT 0x14
46#define DW_IC_SS_SCL_LCNT 0x18
47#define DW_IC_FS_SCL_HCNT 0x1c
48#define DW_IC_FS_SCL_LCNT 0x20
49#define DW_IC_INTR_STAT 0x2c
50#define DW_IC_INTR_MASK 0x30
51#define DW_IC_RAW_INTR_STAT 0x34
52#define DW_IC_RX_TL 0x38
53#define DW_IC_TX_TL 0x3c
54#define DW_IC_CLR_INTR 0x40
55#define DW_IC_CLR_RX_UNDER 0x44
56#define DW_IC_CLR_RX_OVER 0x48
57#define DW_IC_CLR_TX_OVER 0x4c
58#define DW_IC_CLR_RD_REQ 0x50
59#define DW_IC_CLR_TX_ABRT 0x54
60#define DW_IC_CLR_RX_DONE 0x58
61#define DW_IC_CLR_ACTIVITY 0x5c
62#define DW_IC_CLR_STOP_DET 0x60
63#define DW_IC_CLR_START_DET 0x64
64#define DW_IC_CLR_GEN_CALL 0x68
65#define DW_IC_ENABLE 0x6c
66#define DW_IC_STATUS 0x70
67#define DW_IC_TXFLR 0x74
68#define DW_IC_RXFLR 0x78
69#define DW_IC_SDA_HOLD 0x7c
70#define DW_IC_TX_ABRT_SOURCE 0x80
71#define DW_IC_ENABLE_STATUS 0x9c
72#define DW_IC_COMP_PARAM_1 0xf4
73#define DW_IC_COMP_VERSION 0xf8
74#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
75#define DW_IC_COMP_TYPE 0xfc
76#define DW_IC_COMP_TYPE_VALUE 0x44570140
77
78#define DW_IC_INTR_RX_UNDER 0x001
79#define DW_IC_INTR_RX_OVER 0x002
80#define DW_IC_INTR_RX_FULL 0x004
81#define DW_IC_INTR_TX_OVER 0x008
82#define DW_IC_INTR_TX_EMPTY 0x010
83#define DW_IC_INTR_RD_REQ 0x020
84#define DW_IC_INTR_TX_ABRT 0x040
85#define DW_IC_INTR_RX_DONE 0x080
86#define DW_IC_INTR_ACTIVITY 0x100
87#define DW_IC_INTR_STOP_DET 0x200
88#define DW_IC_INTR_START_DET 0x400
89#define DW_IC_INTR_GEN_CALL 0x800
90
91#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
92 DW_IC_INTR_TX_EMPTY | \
93 DW_IC_INTR_TX_ABRT | \
94 DW_IC_INTR_STOP_DET)
95
96#define DW_IC_STATUS_ACTIVITY 0x1
97
98#define DW_IC_ERR_TX_ABRT 0x1
99
100#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
101
102/*
103 * status codes
104 */
105#define STATUS_IDLE 0x0
106#define STATUS_WRITE_IN_PROGRESS 0x1
107#define STATUS_READ_IN_PROGRESS 0x2
108
109#define TIMEOUT 20 /* ms */
110
111/*
112 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
113 *
114 * only expected abort codes are listed here
115 * refer to the datasheet for the full list
116 */
117#define ABRT_7B_ADDR_NOACK 0
118#define ABRT_10ADDR1_NOACK 1
119#define ABRT_10ADDR2_NOACK 2
120#define ABRT_TXDATA_NOACK 3
121#define ABRT_GCALL_NOACK 4
122#define ABRT_GCALL_READ 5
123#define ABRT_SBYTE_ACKDET 7
124#define ABRT_SBYTE_NORSTRT 9
125#define ABRT_10B_RD_NORSTRT 10
126#define ABRT_MASTER_DIS 11
127#define ARB_LOST 12
128
129#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
130#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
131#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
132#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
133#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
134#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
135#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
136#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
137#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
138#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
139#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
140
141#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
142 DW_IC_TX_ABRT_10ADDR1_NOACK | \
143 DW_IC_TX_ABRT_10ADDR2_NOACK | \
144 DW_IC_TX_ABRT_TXDATA_NOACK | \
145 DW_IC_TX_ABRT_GCALL_NOACK)
146
147static char *abort_sources[] = {
148 [ABRT_7B_ADDR_NOACK] =
149 "slave address not acknowledged (7bit mode)",
150 [ABRT_10ADDR1_NOACK] =
151 "first address byte not acknowledged (10bit mode)",
152 [ABRT_10ADDR2_NOACK] =
153 "second address byte not acknowledged (10bit mode)",
154 [ABRT_TXDATA_NOACK] =
155 "data not acknowledged",
156 [ABRT_GCALL_NOACK] =
157 "no acknowledgement for a general call",
158 [ABRT_GCALL_READ] =
159 "read after general call",
160 [ABRT_SBYTE_ACKDET] =
161 "start byte acknowledged",
162 [ABRT_SBYTE_NORSTRT] =
163 "trying to send start byte when restart is disabled",
164 [ABRT_10B_RD_NORSTRT] =
165 "trying to read when restart is disabled (10bit mode)",
166 [ABRT_MASTER_DIS] =
167 "trying to use disabled adapter",
168 [ARB_LOST] =
169 "lost arbitration",
170};
171
172u32 dw_readl(struct dw_i2c_dev *dev, int offset)
173{
174 u32 value;
175
176 if (dev->accessor_flags & ACCESS_16BIT)
177 value = readw(dev->base + offset) |
178 (readw(dev->base + offset + 2) << 16);
179 else
180 value = readl(dev->base + offset);
181
182 if (dev->accessor_flags & ACCESS_SWAP)
183 return swab32(value);
184 else
185 return value;
186}
187
188void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
189{
190 if (dev->accessor_flags & ACCESS_SWAP)
191 b = swab32(b);
192
193 if (dev->accessor_flags & ACCESS_16BIT) {
194 writew((u16)b, dev->base + offset);
195 writew((u16)(b >> 16), dev->base + offset + 2);
196 } else {
197 writel(b, dev->base + offset);
198 }
199}
200
201static u32
202i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
203{
204 /*
205 * DesignWare I2C core doesn't seem to have solid strategy to meet
206 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
207 * will result in violation of the tHD;STA spec.
208 */
209 if (cond)
210 /*
211 * Conditional expression:
212 *
213 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
214 *
215 * This is based on the DW manuals, and represents an ideal
216 * configuration. The resulting I2C bus speed will be
217 * faster than any of the others.
218 *
219 * If your hardware is free from tHD;STA issue, try this one.
220 */
221 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
222 else
223 /*
224 * Conditional expression:
225 *
226 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
227 *
228 * This is just experimental rule; the tHD;STA period turned
229 * out to be proportinal to (_HCNT + 3). With this setting,
230 * we could meet both tHIGH and tHD;STA timing specs.
231 *
232 * If unsure, you'd better to take this alternative.
233 *
234 * The reason why we need to take into account "tf" here,
235 * is the same as described in i2c_dw_scl_lcnt().
236 */
237 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
238 - 3 + offset;
239}
240
241static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
242{
243 /*
244 * Conditional expression:
245 *
246 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
247 *
248 * DW I2C core starts counting the SCL CNTs for the LOW period
249 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
250 * In order to meet the tLOW timing spec, we need to take into
251 * account the fall time of SCL signal (tf). Default tf value
252 * should be 0.3 us, for safety.
253 */
254 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
255}
256
257static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
258{
259 int timeout = 100;
260
261 do {
262 dw_writel(dev, enable, DW_IC_ENABLE);
263 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
264 return;
265
266 /*
267 * Wait 10 times the signaling period of the highest I2C
268 * transfer supported by the driver (for 400KHz this is
269 * 25us) as described in the DesignWare I2C databook.
270 */
271 usleep_range(25, 250);
272 } while (timeout--);
273
274 dev_warn(dev->dev, "timeout in %sabling adapter\n",
275 enable ? "en" : "dis");
276}
277
278/**
279 * i2c_dw_init() - initialize the designware i2c master hardware
280 * @dev: device private data
281 *
282 * This functions configures and enables the I2C master.
283 * This function is called during I2C init function, and in case of timeout at
284 * run time.
285 */
286int i2c_dw_init(struct dw_i2c_dev *dev)
287{
288 u32 input_clock_khz;
289 u32 hcnt, lcnt;
290 u32 reg;
291 u32 sda_falling_time, scl_falling_time;
292
293 input_clock_khz = dev->get_clk_rate_khz(dev);
294
295 reg = dw_readl(dev, DW_IC_COMP_TYPE);
296 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
297 /* Configure register endianess access */
298 dev->accessor_flags |= ACCESS_SWAP;
299 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
300 /* Configure register access mode 16bit */
301 dev->accessor_flags |= ACCESS_16BIT;
302 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
303 dev_err(dev->dev, "Unknown Synopsys component type: "
304 "0x%08x\n", reg);
305 return -ENODEV;
306 }
307
308 /* Disable the adapter */
309 __i2c_dw_enable(dev, false);
310
311 /* set standard and fast speed deviders for high/low periods */
312
313 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
314 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
315
316 /* Standard-mode */
317 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
318 4000, /* tHD;STA = tHIGH = 4.0 us */
319 sda_falling_time,
320 0, /* 0: DW default, 1: Ideal */
321 0); /* No offset */
322 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
323 4700, /* tLOW = 4.7 us */
324 scl_falling_time,
325 0); /* No offset */
326
327 /* Allow platforms to specify the ideal HCNT and LCNT values */
328 if (dev->ss_hcnt && dev->ss_lcnt) {
329 hcnt = dev->ss_hcnt;
330 lcnt = dev->ss_lcnt;
331 }
332 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
333 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
334 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
335
336 /* Fast-mode */
337 hcnt = i2c_dw_scl_hcnt(input_clock_khz,
338 600, /* tHD;STA = tHIGH = 0.6 us */
339 sda_falling_time,
340 0, /* 0: DW default, 1: Ideal */
341 0); /* No offset */
342 lcnt = i2c_dw_scl_lcnt(input_clock_khz,
343 1300, /* tLOW = 1.3 us */
344 scl_falling_time,
345 0); /* No offset */
346
347 if (dev->fs_hcnt && dev->fs_lcnt) {
348 hcnt = dev->fs_hcnt;
349 lcnt = dev->fs_lcnt;
350 }
351 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
352 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
353 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
354
355 /* Configure SDA Hold Time if required */
356 if (dev->sda_hold_time) {
357 reg = dw_readl(dev, DW_IC_COMP_VERSION);
358 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
359 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
360 else
361 dev_warn(dev->dev,
362 "Hardware too old to adjust SDA hold time.");
363 }
364
365 /* Configure Tx/Rx FIFO threshold levels */
366 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
367 dw_writel(dev, 0, DW_IC_RX_TL);
368
369 /* configure the i2c master */
370 dw_writel(dev, dev->master_cfg , DW_IC_CON);
371 return 0;
372}
373EXPORT_SYMBOL_GPL(i2c_dw_init);
374
375/*
376 * Waiting for bus not busy
377 */
378static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
379{
380 int timeout = TIMEOUT;
381
382 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
383 if (timeout <= 0) {
384 dev_warn(dev->dev, "timeout waiting for bus ready\n");
385 return -ETIMEDOUT;
386 }
387 timeout--;
388 usleep_range(1000, 1100);
389 }
390
391 return 0;
392}
393
394static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
395{
396 struct i2c_msg *msgs = dev->msgs;
397 u32 ic_con, ic_tar = 0;
398
399 /* Disable the adapter */
400 __i2c_dw_enable(dev, false);
401
402 /* if the slave address is ten bit address, enable 10BITADDR */
403 ic_con = dw_readl(dev, DW_IC_CON);
404 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
405 ic_con |= DW_IC_CON_10BITADDR_MASTER;
406 /*
407 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
408 * mode has to be enabled via bit 12 of IC_TAR register.
409 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
410 * detected from registers.
411 */
412 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
413 } else {
414 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
415 }
416
417 dw_writel(dev, ic_con, DW_IC_CON);
418
419 /*
420 * Set the slave (target) address and enable 10-bit addressing mode
421 * if applicable.
422 */
423 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
424
425 /* enforce disabled interrupts (due to HW issues) */
426 i2c_dw_disable_int(dev);
427
428 /* Enable the adapter */
429 __i2c_dw_enable(dev, true);
430
431 /* Clear and enable interrupts */
432 i2c_dw_clear_int(dev);
433 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
434}
435
436/*
437 * Initiate (and continue) low level master read/write transaction.
438 * This function is only called from i2c_dw_isr, and pumping i2c_msg
439 * messages into the tx buffer. Even if the size of i2c_msg data is
440 * longer than the size of the tx buffer, it handles everything.
441 */
442static void
443i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
444{
445 struct i2c_msg *msgs = dev->msgs;
446 u32 intr_mask;
447 int tx_limit, rx_limit;
448 u32 addr = msgs[dev->msg_write_idx].addr;
449 u32 buf_len = dev->tx_buf_len;
450 u8 *buf = dev->tx_buf;
451 bool need_restart = false;
452
453 intr_mask = DW_IC_INTR_DEFAULT_MASK;
454
455 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
456 /*
457 * if target address has changed, we need to
458 * reprogram the target address in the i2c
459 * adapter when we are done with this transfer
460 */
461 if (msgs[dev->msg_write_idx].addr != addr) {
462 dev_err(dev->dev,
463 "%s: invalid target address\n", __func__);
464 dev->msg_err = -EINVAL;
465 break;
466 }
467
468 if (msgs[dev->msg_write_idx].len == 0) {
469 dev_err(dev->dev,
470 "%s: invalid message length\n", __func__);
471 dev->msg_err = -EINVAL;
472 break;
473 }
474
475 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
476 /* new i2c_msg */
477 buf = msgs[dev->msg_write_idx].buf;
478 buf_len = msgs[dev->msg_write_idx].len;
479
480 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
481 * IC_RESTART_EN are set, we must manually
482 * set restart bit between messages.
483 */
484 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
485 (dev->msg_write_idx > 0))
486 need_restart = true;
487 }
488
489 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
490 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
491
492 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
493 u32 cmd = 0;
494
495 /*
496 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
497 * manually set the stop bit. However, it cannot be
498 * detected from the registers so we set it always
499 * when writing/reading the last byte.
500 */
501 if (dev->msg_write_idx == dev->msgs_num - 1 &&
502 buf_len == 1)
503 cmd |= BIT(9);
504
505 if (need_restart) {
506 cmd |= BIT(10);
507 need_restart = false;
508 }
509
510 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
511
512 /* avoid rx buffer overrun */
513 if (rx_limit - dev->rx_outstanding <= 0)
514 break;
515
516 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
517 rx_limit--;
518 dev->rx_outstanding++;
519 } else
520 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
521 tx_limit--; buf_len--;
522 }
523
524 dev->tx_buf = buf;
525 dev->tx_buf_len = buf_len;
526
527 if (buf_len > 0) {
528 /* more bytes to be written */
529 dev->status |= STATUS_WRITE_IN_PROGRESS;
530 break;
531 } else
532 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
533 }
534
535 /*
536 * If i2c_msg index search is completed, we don't need TX_EMPTY
537 * interrupt any more.
538 */
539 if (dev->msg_write_idx == dev->msgs_num)
540 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
541
542 if (dev->msg_err)
543 intr_mask = 0;
544
545 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
546}
547
548static void
549i2c_dw_read(struct dw_i2c_dev *dev)
550{
551 struct i2c_msg *msgs = dev->msgs;
552 int rx_valid;
553
554 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
555 u32 len;
556 u8 *buf;
557
558 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
559 continue;
560
561 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
562 len = msgs[dev->msg_read_idx].len;
563 buf = msgs[dev->msg_read_idx].buf;
564 } else {
565 len = dev->rx_buf_len;
566 buf = dev->rx_buf;
567 }
568
569 rx_valid = dw_readl(dev, DW_IC_RXFLR);
570
571 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
572 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
573 dev->rx_outstanding--;
574 }
575
576 if (len > 0) {
577 dev->status |= STATUS_READ_IN_PROGRESS;
578 dev->rx_buf_len = len;
579 dev->rx_buf = buf;
580 return;
581 } else
582 dev->status &= ~STATUS_READ_IN_PROGRESS;
583 }
584}
585
586static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
587{
588 unsigned long abort_source = dev->abort_source;
589 int i;
590
591 if (abort_source & DW_IC_TX_ABRT_NOACK) {
592 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
593 dev_dbg(dev->dev,
594 "%s: %s\n", __func__, abort_sources[i]);
595 return -EREMOTEIO;
596 }
597
598 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
599 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
600
601 if (abort_source & DW_IC_TX_ARB_LOST)
602 return -EAGAIN;
603 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
604 return -EINVAL; /* wrong msgs[] data */
605 else
606 return -EIO;
607}
608
609/*
610 * Prepare controller for a transaction and call i2c_dw_xfer_msg
611 */
612int
613i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
614{
615 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
616 int ret;
617
618 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
619
620 mutex_lock(&dev->lock);
621 pm_runtime_get_sync(dev->dev);
622
623 reinit_completion(&dev->cmd_complete);
624 dev->msgs = msgs;
625 dev->msgs_num = num;
626 dev->cmd_err = 0;
627 dev->msg_write_idx = 0;
628 dev->msg_read_idx = 0;
629 dev->msg_err = 0;
630 dev->status = STATUS_IDLE;
631 dev->abort_source = 0;
632 dev->rx_outstanding = 0;
633
634 ret = i2c_dw_wait_bus_not_busy(dev);
635 if (ret < 0)
636 goto done;
637
638 /* start the transfers */
639 i2c_dw_xfer_init(dev);
640
641 /* wait for tx to complete */
642 ret = wait_for_completion_timeout(&dev->cmd_complete, HZ);
643 if (ret == 0) {
644 dev_err(dev->dev, "controller timed out\n");
645 /* i2c_dw_init implicitly disables the adapter */
646 i2c_dw_init(dev);
647 ret = -ETIMEDOUT;
648 goto done;
649 }
650
651 /*
652 * We must disable the adapter before unlocking the &dev->lock mutex
653 * below. Otherwise the hardware might continue generating interrupts
654 * which in turn causes a race condition with the following transfer.
655 * Needs some more investigation if the additional interrupts are
656 * a hardware bug or this driver doesn't handle them correctly yet.
657 */
658 __i2c_dw_enable(dev, false);
659
660 if (dev->msg_err) {
661 ret = dev->msg_err;
662 goto done;
663 }
664
665 /* no error */
666 if (likely(!dev->cmd_err)) {
667 ret = num;
668 goto done;
669 }
670
671 /* We have an error */
672 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
673 ret = i2c_dw_handle_tx_abort(dev);
674 goto done;
675 }
676 ret = -EIO;
677
678done:
679 pm_runtime_mark_last_busy(dev->dev);
680 pm_runtime_put_autosuspend(dev->dev);
681 mutex_unlock(&dev->lock);
682
683 return ret;
684}
685EXPORT_SYMBOL_GPL(i2c_dw_xfer);
686
687u32 i2c_dw_func(struct i2c_adapter *adap)
688{
689 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
690 return dev->functionality;
691}
692EXPORT_SYMBOL_GPL(i2c_dw_func);
693
694static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
695{
696 u32 stat;
697
698 /*
699 * The IC_INTR_STAT register just indicates "enabled" interrupts.
700 * Ths unmasked raw version of interrupt status bits are available
701 * in the IC_RAW_INTR_STAT register.
702 *
703 * That is,
704 * stat = dw_readl(IC_INTR_STAT);
705 * equals to,
706 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
707 *
708 * The raw version might be useful for debugging purposes.
709 */
710 stat = dw_readl(dev, DW_IC_INTR_STAT);
711
712 /*
713 * Do not use the IC_CLR_INTR register to clear interrupts, or
714 * you'll miss some interrupts, triggered during the period from
715 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
716 *
717 * Instead, use the separately-prepared IC_CLR_* registers.
718 */
719 if (stat & DW_IC_INTR_RX_UNDER)
720 dw_readl(dev, DW_IC_CLR_RX_UNDER);
721 if (stat & DW_IC_INTR_RX_OVER)
722 dw_readl(dev, DW_IC_CLR_RX_OVER);
723 if (stat & DW_IC_INTR_TX_OVER)
724 dw_readl(dev, DW_IC_CLR_TX_OVER);
725 if (stat & DW_IC_INTR_RD_REQ)
726 dw_readl(dev, DW_IC_CLR_RD_REQ);
727 if (stat & DW_IC_INTR_TX_ABRT) {
728 /*
729 * The IC_TX_ABRT_SOURCE register is cleared whenever
730 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
731 */
732 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
733 dw_readl(dev, DW_IC_CLR_TX_ABRT);
734 }
735 if (stat & DW_IC_INTR_RX_DONE)
736 dw_readl(dev, DW_IC_CLR_RX_DONE);
737 if (stat & DW_IC_INTR_ACTIVITY)
738 dw_readl(dev, DW_IC_CLR_ACTIVITY);
739 if (stat & DW_IC_INTR_STOP_DET)
740 dw_readl(dev, DW_IC_CLR_STOP_DET);
741 if (stat & DW_IC_INTR_START_DET)
742 dw_readl(dev, DW_IC_CLR_START_DET);
743 if (stat & DW_IC_INTR_GEN_CALL)
744 dw_readl(dev, DW_IC_CLR_GEN_CALL);
745
746 return stat;
747}
748
749/*
750 * Interrupt service routine. This gets called whenever an I2C interrupt
751 * occurs.
752 */
753irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
754{
755 struct dw_i2c_dev *dev = dev_id;
756 u32 stat, enabled;
757
758 enabled = dw_readl(dev, DW_IC_ENABLE);
759 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
760 dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__,
761 dev->adapter.name, enabled, stat);
762 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
763 return IRQ_NONE;
764
765 stat = i2c_dw_read_clear_intrbits(dev);
766
767 if (stat & DW_IC_INTR_TX_ABRT) {
768 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
769 dev->status = STATUS_IDLE;
770
771 /*
772 * Anytime TX_ABRT is set, the contents of the tx/rx
773 * buffers are flushed. Make sure to skip them.
774 */
775 dw_writel(dev, 0, DW_IC_INTR_MASK);
776 goto tx_aborted;
777 }
778
779 if (stat & DW_IC_INTR_RX_FULL)
780 i2c_dw_read(dev);
781
782 if (stat & DW_IC_INTR_TX_EMPTY)
783 i2c_dw_xfer_msg(dev);
784
785 /*
786 * No need to modify or disable the interrupt mask here.
787 * i2c_dw_xfer_msg() will take care of it according to
788 * the current transmit status.
789 */
790
791tx_aborted:
792 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
793 complete(&dev->cmd_complete);
794
795 return IRQ_HANDLED;
796}
797EXPORT_SYMBOL_GPL(i2c_dw_isr);
798
799void i2c_dw_enable(struct dw_i2c_dev *dev)
800{
801 /* Enable the adapter */
802 __i2c_dw_enable(dev, true);
803}
804EXPORT_SYMBOL_GPL(i2c_dw_enable);
805
806u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev)
807{
808 return dw_readl(dev, DW_IC_ENABLE);
809}
810EXPORT_SYMBOL_GPL(i2c_dw_is_enabled);
811
812void i2c_dw_disable(struct dw_i2c_dev *dev)
813{
814 /* Disable controller */
815 __i2c_dw_enable(dev, false);
816
817 /* Disable all interupts */
818 dw_writel(dev, 0, DW_IC_INTR_MASK);
819 dw_readl(dev, DW_IC_CLR_INTR);
820}
821EXPORT_SYMBOL_GPL(i2c_dw_disable);
822
823void i2c_dw_clear_int(struct dw_i2c_dev *dev)
824{
825 dw_readl(dev, DW_IC_CLR_INTR);
826}
827EXPORT_SYMBOL_GPL(i2c_dw_clear_int);
828
829void i2c_dw_disable_int(struct dw_i2c_dev *dev)
830{
831 dw_writel(dev, 0, DW_IC_INTR_MASK);
832}
833EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
834
835u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
836{
837 return dw_readl(dev, DW_IC_COMP_PARAM_1);
838}
839EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
840
841MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
842MODULE_LICENSE("GPL");