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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/printk.h>
25#include <linux/slab.h>
26#include <linux/uaccess.h>
27#include "kfd_priv.h"
28#include "kfd_mqd_manager.h"
29#include "v11_structs.h"
30#include "gc/gc_11_0_0_offset.h"
31#include "gc/gc_11_0_0_sh_mask.h"
32#include "amdgpu_amdkfd.h"
33
34static inline struct v11_compute_mqd *get_mqd(void *mqd)
35{
36 return (struct v11_compute_mqd *)mqd;
37}
38
39static inline struct v11_sdma_mqd *get_sdma_mqd(void *mqd)
40{
41 return (struct v11_sdma_mqd *)mqd;
42}
43
44static void update_cu_mask(struct mqd_manager *mm, void *mqd,
45 struct mqd_update_info *minfo)
46{
47 struct v11_compute_mqd *m;
48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
49
50 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) ||
51 !minfo->cu_mask.ptr)
52 return;
53
54 mqd_symmetrically_map_cu_mask(mm,
55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);
56
57 m = get_mqd(mqd);
58 m->compute_static_thread_mgmt_se0 = se_mask[0];
59 m->compute_static_thread_mgmt_se1 = se_mask[1];
60 m->compute_static_thread_mgmt_se2 = se_mask[2];
61 m->compute_static_thread_mgmt_se3 = se_mask[3];
62 m->compute_static_thread_mgmt_se4 = se_mask[4];
63 m->compute_static_thread_mgmt_se5 = se_mask[5];
64 m->compute_static_thread_mgmt_se6 = se_mask[6];
65 m->compute_static_thread_mgmt_se7 = se_mask[7];
66
67 pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n",
68 m->compute_static_thread_mgmt_se0,
69 m->compute_static_thread_mgmt_se1,
70 m->compute_static_thread_mgmt_se2,
71 m->compute_static_thread_mgmt_se3,
72 m->compute_static_thread_mgmt_se4,
73 m->compute_static_thread_mgmt_se5,
74 m->compute_static_thread_mgmt_se6,
75 m->compute_static_thread_mgmt_se7);
76}
77
78static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q)
79{
80 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
81 m->cp_hqd_queue_priority = q->priority;
82}
83
84static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
85 struct queue_properties *q)
86{
87 struct kfd_mem_obj *mqd_mem_obj;
88 int size;
89
90 /*
91 * MES write to areas beyond MQD size. So allocate
92 * 1 PAGE_SIZE memory for MQD is MES is enabled.
93 */
94 if (kfd->shared_resources.enable_mes)
95 size = PAGE_SIZE;
96 else
97 size = sizeof(struct v11_compute_mqd);
98
99 if (kfd_gtt_sa_allocate(kfd, size, &mqd_mem_obj))
100 return NULL;
101
102 return mqd_mem_obj;
103}
104
105static void init_mqd(struct mqd_manager *mm, void **mqd,
106 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
107 struct queue_properties *q)
108{
109 uint64_t addr;
110 struct v11_compute_mqd *m;
111 int size;
112
113 m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr;
114 addr = mqd_mem_obj->gpu_addr;
115
116 if (mm->dev->shared_resources.enable_mes)
117 size = PAGE_SIZE;
118 else
119 size = sizeof(struct v11_compute_mqd);
120
121 memset(m, 0, size);
122
123 m->header = 0xC0310800;
124 m->compute_pipelinestat_enable = 1;
125 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
126 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
127 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
128 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
129 m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF;
130 m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF;
131 m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF;
132 m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF;
133
134 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
135 0x55 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
136
137 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;
138
139 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
140 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
141
142 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
143 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
144 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
145
146 if (q->format == KFD_QUEUE_FORMAT_AQL) {
147 m->cp_hqd_aql_control =
148 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT;
149 }
150
151 if (mm->dev->cwsr_enabled) {
152 m->cp_hqd_persistent_state |=
153 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
154 m->cp_hqd_ctx_save_base_addr_lo =
155 lower_32_bits(q->ctx_save_restore_area_address);
156 m->cp_hqd_ctx_save_base_addr_hi =
157 upper_32_bits(q->ctx_save_restore_area_address);
158 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
159 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
160 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
161 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
162 }
163
164 *mqd = m;
165 if (gart_addr)
166 *gart_addr = addr;
167 mm->update_mqd(mm, m, q, NULL);
168}
169
170static int load_mqd(struct mqd_manager *mm, void *mqd,
171 uint32_t pipe_id, uint32_t queue_id,
172 struct queue_properties *p, struct mm_struct *mms)
173{
174 int r = 0;
175 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
176 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
177
178 r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id,
179 (uint32_t __user *)p->write_ptr,
180 wptr_shift, 0, mms);
181 return r;
182}
183
184static void update_mqd(struct mqd_manager *mm, void *mqd,
185 struct queue_properties *q,
186 struct mqd_update_info *minfo)
187{
188 struct v11_compute_mqd *m;
189
190 m = get_mqd(mqd);
191
192 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;
193 m->cp_hqd_pq_control |=
194 ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
195 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
196
197 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
198 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
199
200 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
201 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
202 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
203 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
204
205 m->cp_hqd_pq_doorbell_control =
206 q->doorbell_off <<
207 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
208 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
209 m->cp_hqd_pq_doorbell_control);
210
211 m->cp_hqd_ib_control = 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT;
212
213 /*
214 * HW does not clamp this field correctly. Maximum EOP queue size
215 * is constrained by per-SE EOP done signal count, which is 8-bit.
216 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
217 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
218 * is safe, giving a maximum field value of 0xA.
219 */
220 m->cp_hqd_eop_control = min(0xA,
221 ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
222 m->cp_hqd_eop_base_addr_lo =
223 lower_32_bits(q->eop_ring_buffer_address >> 8);
224 m->cp_hqd_eop_base_addr_hi =
225 upper_32_bits(q->eop_ring_buffer_address >> 8);
226
227 m->cp_hqd_iq_timer = 0;
228
229 m->cp_hqd_vmid = q->vmid;
230
231 if (q->format == KFD_QUEUE_FORMAT_AQL) {
232 /* GC 10 removed WPP_CLAMP from PQ Control */
233 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
234 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT |
235 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT ;
236 m->cp_hqd_pq_doorbell_control |=
237 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT;
238 }
239 if (mm->dev->cwsr_enabled)
240 m->cp_hqd_ctx_save_control = 0;
241
242 update_cu_mask(mm, mqd, minfo);
243 set_priority(m, q);
244
245 q->is_active = QUEUE_IS_ACTIVE(*q);
246}
247
248static uint32_t read_doorbell_id(void *mqd)
249{
250 struct v11_compute_mqd *m = (struct v11_compute_mqd *)mqd;
251
252 return m->queue_doorbell_id0;
253}
254
255static int get_wave_state(struct mqd_manager *mm, void *mqd,
256 void __user *ctl_stack,
257 u32 *ctl_stack_used_size,
258 u32 *save_area_used_size)
259{
260 struct v11_compute_mqd *m;
261 /*struct mqd_user_context_save_area_header header;*/
262
263 m = get_mqd(mqd);
264
265 /* Control stack is written backwards, while workgroup context data
266 * is written forwards. Both starts from m->cp_hqd_cntl_stack_size.
267 * Current position is at m->cp_hqd_cntl_stack_offset and
268 * m->cp_hqd_wg_state_offset, respectively.
269 */
270 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
271 m->cp_hqd_cntl_stack_offset;
272 *save_area_used_size = m->cp_hqd_wg_state_offset -
273 m->cp_hqd_cntl_stack_size;
274
275 /* Control stack is not copied to user mode for GFXv11 because
276 * it's part of the context save area that is already
277 * accessible to user mode
278 */
279/*
280 header.control_stack_size = *ctl_stack_used_size;
281 header.wave_state_size = *save_area_used_size;
282
283 header.wave_state_offset = m->cp_hqd_wg_state_offset;
284 header.control_stack_offset = m->cp_hqd_cntl_stack_offset;
285
286 if (copy_to_user(ctl_stack, &header, sizeof(header)))
287 return -EFAULT;
288*/
289 return 0;
290}
291
292static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
293 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
294 struct queue_properties *q)
295{
296 struct v11_compute_mqd *m;
297
298 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
299
300 m = get_mqd(*mqd);
301
302 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
303 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
304}
305
306static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
307 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
308 struct queue_properties *q)
309{
310 struct v11_sdma_mqd *m;
311
312 m = (struct v11_sdma_mqd *) mqd_mem_obj->cpu_ptr;
313
314 memset(m, 0, sizeof(struct v11_sdma_mqd));
315
316 *mqd = m;
317 if (gart_addr)
318 *gart_addr = mqd_mem_obj->gpu_addr;
319
320 mm->update_mqd(mm, m, q, NULL);
321}
322
323#define SDMA_RLC_DUMMY_DEFAULT 0xf
324
325static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
326 struct queue_properties *q,
327 struct mqd_update_info *minfo)
328{
329 struct v11_sdma_mqd *m;
330
331 m = get_sdma_mqd(mqd);
332 m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
333 << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
334 q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT |
335 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
336 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
337 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
338
339 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
340 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
341 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
342 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
343 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
344 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
345 m->sdmax_rlcx_doorbell_offset =
346 q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
347
348 m->sdma_engine_id = q->sdma_engine_id;
349 m->sdma_queue_id = q->sdma_queue_id;
350 m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT;
351
352 q->is_active = QUEUE_IS_ACTIVE(*q);
353}
354
355#if defined(CONFIG_DEBUG_FS)
356
357static int debugfs_show_mqd(struct seq_file *m, void *data)
358{
359 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
360 data, sizeof(struct v11_compute_mqd), false);
361 return 0;
362}
363
364static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
365{
366 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
367 data, sizeof(struct v11_sdma_mqd), false);
368 return 0;
369}
370
371#endif
372
373struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type,
374 struct kfd_dev *dev)
375{
376 struct mqd_manager *mqd;
377
378 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
379 return NULL;
380
381 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
382 if (!mqd)
383 return NULL;
384
385 mqd->dev = dev;
386
387 switch (type) {
388 case KFD_MQD_TYPE_CP:
389 pr_debug("%s@%i\n", __func__, __LINE__);
390 mqd->allocate_mqd = allocate_mqd;
391 mqd->init_mqd = init_mqd;
392 mqd->free_mqd = kfd_free_mqd_cp;
393 mqd->load_mqd = load_mqd;
394 mqd->update_mqd = update_mqd;
395 mqd->destroy_mqd = kfd_destroy_mqd_cp;
396 mqd->is_occupied = kfd_is_occupied_cp;
397 mqd->mqd_size = sizeof(struct v11_compute_mqd);
398 mqd->get_wave_state = get_wave_state;
399#if defined(CONFIG_DEBUG_FS)
400 mqd->debugfs_show_mqd = debugfs_show_mqd;
401#endif
402 pr_debug("%s@%i\n", __func__, __LINE__);
403 break;
404 case KFD_MQD_TYPE_HIQ:
405 pr_debug("%s@%i\n", __func__, __LINE__);
406 mqd->allocate_mqd = allocate_hiq_mqd;
407 mqd->init_mqd = init_mqd_hiq;
408 mqd->free_mqd = free_mqd_hiq_sdma;
409 mqd->load_mqd = kfd_hiq_load_mqd_kiq;
410 mqd->update_mqd = update_mqd;
411 mqd->destroy_mqd = kfd_destroy_mqd_cp;
412 mqd->is_occupied = kfd_is_occupied_cp;
413 mqd->mqd_size = sizeof(struct v11_compute_mqd);
414#if defined(CONFIG_DEBUG_FS)
415 mqd->debugfs_show_mqd = debugfs_show_mqd;
416#endif
417 mqd->read_doorbell_id = read_doorbell_id;
418 pr_debug("%s@%i\n", __func__, __LINE__);
419 break;
420 case KFD_MQD_TYPE_DIQ:
421 mqd->allocate_mqd = allocate_mqd;
422 mqd->init_mqd = init_mqd_hiq;
423 mqd->free_mqd = kfd_free_mqd_cp;
424 mqd->load_mqd = load_mqd;
425 mqd->update_mqd = update_mqd;
426 mqd->destroy_mqd = kfd_destroy_mqd_cp;
427 mqd->is_occupied = kfd_is_occupied_cp;
428 mqd->mqd_size = sizeof(struct v11_compute_mqd);
429#if defined(CONFIG_DEBUG_FS)
430 mqd->debugfs_show_mqd = debugfs_show_mqd;
431#endif
432 break;
433 case KFD_MQD_TYPE_SDMA:
434 pr_debug("%s@%i\n", __func__, __LINE__);
435 mqd->allocate_mqd = allocate_sdma_mqd;
436 mqd->init_mqd = init_mqd_sdma;
437 mqd->free_mqd = free_mqd_hiq_sdma;
438 mqd->load_mqd = kfd_load_mqd_sdma;
439 mqd->update_mqd = update_mqd_sdma;
440 mqd->destroy_mqd = kfd_destroy_mqd_sdma;
441 mqd->is_occupied = kfd_is_occupied_sdma;
442 mqd->mqd_size = sizeof(struct v11_sdma_mqd);
443#if defined(CONFIG_DEBUG_FS)
444 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
445#endif
446 pr_debug("%s@%i\n", __func__, __LINE__);
447 break;
448 default:
449 kfree(mqd);
450 return NULL;
451 }
452
453 return mqd;
454}