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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * nicstar.c
4 *
5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
6 *
7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
8 * It was taken from the frle-0.22 device driver.
9 * As the file doesn't have a copyright notice, in the file
10 * nicstarmac.copyright I put the copyright notice from the
11 * frle-0.22 device driver.
12 * Some code is based on the nicstar driver by M. Welsh.
13 *
14 * Author: Rui Prior (rprior@inescn.pt)
15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
16 *
17 *
18 * (C) INESC 1999
19 */
20
21/*
22 * IMPORTANT INFORMATION
23 *
24 * There are currently three types of spinlocks:
25 *
26 * 1 - Per card interrupt spinlock (to protect structures and such)
27 * 2 - Per SCQ scq spinlock
28 * 3 - Per card resource spinlock (to access registers, etc.)
29 *
30 * These must NEVER be grabbed in reverse order.
31 *
32 */
33
34/* Header files */
35
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/skbuff.h>
39#include <linux/atmdev.h>
40#include <linux/atm.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/types.h>
44#include <linux/string.h>
45#include <linux/delay.h>
46#include <linux/init.h>
47#include <linux/sched.h>
48#include <linux/timer.h>
49#include <linux/interrupt.h>
50#include <linux/bitops.h>
51#include <linux/slab.h>
52#include <linux/idr.h>
53#include <asm/io.h>
54#include <linux/uaccess.h>
55#include <linux/atomic.h>
56#include <linux/etherdevice.h>
57#include "nicstar.h"
58#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
59#include "suni.h"
60#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
61#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
62#include "idt77105.h"
63#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
64
65/* Additional code */
66
67#include "nicstarmac.c"
68
69/* Configurable parameters */
70
71#undef PHY_LOOPBACK
72#undef TX_DEBUG
73#undef RX_DEBUG
74#undef GENERAL_DEBUG
75#undef EXTRA_DEBUG
76
77/* Do not touch these */
78
79#ifdef TX_DEBUG
80#define TXPRINTK(args...) printk(args)
81#else
82#define TXPRINTK(args...)
83#endif /* TX_DEBUG */
84
85#ifdef RX_DEBUG
86#define RXPRINTK(args...) printk(args)
87#else
88#define RXPRINTK(args...)
89#endif /* RX_DEBUG */
90
91#ifdef GENERAL_DEBUG
92#define PRINTK(args...) printk(args)
93#else
94#define PRINTK(args...) do {} while (0)
95#endif /* GENERAL_DEBUG */
96
97#ifdef EXTRA_DEBUG
98#define XPRINTK(args...) printk(args)
99#else
100#define XPRINTK(args...)
101#endif /* EXTRA_DEBUG */
102
103/* Macros */
104
105#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
106
107#define NS_DELAY mdelay(1)
108
109#define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
110
111#ifndef ATM_SKB
112#define ATM_SKB(s) (&(s)->atm)
113#endif
114
115#define scq_virt_to_bus(scq, p) \
116 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
117
118/* Function declarations */
119
120static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
122 int count);
123static int ns_init_card(int i, struct pci_dev *pcidev);
124static void ns_init_card_error(ns_dev * card, int error);
125static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
127static void push_rxbufs(ns_dev *, struct sk_buff *);
128static irqreturn_t ns_irq_handler(int irq, void *dev_id);
129static int ns_open(struct atm_vcc *vcc);
130static void ns_close(struct atm_vcc *vcc);
131static void fill_tst(ns_dev * card, int n, vc_map * vc);
132static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
133static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb);
134static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
135 struct sk_buff *skb, bool may_sleep);
136static void process_tsq(ns_dev * card);
137static void drain_scq(ns_dev * card, scq_info * scq, int pos);
138static void process_rsq(ns_dev * card);
139static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
140static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
141static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
142static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
143static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
144static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
145static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
146static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
147#ifdef EXTRA_DEBUG
148static void which_list(ns_dev * card, struct sk_buff *skb);
149#endif
150static void ns_poll(struct timer_list *unused);
151static void ns_phy_put(struct atm_dev *dev, unsigned char value,
152 unsigned long addr);
153static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
154
155/* Global variables */
156
157static struct ns_dev *cards[NS_MAX_CARDS];
158static unsigned num_cards;
159static const struct atmdev_ops atm_ops = {
160 .open = ns_open,
161 .close = ns_close,
162 .ioctl = ns_ioctl,
163 .send = ns_send,
164 .send_bh = ns_send_bh,
165 .phy_put = ns_phy_put,
166 .phy_get = ns_phy_get,
167 .proc_read = ns_proc_read,
168 .owner = THIS_MODULE,
169};
170
171static struct timer_list ns_timer;
172static char *mac[NS_MAX_CARDS];
173module_param_array(mac, charp, NULL, 0);
174MODULE_LICENSE("GPL");
175
176/* Functions */
177
178static int nicstar_init_one(struct pci_dev *pcidev,
179 const struct pci_device_id *ent)
180{
181 static int index = -1;
182 unsigned int error;
183
184 index++;
185 cards[index] = NULL;
186
187 error = ns_init_card(index, pcidev);
188 if (error) {
189 cards[index--] = NULL; /* don't increment index */
190 goto err_out;
191 }
192
193 return 0;
194err_out:
195 return -ENODEV;
196}
197
198static void nicstar_remove_one(struct pci_dev *pcidev)
199{
200 int i, j;
201 ns_dev *card = pci_get_drvdata(pcidev);
202 struct sk_buff *hb;
203 struct sk_buff *iovb;
204 struct sk_buff *lb;
205 struct sk_buff *sb;
206
207 i = card->index;
208
209 if (cards[i] == NULL)
210 return;
211
212 if (card->atmdev->phy && card->atmdev->phy->stop)
213 card->atmdev->phy->stop(card->atmdev);
214
215 /* Stop everything */
216 writel(0x00000000, card->membase + CFG);
217
218 /* De-register device */
219 atm_dev_deregister(card->atmdev);
220
221 /* Disable PCI device */
222 pci_disable_device(pcidev);
223
224 /* Free up resources */
225 j = 0;
226 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
227 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
228 dev_kfree_skb_any(hb);
229 j++;
230 }
231 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
232 j = 0;
233 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
234 card->iovpool.count);
235 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
236 dev_kfree_skb_any(iovb);
237 j++;
238 }
239 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
240 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
241 dev_kfree_skb_any(lb);
242 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
243 dev_kfree_skb_any(sb);
244 free_scq(card, card->scq0, NULL);
245 for (j = 0; j < NS_FRSCD_NUM; j++) {
246 if (card->scd2vc[j] != NULL)
247 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
248 }
249 idr_destroy(&card->idr);
250 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
251 card->rsq.org, card->rsq.dma);
252 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
253 card->tsq.org, card->tsq.dma);
254 free_irq(card->pcidev->irq, card);
255 iounmap(card->membase);
256 kfree(card);
257}
258
259static const struct pci_device_id nicstar_pci_tbl[] = {
260 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
261 {0,} /* terminate list */
262};
263
264MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
265
266static struct pci_driver nicstar_driver = {
267 .name = "nicstar",
268 .id_table = nicstar_pci_tbl,
269 .probe = nicstar_init_one,
270 .remove = nicstar_remove_one,
271};
272
273static int __init nicstar_init(void)
274{
275 unsigned error = 0; /* Initialized to remove compile warning */
276
277 XPRINTK("nicstar: nicstar_init() called.\n");
278
279 error = pci_register_driver(&nicstar_driver);
280
281 TXPRINTK("nicstar: TX debug enabled.\n");
282 RXPRINTK("nicstar: RX debug enabled.\n");
283 PRINTK("nicstar: General debug enabled.\n");
284#ifdef PHY_LOOPBACK
285 printk("nicstar: using PHY loopback.\n");
286#endif /* PHY_LOOPBACK */
287 XPRINTK("nicstar: nicstar_init() returned.\n");
288
289 if (!error) {
290 timer_setup(&ns_timer, ns_poll, 0);
291 ns_timer.expires = jiffies + NS_POLL_PERIOD;
292 add_timer(&ns_timer);
293 }
294
295 return error;
296}
297
298static void __exit nicstar_cleanup(void)
299{
300 XPRINTK("nicstar: nicstar_cleanup() called.\n");
301
302 del_timer_sync(&ns_timer);
303
304 pci_unregister_driver(&nicstar_driver);
305
306 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
307}
308
309static u32 ns_read_sram(ns_dev * card, u32 sram_address)
310{
311 unsigned long flags;
312 u32 data;
313 sram_address <<= 2;
314 sram_address &= 0x0007FFFC; /* address must be dword aligned */
315 sram_address |= 0x50000000; /* SRAM read command */
316 spin_lock_irqsave(&card->res_lock, flags);
317 while (CMD_BUSY(card)) ;
318 writel(sram_address, card->membase + CMD);
319 while (CMD_BUSY(card)) ;
320 data = readl(card->membase + DR0);
321 spin_unlock_irqrestore(&card->res_lock, flags);
322 return data;
323}
324
325static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
326 int count)
327{
328 unsigned long flags;
329 int i, c;
330 count--; /* count range now is 0..3 instead of 1..4 */
331 c = count;
332 c <<= 2; /* to use increments of 4 */
333 spin_lock_irqsave(&card->res_lock, flags);
334 while (CMD_BUSY(card)) ;
335 for (i = 0; i <= c; i += 4)
336 writel(*(value++), card->membase + i);
337 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
338 so card->membase + DR0 == card->membase */
339 sram_address <<= 2;
340 sram_address &= 0x0007FFFC;
341 sram_address |= (0x40000000 | count);
342 writel(sram_address, card->membase + CMD);
343 spin_unlock_irqrestore(&card->res_lock, flags);
344}
345
346static int ns_init_card(int i, struct pci_dev *pcidev)
347{
348 int j;
349 struct ns_dev *card = NULL;
350 unsigned char pci_latency;
351 unsigned error;
352 u32 data;
353 u32 u32d[4];
354 u32 ns_cfg_rctsize;
355 int bcount;
356 unsigned long membase;
357
358 error = 0;
359
360 if (pci_enable_device(pcidev)) {
361 printk("nicstar%d: can't enable PCI device\n", i);
362 error = 2;
363 ns_init_card_error(card, error);
364 return error;
365 }
366 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) {
367 printk(KERN_WARNING
368 "nicstar%d: No suitable DMA available.\n", i);
369 error = 2;
370 ns_init_card_error(card, error);
371 return error;
372 }
373
374 card = kmalloc(sizeof(*card), GFP_KERNEL);
375 if (!card) {
376 printk
377 ("nicstar%d: can't allocate memory for device structure.\n",
378 i);
379 error = 2;
380 ns_init_card_error(card, error);
381 return error;
382 }
383 cards[i] = card;
384 spin_lock_init(&card->int_lock);
385 spin_lock_init(&card->res_lock);
386
387 pci_set_drvdata(pcidev, card);
388
389 card->index = i;
390 card->atmdev = NULL;
391 card->pcidev = pcidev;
392 membase = pci_resource_start(pcidev, 1);
393 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
394 if (!card->membase) {
395 printk("nicstar%d: can't ioremap() membase.\n", i);
396 error = 3;
397 ns_init_card_error(card, error);
398 return error;
399 }
400 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
401
402 pci_set_master(pcidev);
403
404 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
405 printk("nicstar%d: can't read PCI latency timer.\n", i);
406 error = 6;
407 ns_init_card_error(card, error);
408 return error;
409 }
410#ifdef NS_PCI_LATENCY
411 if (pci_latency < NS_PCI_LATENCY) {
412 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
413 NS_PCI_LATENCY);
414 for (j = 1; j < 4; j++) {
415 if (pci_write_config_byte
416 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
417 break;
418 }
419 if (j == 4) {
420 printk
421 ("nicstar%d: can't set PCI latency timer to %d.\n",
422 i, NS_PCI_LATENCY);
423 error = 7;
424 ns_init_card_error(card, error);
425 return error;
426 }
427 }
428#endif /* NS_PCI_LATENCY */
429
430 /* Clear timer overflow */
431 data = readl(card->membase + STAT);
432 if (data & NS_STAT_TMROF)
433 writel(NS_STAT_TMROF, card->membase + STAT);
434
435 /* Software reset */
436 writel(NS_CFG_SWRST, card->membase + CFG);
437 NS_DELAY;
438 writel(0x00000000, card->membase + CFG);
439
440 /* PHY reset */
441 writel(0x00000008, card->membase + GP);
442 NS_DELAY;
443 writel(0x00000001, card->membase + GP);
444 NS_DELAY;
445 while (CMD_BUSY(card)) ;
446 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
447 NS_DELAY;
448
449 /* Detect PHY type */
450 while (CMD_BUSY(card)) ;
451 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
452 while (CMD_BUSY(card)) ;
453 data = readl(card->membase + DR0);
454 switch (data) {
455 case 0x00000009:
456 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
457 card->max_pcr = ATM_25_PCR;
458 while (CMD_BUSY(card)) ;
459 writel(0x00000008, card->membase + DR0);
460 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
461 /* Clear an eventual pending interrupt */
462 writel(NS_STAT_SFBQF, card->membase + STAT);
463#ifdef PHY_LOOPBACK
464 while (CMD_BUSY(card)) ;
465 writel(0x00000022, card->membase + DR0);
466 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
467#endif /* PHY_LOOPBACK */
468 break;
469 case 0x00000030:
470 case 0x00000031:
471 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
472 card->max_pcr = ATM_OC3_PCR;
473#ifdef PHY_LOOPBACK
474 while (CMD_BUSY(card)) ;
475 writel(0x00000002, card->membase + DR0);
476 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
477#endif /* PHY_LOOPBACK */
478 break;
479 default:
480 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
481 error = 8;
482 ns_init_card_error(card, error);
483 return error;
484 }
485 writel(0x00000000, card->membase + GP);
486
487 /* Determine SRAM size */
488 data = 0x76543210;
489 ns_write_sram(card, 0x1C003, &data, 1);
490 data = 0x89ABCDEF;
491 ns_write_sram(card, 0x14003, &data, 1);
492 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
493 ns_read_sram(card, 0x1C003) == 0x76543210)
494 card->sram_size = 128;
495 else
496 card->sram_size = 32;
497 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
498
499 card->rct_size = NS_MAX_RCTSIZE;
500
501#if (NS_MAX_RCTSIZE == 4096)
502 if (card->sram_size == 128)
503 printk
504 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
505 i);
506#elif (NS_MAX_RCTSIZE == 16384)
507 if (card->sram_size == 32) {
508 printk
509 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
510 i);
511 card->rct_size = 4096;
512 }
513#else
514#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
515#endif
516
517 card->vpibits = NS_VPIBITS;
518 if (card->rct_size == 4096)
519 card->vcibits = 12 - NS_VPIBITS;
520 else /* card->rct_size == 16384 */
521 card->vcibits = 14 - NS_VPIBITS;
522
523 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
524 if (mac[i] == NULL)
525 nicstar_init_eprom(card->membase);
526
527 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
528 writel(0x00000000, card->membase + VPM);
529
530 card->intcnt = 0;
531 if (request_irq
532 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
533 pr_err("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
534 error = 9;
535 ns_init_card_error(card, error);
536 return error;
537 }
538
539 /* Initialize TSQ */
540 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
541 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
542 &card->tsq.dma, GFP_KERNEL);
543 if (card->tsq.org == NULL) {
544 printk("nicstar%d: can't allocate TSQ.\n", i);
545 error = 10;
546 ns_init_card_error(card, error);
547 return error;
548 }
549 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
550 card->tsq.next = card->tsq.base;
551 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
552 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
553 ns_tsi_init(card->tsq.base + j);
554 writel(0x00000000, card->membase + TSQH);
555 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
556 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
557
558 /* Initialize RSQ */
559 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
560 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
561 &card->rsq.dma, GFP_KERNEL);
562 if (card->rsq.org == NULL) {
563 printk("nicstar%d: can't allocate RSQ.\n", i);
564 error = 11;
565 ns_init_card_error(card, error);
566 return error;
567 }
568 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
569 card->rsq.next = card->rsq.base;
570 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
571 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
572 ns_rsqe_init(card->rsq.base + j);
573 writel(0x00000000, card->membase + RSQH);
574 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
575 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
576
577 /* Initialize SCQ0, the only VBR SCQ used */
578 card->scq1 = NULL;
579 card->scq2 = NULL;
580 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
581 if (card->scq0 == NULL) {
582 printk("nicstar%d: can't get SCQ0.\n", i);
583 error = 12;
584 ns_init_card_error(card, error);
585 return error;
586 }
587 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
588 u32d[1] = (u32) 0x00000000;
589 u32d[2] = (u32) 0xffffffff;
590 u32d[3] = (u32) 0x00000000;
591 ns_write_sram(card, NS_VRSCD0, u32d, 4);
592 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
593 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
594 card->scq0->scd = NS_VRSCD0;
595 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
596
597 /* Initialize TSTs */
598 card->tst_addr = NS_TST0;
599 card->tst_free_entries = NS_TST_NUM_ENTRIES;
600 data = NS_TST_OPCODE_VARIABLE;
601 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
602 ns_write_sram(card, NS_TST0 + j, &data, 1);
603 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
604 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
605 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
606 ns_write_sram(card, NS_TST1 + j, &data, 1);
607 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
608 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
609 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
610 card->tste2vc[j] = NULL;
611 writel(NS_TST0 << 2, card->membase + TSTB);
612
613 /* Initialize RCT. AAL type is set on opening the VC. */
614#ifdef RCQ_SUPPORT
615 u32d[0] = NS_RCTE_RAWCELLINTEN;
616#else
617 u32d[0] = 0x00000000;
618#endif /* RCQ_SUPPORT */
619 u32d[1] = 0x00000000;
620 u32d[2] = 0x00000000;
621 u32d[3] = 0xFFFFFFFF;
622 for (j = 0; j < card->rct_size; j++)
623 ns_write_sram(card, j * 4, u32d, 4);
624
625 memset(card->vcmap, 0, sizeof(card->vcmap));
626
627 for (j = 0; j < NS_FRSCD_NUM; j++)
628 card->scd2vc[j] = NULL;
629
630 /* Initialize buffer levels */
631 card->sbnr.min = MIN_SB;
632 card->sbnr.init = NUM_SB;
633 card->sbnr.max = MAX_SB;
634 card->lbnr.min = MIN_LB;
635 card->lbnr.init = NUM_LB;
636 card->lbnr.max = MAX_LB;
637 card->iovnr.min = MIN_IOVB;
638 card->iovnr.init = NUM_IOVB;
639 card->iovnr.max = MAX_IOVB;
640 card->hbnr.min = MIN_HB;
641 card->hbnr.init = NUM_HB;
642 card->hbnr.max = MAX_HB;
643
644 card->sm_handle = NULL;
645 card->sm_addr = 0x00000000;
646 card->lg_handle = NULL;
647 card->lg_addr = 0x00000000;
648
649 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
650
651 idr_init(&card->idr);
652
653 /* Pre-allocate some huge buffers */
654 skb_queue_head_init(&card->hbpool.queue);
655 card->hbpool.count = 0;
656 for (j = 0; j < NUM_HB; j++) {
657 struct sk_buff *hb;
658 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
659 if (hb == NULL) {
660 printk
661 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
662 i, j, NUM_HB);
663 error = 13;
664 ns_init_card_error(card, error);
665 return error;
666 }
667 NS_PRV_BUFTYPE(hb) = BUF_NONE;
668 skb_queue_tail(&card->hbpool.queue, hb);
669 card->hbpool.count++;
670 }
671
672 /* Allocate large buffers */
673 skb_queue_head_init(&card->lbpool.queue);
674 card->lbpool.count = 0; /* Not used */
675 for (j = 0; j < NUM_LB; j++) {
676 struct sk_buff *lb;
677 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
678 if (lb == NULL) {
679 printk
680 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
681 i, j, NUM_LB);
682 error = 14;
683 ns_init_card_error(card, error);
684 return error;
685 }
686 NS_PRV_BUFTYPE(lb) = BUF_LG;
687 skb_queue_tail(&card->lbpool.queue, lb);
688 skb_reserve(lb, NS_SMBUFSIZE);
689 push_rxbufs(card, lb);
690 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
691 if (j == 1) {
692 card->rcbuf = lb;
693 card->rawcell = (struct ns_rcqe *) lb->data;
694 card->rawch = NS_PRV_DMA(lb);
695 }
696 }
697 /* Test for strange behaviour which leads to crashes */
698 if ((bcount =
699 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
700 printk
701 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
702 i, j, bcount);
703 error = 14;
704 ns_init_card_error(card, error);
705 return error;
706 }
707
708 /* Allocate small buffers */
709 skb_queue_head_init(&card->sbpool.queue);
710 card->sbpool.count = 0; /* Not used */
711 for (j = 0; j < NUM_SB; j++) {
712 struct sk_buff *sb;
713 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
714 if (sb == NULL) {
715 printk
716 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
717 i, j, NUM_SB);
718 error = 15;
719 ns_init_card_error(card, error);
720 return error;
721 }
722 NS_PRV_BUFTYPE(sb) = BUF_SM;
723 skb_queue_tail(&card->sbpool.queue, sb);
724 skb_reserve(sb, NS_AAL0_HEADER);
725 push_rxbufs(card, sb);
726 }
727 /* Test for strange behaviour which leads to crashes */
728 if ((bcount =
729 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
730 printk
731 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
732 i, j, bcount);
733 error = 15;
734 ns_init_card_error(card, error);
735 return error;
736 }
737
738 /* Allocate iovec buffers */
739 skb_queue_head_init(&card->iovpool.queue);
740 card->iovpool.count = 0;
741 for (j = 0; j < NUM_IOVB; j++) {
742 struct sk_buff *iovb;
743 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
744 if (iovb == NULL) {
745 printk
746 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
747 i, j, NUM_IOVB);
748 error = 16;
749 ns_init_card_error(card, error);
750 return error;
751 }
752 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
753 skb_queue_tail(&card->iovpool.queue, iovb);
754 card->iovpool.count++;
755 }
756
757 /* Configure NICStAR */
758 if (card->rct_size == 4096)
759 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
760 else /* (card->rct_size == 16384) */
761 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
762
763 card->efbie = 1;
764
765 /* Register device */
766 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
767 -1, NULL);
768 if (card->atmdev == NULL) {
769 printk("nicstar%d: can't register device.\n", i);
770 error = 17;
771 ns_init_card_error(card, error);
772 return error;
773 }
774
775 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
776 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
777 card->atmdev->esi, 6);
778 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
779 nicstar_read_eprom(card->membase,
780 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
781 card->atmdev->esi, 6);
782 }
783 }
784
785 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
786
787 card->atmdev->dev_data = card;
788 card->atmdev->ci_range.vpi_bits = card->vpibits;
789 card->atmdev->ci_range.vci_bits = card->vcibits;
790 card->atmdev->link_rate = card->max_pcr;
791 card->atmdev->phy = NULL;
792
793#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
794 if (card->max_pcr == ATM_OC3_PCR)
795 suni_init(card->atmdev);
796#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
797
798#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
799 if (card->max_pcr == ATM_25_PCR)
800 idt77105_init(card->atmdev);
801#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
802
803 if (card->atmdev->phy && card->atmdev->phy->start)
804 card->atmdev->phy->start(card->atmdev);
805
806 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
807 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
808 NS_CFG_PHYIE, card->membase + CFG);
809
810 num_cards++;
811
812 return error;
813}
814
815static void ns_init_card_error(ns_dev *card, int error)
816{
817 if (error >= 17) {
818 writel(0x00000000, card->membase + CFG);
819 }
820 if (error >= 16) {
821 struct sk_buff *iovb;
822 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
823 dev_kfree_skb_any(iovb);
824 }
825 if (error >= 15) {
826 struct sk_buff *sb;
827 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
828 dev_kfree_skb_any(sb);
829 free_scq(card, card->scq0, NULL);
830 }
831 if (error >= 14) {
832 struct sk_buff *lb;
833 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
834 dev_kfree_skb_any(lb);
835 }
836 if (error >= 13) {
837 struct sk_buff *hb;
838 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
839 dev_kfree_skb_any(hb);
840 }
841 if (error >= 12) {
842 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
843 card->rsq.org, card->rsq.dma);
844 }
845 if (error >= 11) {
846 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
847 card->tsq.org, card->tsq.dma);
848 }
849 if (error >= 10) {
850 free_irq(card->pcidev->irq, card);
851 }
852 if (error >= 4) {
853 iounmap(card->membase);
854 }
855 if (error >= 3) {
856 pci_disable_device(card->pcidev);
857 kfree(card);
858 }
859}
860
861static scq_info *get_scq(ns_dev *card, int size, u32 scd)
862{
863 scq_info *scq;
864
865 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
866 return NULL;
867
868 scq = kmalloc(sizeof(*scq), GFP_KERNEL);
869 if (!scq)
870 return NULL;
871 scq->org = dma_alloc_coherent(&card->pcidev->dev,
872 2 * size, &scq->dma, GFP_KERNEL);
873 if (!scq->org) {
874 kfree(scq);
875 return NULL;
876 }
877 scq->skb = kcalloc(size / NS_SCQE_SIZE, sizeof(*scq->skb),
878 GFP_KERNEL);
879 if (!scq->skb) {
880 dma_free_coherent(&card->pcidev->dev,
881 2 * size, scq->org, scq->dma);
882 kfree(scq);
883 return NULL;
884 }
885 scq->num_entries = size / NS_SCQE_SIZE;
886 scq->base = PTR_ALIGN(scq->org, size);
887 scq->next = scq->base;
888 scq->last = scq->base + (scq->num_entries - 1);
889 scq->tail = scq->last;
890 scq->scd = scd;
891 scq->tbd_count = 0;
892 init_waitqueue_head(&scq->scqfull_waitq);
893 scq->full = 0;
894 spin_lock_init(&scq->lock);
895
896 return scq;
897}
898
899/* For variable rate SCQ vcc must be NULL */
900static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
901{
902 int i;
903
904 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
905 for (i = 0; i < scq->num_entries; i++) {
906 if (scq->skb[i] != NULL) {
907 vcc = ATM_SKB(scq->skb[i])->vcc;
908 if (vcc->pop != NULL)
909 vcc->pop(vcc, scq->skb[i]);
910 else
911 dev_kfree_skb_any(scq->skb[i]);
912 }
913 } else { /* vcc must be != NULL */
914
915 if (vcc == NULL) {
916 printk
917 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
918 for (i = 0; i < scq->num_entries; i++)
919 dev_kfree_skb_any(scq->skb[i]);
920 } else
921 for (i = 0; i < scq->num_entries; i++) {
922 if (scq->skb[i] != NULL) {
923 if (vcc->pop != NULL)
924 vcc->pop(vcc, scq->skb[i]);
925 else
926 dev_kfree_skb_any(scq->skb[i]);
927 }
928 }
929 }
930 kfree(scq->skb);
931 dma_free_coherent(&card->pcidev->dev,
932 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
933 VBR_SCQSIZE : CBR_SCQSIZE),
934 scq->org, scq->dma);
935 kfree(scq);
936}
937
938/* The handles passed must be pointers to the sk_buff containing the small
939 or large buffer(s) cast to u32. */
940static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
941{
942 struct sk_buff *handle1, *handle2;
943 int id1, id2;
944 u32 addr1, addr2;
945 u32 stat;
946 unsigned long flags;
947
948 /* *BARF* */
949 handle2 = NULL;
950 addr2 = 0;
951 handle1 = skb;
952 addr1 = dma_map_single(&card->pcidev->dev,
953 skb->data,
954 (NS_PRV_BUFTYPE(skb) == BUF_SM
955 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
956 DMA_TO_DEVICE);
957 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
958
959#ifdef GENERAL_DEBUG
960 if (!addr1)
961 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
962 card->index);
963#endif /* GENERAL_DEBUG */
964
965 stat = readl(card->membase + STAT);
966 card->sbfqc = ns_stat_sfbqc_get(stat);
967 card->lbfqc = ns_stat_lfbqc_get(stat);
968 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
969 if (!addr2) {
970 if (card->sm_addr) {
971 addr2 = card->sm_addr;
972 handle2 = card->sm_handle;
973 card->sm_addr = 0x00000000;
974 card->sm_handle = NULL;
975 } else { /* (!sm_addr) */
976
977 card->sm_addr = addr1;
978 card->sm_handle = handle1;
979 }
980 }
981 } else { /* buf_type == BUF_LG */
982
983 if (!addr2) {
984 if (card->lg_addr) {
985 addr2 = card->lg_addr;
986 handle2 = card->lg_handle;
987 card->lg_addr = 0x00000000;
988 card->lg_handle = NULL;
989 } else { /* (!lg_addr) */
990
991 card->lg_addr = addr1;
992 card->lg_handle = handle1;
993 }
994 }
995 }
996
997 if (addr2) {
998 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
999 if (card->sbfqc >= card->sbnr.max) {
1000 skb_unlink(handle1, &card->sbpool.queue);
1001 dev_kfree_skb_any(handle1);
1002 skb_unlink(handle2, &card->sbpool.queue);
1003 dev_kfree_skb_any(handle2);
1004 return;
1005 } else
1006 card->sbfqc += 2;
1007 } else { /* (buf_type == BUF_LG) */
1008
1009 if (card->lbfqc >= card->lbnr.max) {
1010 skb_unlink(handle1, &card->lbpool.queue);
1011 dev_kfree_skb_any(handle1);
1012 skb_unlink(handle2, &card->lbpool.queue);
1013 dev_kfree_skb_any(handle2);
1014 return;
1015 } else
1016 card->lbfqc += 2;
1017 }
1018
1019 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1020 if (id1 < 0)
1021 goto out;
1022
1023 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1024 if (id2 < 0)
1025 goto out;
1026
1027 spin_lock_irqsave(&card->res_lock, flags);
1028 while (CMD_BUSY(card)) ;
1029 writel(addr2, card->membase + DR3);
1030 writel(id2, card->membase + DR2);
1031 writel(addr1, card->membase + DR1);
1032 writel(id1, card->membase + DR0);
1033 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1034 card->membase + CMD);
1035 spin_unlock_irqrestore(&card->res_lock, flags);
1036
1037 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1038 card->index,
1039 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1040 addr1, addr2);
1041 }
1042
1043 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1044 card->lbfqc >= card->lbnr.min) {
1045 card->efbie = 1;
1046 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1047 card->membase + CFG);
1048 }
1049
1050out:
1051 return;
1052}
1053
1054static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1055{
1056 u32 stat_r;
1057 ns_dev *card;
1058 struct atm_dev *dev;
1059 unsigned long flags;
1060
1061 card = (ns_dev *) dev_id;
1062 dev = card->atmdev;
1063 card->intcnt++;
1064
1065 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1066
1067 spin_lock_irqsave(&card->int_lock, flags);
1068
1069 stat_r = readl(card->membase + STAT);
1070
1071 /* Transmit Status Indicator has been written to T. S. Queue */
1072 if (stat_r & NS_STAT_TSIF) {
1073 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1074 process_tsq(card);
1075 writel(NS_STAT_TSIF, card->membase + STAT);
1076 }
1077
1078 /* Incomplete CS-PDU has been transmitted */
1079 if (stat_r & NS_STAT_TXICP) {
1080 writel(NS_STAT_TXICP, card->membase + STAT);
1081 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1082 card->index);
1083 }
1084
1085 /* Transmit Status Queue 7/8 full */
1086 if (stat_r & NS_STAT_TSQF) {
1087 writel(NS_STAT_TSQF, card->membase + STAT);
1088 PRINTK("nicstar%d: TSQ full.\n", card->index);
1089 process_tsq(card);
1090 }
1091
1092 /* Timer overflow */
1093 if (stat_r & NS_STAT_TMROF) {
1094 writel(NS_STAT_TMROF, card->membase + STAT);
1095 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1096 }
1097
1098 /* PHY device interrupt signal active */
1099 if (stat_r & NS_STAT_PHYI) {
1100 writel(NS_STAT_PHYI, card->membase + STAT);
1101 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1102 if (dev->phy && dev->phy->interrupt) {
1103 dev->phy->interrupt(dev);
1104 }
1105 }
1106
1107 /* Small Buffer Queue is full */
1108 if (stat_r & NS_STAT_SFBQF) {
1109 writel(NS_STAT_SFBQF, card->membase + STAT);
1110 printk("nicstar%d: Small free buffer queue is full.\n",
1111 card->index);
1112 }
1113
1114 /* Large Buffer Queue is full */
1115 if (stat_r & NS_STAT_LFBQF) {
1116 writel(NS_STAT_LFBQF, card->membase + STAT);
1117 printk("nicstar%d: Large free buffer queue is full.\n",
1118 card->index);
1119 }
1120
1121 /* Receive Status Queue is full */
1122 if (stat_r & NS_STAT_RSQF) {
1123 writel(NS_STAT_RSQF, card->membase + STAT);
1124 printk("nicstar%d: RSQ full.\n", card->index);
1125 process_rsq(card);
1126 }
1127
1128 /* Complete CS-PDU received */
1129 if (stat_r & NS_STAT_EOPDU) {
1130 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1131 process_rsq(card);
1132 writel(NS_STAT_EOPDU, card->membase + STAT);
1133 }
1134
1135 /* Raw cell received */
1136 if (stat_r & NS_STAT_RAWCF) {
1137 writel(NS_STAT_RAWCF, card->membase + STAT);
1138#ifndef RCQ_SUPPORT
1139 printk("nicstar%d: Raw cell received and no support yet...\n",
1140 card->index);
1141#endif /* RCQ_SUPPORT */
1142 /* NOTE: the following procedure may keep a raw cell pending until the
1143 next interrupt. As this preliminary support is only meant to
1144 avoid buffer leakage, this is not an issue. */
1145 while (readl(card->membase + RAWCT) != card->rawch) {
1146
1147 if (ns_rcqe_islast(card->rawcell)) {
1148 struct sk_buff *oldbuf;
1149
1150 oldbuf = card->rcbuf;
1151 card->rcbuf = idr_find(&card->idr,
1152 ns_rcqe_nextbufhandle(card->rawcell));
1153 card->rawch = NS_PRV_DMA(card->rcbuf);
1154 card->rawcell = (struct ns_rcqe *)
1155 card->rcbuf->data;
1156 recycle_rx_buf(card, oldbuf);
1157 } else {
1158 card->rawch += NS_RCQE_SIZE;
1159 card->rawcell++;
1160 }
1161 }
1162 }
1163
1164 /* Small buffer queue is empty */
1165 if (stat_r & NS_STAT_SFBQE) {
1166 int i;
1167 struct sk_buff *sb;
1168
1169 writel(NS_STAT_SFBQE, card->membase + STAT);
1170 printk("nicstar%d: Small free buffer queue empty.\n",
1171 card->index);
1172 for (i = 0; i < card->sbnr.min; i++) {
1173 sb = dev_alloc_skb(NS_SMSKBSIZE);
1174 if (sb == NULL) {
1175 writel(readl(card->membase + CFG) &
1176 ~NS_CFG_EFBIE, card->membase + CFG);
1177 card->efbie = 0;
1178 break;
1179 }
1180 NS_PRV_BUFTYPE(sb) = BUF_SM;
1181 skb_queue_tail(&card->sbpool.queue, sb);
1182 skb_reserve(sb, NS_AAL0_HEADER);
1183 push_rxbufs(card, sb);
1184 }
1185 card->sbfqc = i;
1186 process_rsq(card);
1187 }
1188
1189 /* Large buffer queue empty */
1190 if (stat_r & NS_STAT_LFBQE) {
1191 int i;
1192 struct sk_buff *lb;
1193
1194 writel(NS_STAT_LFBQE, card->membase + STAT);
1195 printk("nicstar%d: Large free buffer queue empty.\n",
1196 card->index);
1197 for (i = 0; i < card->lbnr.min; i++) {
1198 lb = dev_alloc_skb(NS_LGSKBSIZE);
1199 if (lb == NULL) {
1200 writel(readl(card->membase + CFG) &
1201 ~NS_CFG_EFBIE, card->membase + CFG);
1202 card->efbie = 0;
1203 break;
1204 }
1205 NS_PRV_BUFTYPE(lb) = BUF_LG;
1206 skb_queue_tail(&card->lbpool.queue, lb);
1207 skb_reserve(lb, NS_SMBUFSIZE);
1208 push_rxbufs(card, lb);
1209 }
1210 card->lbfqc = i;
1211 process_rsq(card);
1212 }
1213
1214 /* Receive Status Queue is 7/8 full */
1215 if (stat_r & NS_STAT_RSQAF) {
1216 writel(NS_STAT_RSQAF, card->membase + STAT);
1217 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1218 process_rsq(card);
1219 }
1220
1221 spin_unlock_irqrestore(&card->int_lock, flags);
1222 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1223 return IRQ_HANDLED;
1224}
1225
1226static int ns_open(struct atm_vcc *vcc)
1227{
1228 ns_dev *card;
1229 vc_map *vc;
1230 unsigned long tmpl, modl;
1231 int tcr, tcra; /* target cell rate, and absolute value */
1232 int n = 0; /* Number of entries in the TST. Initialized to remove
1233 the compiler warning. */
1234 u32 u32d[4];
1235 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1236 warning. How I wish compilers were clever enough to
1237 tell which variables can truly be used
1238 uninitialized... */
1239 int inuse; /* tx or rx vc already in use by another vcc */
1240 short vpi = vcc->vpi;
1241 int vci = vcc->vci;
1242
1243 card = (ns_dev *) vcc->dev->dev_data;
1244 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1245 vci);
1246 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1247 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1248 return -EINVAL;
1249 }
1250
1251 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1252 vcc->dev_data = vc;
1253
1254 inuse = 0;
1255 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1256 inuse = 1;
1257 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1258 inuse += 2;
1259 if (inuse) {
1260 printk("nicstar%d: %s vci already in use.\n", card->index,
1261 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1262 return -EINVAL;
1263 }
1264
1265 set_bit(ATM_VF_ADDR, &vcc->flags);
1266
1267 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1268 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1269 needed to do that. */
1270 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1271 scq_info *scq;
1272
1273 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1274 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1275 /* Check requested cell rate and availability of SCD */
1276 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1277 && vcc->qos.txtp.min_pcr == 0) {
1278 PRINTK
1279 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1280 card->index);
1281 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1282 clear_bit(ATM_VF_ADDR, &vcc->flags);
1283 return -EINVAL;
1284 }
1285
1286 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1287 tcra = tcr >= 0 ? tcr : -tcr;
1288
1289 PRINTK("nicstar%d: target cell rate = %d.\n",
1290 card->index, vcc->qos.txtp.max_pcr);
1291
1292 tmpl =
1293 (unsigned long)tcra *(unsigned long)
1294 NS_TST_NUM_ENTRIES;
1295 modl = tmpl % card->max_pcr;
1296
1297 n = (int)(tmpl / card->max_pcr);
1298 if (tcr > 0) {
1299 if (modl > 0)
1300 n++;
1301 } else if (tcr == 0) {
1302 if ((n =
1303 (card->tst_free_entries -
1304 NS_TST_RESERVED)) <= 0) {
1305 PRINTK
1306 ("nicstar%d: no CBR bandwidth free.\n",
1307 card->index);
1308 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1309 clear_bit(ATM_VF_ADDR, &vcc->flags);
1310 return -EINVAL;
1311 }
1312 }
1313
1314 if (n == 0) {
1315 printk
1316 ("nicstar%d: selected bandwidth < granularity.\n",
1317 card->index);
1318 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1319 clear_bit(ATM_VF_ADDR, &vcc->flags);
1320 return -EINVAL;
1321 }
1322
1323 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1324 PRINTK
1325 ("nicstar%d: not enough free CBR bandwidth.\n",
1326 card->index);
1327 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1328 clear_bit(ATM_VF_ADDR, &vcc->flags);
1329 return -EINVAL;
1330 } else
1331 card->tst_free_entries -= n;
1332
1333 XPRINTK("nicstar%d: writing %d tst entries.\n",
1334 card->index, n);
1335 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1336 if (card->scd2vc[frscdi] == NULL) {
1337 card->scd2vc[frscdi] = vc;
1338 break;
1339 }
1340 }
1341 if (frscdi == NS_FRSCD_NUM) {
1342 PRINTK
1343 ("nicstar%d: no SCD available for CBR channel.\n",
1344 card->index);
1345 card->tst_free_entries += n;
1346 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1347 clear_bit(ATM_VF_ADDR, &vcc->flags);
1348 return -EBUSY;
1349 }
1350
1351 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1352
1353 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1354 if (scq == NULL) {
1355 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1356 card->index);
1357 card->scd2vc[frscdi] = NULL;
1358 card->tst_free_entries += n;
1359 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1360 clear_bit(ATM_VF_ADDR, &vcc->flags);
1361 return -ENOMEM;
1362 }
1363 vc->scq = scq;
1364 u32d[0] = scq_virt_to_bus(scq, scq->base);
1365 u32d[1] = (u32) 0x00000000;
1366 u32d[2] = (u32) 0xffffffff;
1367 u32d[3] = (u32) 0x00000000;
1368 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1369
1370 fill_tst(card, n, vc);
1371 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1372 vc->cbr_scd = 0x00000000;
1373 vc->scq = card->scq0;
1374 }
1375
1376 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1377 vc->tx = 1;
1378 vc->tx_vcc = vcc;
1379 vc->tbd_count = 0;
1380 }
1381 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1382 u32 status;
1383
1384 vc->rx = 1;
1385 vc->rx_vcc = vcc;
1386 vc->rx_iov = NULL;
1387
1388 /* Open the connection in hardware */
1389 if (vcc->qos.aal == ATM_AAL5)
1390 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1391 else /* vcc->qos.aal == ATM_AAL0 */
1392 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1393#ifdef RCQ_SUPPORT
1394 status |= NS_RCTE_RAWCELLINTEN;
1395#endif /* RCQ_SUPPORT */
1396 ns_write_sram(card,
1397 NS_RCT +
1398 (vpi << card->vcibits | vci) *
1399 NS_RCT_ENTRY_SIZE, &status, 1);
1400 }
1401
1402 }
1403
1404 set_bit(ATM_VF_READY, &vcc->flags);
1405 return 0;
1406}
1407
1408static void ns_close(struct atm_vcc *vcc)
1409{
1410 vc_map *vc;
1411 ns_dev *card;
1412 u32 data;
1413 int i;
1414
1415 vc = vcc->dev_data;
1416 card = vcc->dev->dev_data;
1417 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1418 (int)vcc->vpi, vcc->vci);
1419
1420 clear_bit(ATM_VF_READY, &vcc->flags);
1421
1422 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1423 u32 addr;
1424 unsigned long flags;
1425
1426 addr =
1427 NS_RCT +
1428 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1429 spin_lock_irqsave(&card->res_lock, flags);
1430 while (CMD_BUSY(card)) ;
1431 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1432 card->membase + CMD);
1433 spin_unlock_irqrestore(&card->res_lock, flags);
1434
1435 vc->rx = 0;
1436 if (vc->rx_iov != NULL) {
1437 struct sk_buff *iovb;
1438 u32 stat;
1439
1440 stat = readl(card->membase + STAT);
1441 card->sbfqc = ns_stat_sfbqc_get(stat);
1442 card->lbfqc = ns_stat_lfbqc_get(stat);
1443
1444 PRINTK
1445 ("nicstar%d: closing a VC with pending rx buffers.\n",
1446 card->index);
1447 iovb = vc->rx_iov;
1448 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1449 NS_PRV_IOVCNT(iovb));
1450 NS_PRV_IOVCNT(iovb) = 0;
1451 spin_lock_irqsave(&card->int_lock, flags);
1452 recycle_iov_buf(card, iovb);
1453 spin_unlock_irqrestore(&card->int_lock, flags);
1454 vc->rx_iov = NULL;
1455 }
1456 }
1457
1458 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1459 vc->tx = 0;
1460 }
1461
1462 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1463 unsigned long flags;
1464 ns_scqe *scqep;
1465 scq_info *scq;
1466
1467 scq = vc->scq;
1468
1469 for (;;) {
1470 spin_lock_irqsave(&scq->lock, flags);
1471 scqep = scq->next;
1472 if (scqep == scq->base)
1473 scqep = scq->last;
1474 else
1475 scqep--;
1476 if (scqep == scq->tail) {
1477 spin_unlock_irqrestore(&scq->lock, flags);
1478 break;
1479 }
1480 /* If the last entry is not a TSR, place one in the SCQ in order to
1481 be able to completely drain it and then close. */
1482 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1483 ns_scqe tsr;
1484 u32 scdi, scqi;
1485 u32 data;
1486 int index;
1487
1488 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1489 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1490 scqi = scq->next - scq->base;
1491 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1492 tsr.word_3 = 0x00000000;
1493 tsr.word_4 = 0x00000000;
1494 *scq->next = tsr;
1495 index = (int)scqi;
1496 scq->skb[index] = NULL;
1497 if (scq->next == scq->last)
1498 scq->next = scq->base;
1499 else
1500 scq->next++;
1501 data = scq_virt_to_bus(scq, scq->next);
1502 ns_write_sram(card, scq->scd, &data, 1);
1503 }
1504 spin_unlock_irqrestore(&scq->lock, flags);
1505 schedule();
1506 }
1507
1508 /* Free all TST entries */
1509 data = NS_TST_OPCODE_VARIABLE;
1510 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1511 if (card->tste2vc[i] == vc) {
1512 ns_write_sram(card, card->tst_addr + i, &data,
1513 1);
1514 card->tste2vc[i] = NULL;
1515 card->tst_free_entries++;
1516 }
1517 }
1518
1519 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1520 free_scq(card, vc->scq, vcc);
1521 }
1522
1523 /* remove all references to vcc before deleting it */
1524 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1525 unsigned long flags;
1526 scq_info *scq = card->scq0;
1527
1528 spin_lock_irqsave(&scq->lock, flags);
1529
1530 for (i = 0; i < scq->num_entries; i++) {
1531 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1532 ATM_SKB(scq->skb[i])->vcc = NULL;
1533 atm_return(vcc, scq->skb[i]->truesize);
1534 PRINTK
1535 ("nicstar: deleted pending vcc mapping\n");
1536 }
1537 }
1538
1539 spin_unlock_irqrestore(&scq->lock, flags);
1540 }
1541
1542 vcc->dev_data = NULL;
1543 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1544 clear_bit(ATM_VF_ADDR, &vcc->flags);
1545
1546#ifdef RX_DEBUG
1547 {
1548 u32 stat, cfg;
1549 stat = readl(card->membase + STAT);
1550 cfg = readl(card->membase + CFG);
1551 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1552 printk
1553 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1554 card->tsq.base, card->tsq.next,
1555 card->tsq.last, readl(card->membase + TSQT));
1556 printk
1557 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1558 card->rsq.base, card->rsq.next,
1559 card->rsq.last, readl(card->membase + RSQT));
1560 printk("Empty free buffer queue interrupt %s \n",
1561 card->efbie ? "enabled" : "disabled");
1562 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1563 ns_stat_sfbqc_get(stat), card->sbpool.count,
1564 ns_stat_lfbqc_get(stat), card->lbpool.count);
1565 printk("hbpool.count = %d iovpool.count = %d \n",
1566 card->hbpool.count, card->iovpool.count);
1567 }
1568#endif /* RX_DEBUG */
1569}
1570
1571static void fill_tst(ns_dev * card, int n, vc_map * vc)
1572{
1573 u32 new_tst;
1574 unsigned long cl;
1575 int e, r;
1576 u32 data;
1577
1578 /* It would be very complicated to keep the two TSTs synchronized while
1579 assuring that writes are only made to the inactive TST. So, for now I
1580 will use only one TST. If problems occur, I will change this again */
1581
1582 new_tst = card->tst_addr;
1583
1584 /* Fill procedure */
1585
1586 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1587 if (card->tste2vc[e] == NULL)
1588 break;
1589 }
1590 if (e == NS_TST_NUM_ENTRIES) {
1591 printk("nicstar%d: No free TST entries found. \n", card->index);
1592 return;
1593 }
1594
1595 r = n;
1596 cl = NS_TST_NUM_ENTRIES;
1597 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1598
1599 while (r > 0) {
1600 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1601 card->tste2vc[e] = vc;
1602 ns_write_sram(card, new_tst + e, &data, 1);
1603 cl -= NS_TST_NUM_ENTRIES;
1604 r--;
1605 }
1606
1607 if (++e == NS_TST_NUM_ENTRIES) {
1608 e = 0;
1609 }
1610 cl += n;
1611 }
1612
1613 /* End of fill procedure */
1614
1615 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1616 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1617 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1618 card->tst_addr = new_tst;
1619}
1620
1621static int _ns_send(struct atm_vcc *vcc, struct sk_buff *skb, bool may_sleep)
1622{
1623 ns_dev *card;
1624 vc_map *vc;
1625 scq_info *scq;
1626 unsigned long buflen;
1627 ns_scqe scqe;
1628 u32 flags; /* TBD flags, not CPU flags */
1629
1630 card = vcc->dev->dev_data;
1631 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1632 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1633 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1634 card->index);
1635 atomic_inc(&vcc->stats->tx_err);
1636 dev_kfree_skb_any(skb);
1637 return -EINVAL;
1638 }
1639
1640 if (!vc->tx) {
1641 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1642 card->index);
1643 atomic_inc(&vcc->stats->tx_err);
1644 dev_kfree_skb_any(skb);
1645 return -EINVAL;
1646 }
1647
1648 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1649 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1650 card->index);
1651 atomic_inc(&vcc->stats->tx_err);
1652 dev_kfree_skb_any(skb);
1653 return -EINVAL;
1654 }
1655
1656 if (skb_shinfo(skb)->nr_frags != 0) {
1657 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1658 atomic_inc(&vcc->stats->tx_err);
1659 dev_kfree_skb_any(skb);
1660 return -EINVAL;
1661 }
1662
1663 ATM_SKB(skb)->vcc = vcc;
1664
1665 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1666 skb->len, DMA_TO_DEVICE);
1667
1668 if (vcc->qos.aal == ATM_AAL5) {
1669 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1670 flags = NS_TBD_AAL5;
1671 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1672 scqe.word_3 = cpu_to_le32(skb->len);
1673 scqe.word_4 =
1674 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1675 ATM_SKB(skb)->
1676 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1677 flags |= NS_TBD_EOPDU;
1678 } else { /* (vcc->qos.aal == ATM_AAL0) */
1679
1680 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1681 flags = NS_TBD_AAL0;
1682 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1683 scqe.word_3 = cpu_to_le32(0x00000000);
1684 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1685 flags |= NS_TBD_EOPDU;
1686 scqe.word_4 =
1687 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1688 /* Force the VPI/VCI to be the same as in VCC struct */
1689 scqe.word_4 |=
1690 cpu_to_le32((((u32) vcc->
1691 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1692 vci) <<
1693 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1694 }
1695
1696 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1697 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1698 scq = ((vc_map *) vcc->dev_data)->scq;
1699 } else {
1700 scqe.word_1 =
1701 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1702 scq = card->scq0;
1703 }
1704
1705 if (push_scqe(card, vc, scq, &scqe, skb, may_sleep) != 0) {
1706 atomic_inc(&vcc->stats->tx_err);
1707 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1708 DMA_TO_DEVICE);
1709 dev_kfree_skb_any(skb);
1710 return -EIO;
1711 }
1712 atomic_inc(&vcc->stats->tx);
1713
1714 return 0;
1715}
1716
1717static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1718{
1719 return _ns_send(vcc, skb, true);
1720}
1721
1722static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb)
1723{
1724 return _ns_send(vcc, skb, false);
1725}
1726
1727static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1728 struct sk_buff *skb, bool may_sleep)
1729{
1730 unsigned long flags;
1731 ns_scqe tsr;
1732 u32 scdi, scqi;
1733 int scq_is_vbr;
1734 u32 data;
1735 int index;
1736
1737 spin_lock_irqsave(&scq->lock, flags);
1738 while (scq->tail == scq->next) {
1739 if (!may_sleep) {
1740 spin_unlock_irqrestore(&scq->lock, flags);
1741 printk("nicstar%d: Error pushing TBD.\n", card->index);
1742 return 1;
1743 }
1744
1745 scq->full = 1;
1746 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1747 scq->tail != scq->next,
1748 scq->lock,
1749 SCQFULL_TIMEOUT);
1750
1751 if (scq->full) {
1752 spin_unlock_irqrestore(&scq->lock, flags);
1753 printk("nicstar%d: Timeout pushing TBD.\n",
1754 card->index);
1755 return 1;
1756 }
1757 }
1758 *scq->next = *tbd;
1759 index = (int)(scq->next - scq->base);
1760 scq->skb[index] = skb;
1761 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1762 card->index, skb, index);
1763 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1764 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1765 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1766 scq->next);
1767 if (scq->next == scq->last)
1768 scq->next = scq->base;
1769 else
1770 scq->next++;
1771
1772 vc->tbd_count++;
1773 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1774 scq->tbd_count++;
1775 scq_is_vbr = 1;
1776 } else
1777 scq_is_vbr = 0;
1778
1779 if (vc->tbd_count >= MAX_TBD_PER_VC
1780 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1781 int has_run = 0;
1782
1783 while (scq->tail == scq->next) {
1784 if (!may_sleep) {
1785 data = scq_virt_to_bus(scq, scq->next);
1786 ns_write_sram(card, scq->scd, &data, 1);
1787 spin_unlock_irqrestore(&scq->lock, flags);
1788 printk("nicstar%d: Error pushing TSR.\n",
1789 card->index);
1790 return 0;
1791 }
1792
1793 scq->full = 1;
1794 if (has_run++)
1795 break;
1796 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1797 scq->tail != scq->next,
1798 scq->lock,
1799 SCQFULL_TIMEOUT);
1800 }
1801
1802 if (!scq->full) {
1803 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1804 if (scq_is_vbr)
1805 scdi = NS_TSR_SCDISVBR;
1806 else
1807 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1808 scqi = scq->next - scq->base;
1809 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1810 tsr.word_3 = 0x00000000;
1811 tsr.word_4 = 0x00000000;
1812
1813 *scq->next = tsr;
1814 index = (int)scqi;
1815 scq->skb[index] = NULL;
1816 XPRINTK
1817 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1818 card->index, le32_to_cpu(tsr.word_1),
1819 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1820 le32_to_cpu(tsr.word_4), scq->next);
1821 if (scq->next == scq->last)
1822 scq->next = scq->base;
1823 else
1824 scq->next++;
1825 vc->tbd_count = 0;
1826 scq->tbd_count = 0;
1827 } else
1828 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1829 card->index);
1830 }
1831 data = scq_virt_to_bus(scq, scq->next);
1832 ns_write_sram(card, scq->scd, &data, 1);
1833
1834 spin_unlock_irqrestore(&scq->lock, flags);
1835
1836 return 0;
1837}
1838
1839static void process_tsq(ns_dev * card)
1840{
1841 u32 scdi;
1842 scq_info *scq;
1843 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1844 int serviced_entries; /* flag indicating at least on entry was serviced */
1845
1846 serviced_entries = 0;
1847
1848 if (card->tsq.next == card->tsq.last)
1849 one_ahead = card->tsq.base;
1850 else
1851 one_ahead = card->tsq.next + 1;
1852
1853 if (one_ahead == card->tsq.last)
1854 two_ahead = card->tsq.base;
1855 else
1856 two_ahead = one_ahead + 1;
1857
1858 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1859 !ns_tsi_isempty(two_ahead))
1860 /* At most two empty, as stated in the 77201 errata */
1861 {
1862 serviced_entries = 1;
1863
1864 /* Skip the one or two possible empty entries */
1865 while (ns_tsi_isempty(card->tsq.next)) {
1866 if (card->tsq.next == card->tsq.last)
1867 card->tsq.next = card->tsq.base;
1868 else
1869 card->tsq.next++;
1870 }
1871
1872 if (!ns_tsi_tmrof(card->tsq.next)) {
1873 scdi = ns_tsi_getscdindex(card->tsq.next);
1874 if (scdi == NS_TSI_SCDISVBR)
1875 scq = card->scq0;
1876 else {
1877 if (card->scd2vc[scdi] == NULL) {
1878 printk
1879 ("nicstar%d: could not find VC from SCD index.\n",
1880 card->index);
1881 ns_tsi_init(card->tsq.next);
1882 return;
1883 }
1884 scq = card->scd2vc[scdi]->scq;
1885 }
1886 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1887 scq->full = 0;
1888 wake_up_interruptible(&(scq->scqfull_waitq));
1889 }
1890
1891 ns_tsi_init(card->tsq.next);
1892 previous = card->tsq.next;
1893 if (card->tsq.next == card->tsq.last)
1894 card->tsq.next = card->tsq.base;
1895 else
1896 card->tsq.next++;
1897
1898 if (card->tsq.next == card->tsq.last)
1899 one_ahead = card->tsq.base;
1900 else
1901 one_ahead = card->tsq.next + 1;
1902
1903 if (one_ahead == card->tsq.last)
1904 two_ahead = card->tsq.base;
1905 else
1906 two_ahead = one_ahead + 1;
1907 }
1908
1909 if (serviced_entries)
1910 writel(PTR_DIFF(previous, card->tsq.base),
1911 card->membase + TSQH);
1912}
1913
1914static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1915{
1916 struct atm_vcc *vcc;
1917 struct sk_buff *skb;
1918 int i;
1919 unsigned long flags;
1920
1921 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1922 card->index, scq, pos);
1923 if (pos >= scq->num_entries) {
1924 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1925 return;
1926 }
1927
1928 spin_lock_irqsave(&scq->lock, flags);
1929 i = (int)(scq->tail - scq->base);
1930 if (++i == scq->num_entries)
1931 i = 0;
1932 while (i != pos) {
1933 skb = scq->skb[i];
1934 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1935 card->index, skb, i);
1936 if (skb != NULL) {
1937 dma_unmap_single(&card->pcidev->dev,
1938 NS_PRV_DMA(skb),
1939 skb->len,
1940 DMA_TO_DEVICE);
1941 vcc = ATM_SKB(skb)->vcc;
1942 if (vcc && vcc->pop != NULL) {
1943 vcc->pop(vcc, skb);
1944 } else {
1945 dev_kfree_skb_irq(skb);
1946 }
1947 scq->skb[i] = NULL;
1948 }
1949 if (++i == scq->num_entries)
1950 i = 0;
1951 }
1952 scq->tail = scq->base + pos;
1953 spin_unlock_irqrestore(&scq->lock, flags);
1954}
1955
1956static void process_rsq(ns_dev * card)
1957{
1958 ns_rsqe *previous;
1959
1960 if (!ns_rsqe_valid(card->rsq.next))
1961 return;
1962 do {
1963 dequeue_rx(card, card->rsq.next);
1964 ns_rsqe_init(card->rsq.next);
1965 previous = card->rsq.next;
1966 if (card->rsq.next == card->rsq.last)
1967 card->rsq.next = card->rsq.base;
1968 else
1969 card->rsq.next++;
1970 } while (ns_rsqe_valid(card->rsq.next));
1971 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1972}
1973
1974static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1975{
1976 u32 vpi, vci;
1977 vc_map *vc;
1978 struct sk_buff *iovb;
1979 struct iovec *iov;
1980 struct atm_vcc *vcc;
1981 struct sk_buff *skb;
1982 unsigned short aal5_len;
1983 int len;
1984 u32 stat;
1985 u32 id;
1986
1987 stat = readl(card->membase + STAT);
1988 card->sbfqc = ns_stat_sfbqc_get(stat);
1989 card->lbfqc = ns_stat_lfbqc_get(stat);
1990
1991 id = le32_to_cpu(rsqe->buffer_handle);
1992 skb = idr_remove(&card->idr, id);
1993 if (!skb) {
1994 RXPRINTK(KERN_ERR
1995 "nicstar%d: skb not found!\n", card->index);
1996 return;
1997 }
1998 dma_sync_single_for_cpu(&card->pcidev->dev,
1999 NS_PRV_DMA(skb),
2000 (NS_PRV_BUFTYPE(skb) == BUF_SM
2001 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2002 DMA_FROM_DEVICE);
2003 dma_unmap_single(&card->pcidev->dev,
2004 NS_PRV_DMA(skb),
2005 (NS_PRV_BUFTYPE(skb) == BUF_SM
2006 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2007 DMA_FROM_DEVICE);
2008 vpi = ns_rsqe_vpi(rsqe);
2009 vci = ns_rsqe_vci(rsqe);
2010 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2011 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2012 card->index, vpi, vci);
2013 recycle_rx_buf(card, skb);
2014 return;
2015 }
2016
2017 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2018 if (!vc->rx) {
2019 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2020 card->index, vpi, vci);
2021 recycle_rx_buf(card, skb);
2022 return;
2023 }
2024
2025 vcc = vc->rx_vcc;
2026
2027 if (vcc->qos.aal == ATM_AAL0) {
2028 struct sk_buff *sb;
2029 unsigned char *cell;
2030 int i;
2031
2032 cell = skb->data;
2033 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2034 sb = dev_alloc_skb(NS_SMSKBSIZE);
2035 if (!sb) {
2036 printk
2037 ("nicstar%d: Can't allocate buffers for aal0.\n",
2038 card->index);
2039 atomic_add(i, &vcc->stats->rx_drop);
2040 break;
2041 }
2042 if (!atm_charge(vcc, sb->truesize)) {
2043 RXPRINTK
2044 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2045 card->index);
2046 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2047 dev_kfree_skb_any(sb);
2048 break;
2049 }
2050 /* Rebuild the header */
2051 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2052 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2053 if (i == 1 && ns_rsqe_eopdu(rsqe))
2054 *((u32 *) sb->data) |= 0x00000002;
2055 skb_put(sb, NS_AAL0_HEADER);
2056 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2057 skb_put(sb, ATM_CELL_PAYLOAD);
2058 ATM_SKB(sb)->vcc = vcc;
2059 __net_timestamp(sb);
2060 vcc->push(vcc, sb);
2061 atomic_inc(&vcc->stats->rx);
2062 cell += ATM_CELL_PAYLOAD;
2063 }
2064
2065 recycle_rx_buf(card, skb);
2066 return;
2067 }
2068
2069 /* To reach this point, the AAL layer can only be AAL5 */
2070
2071 if ((iovb = vc->rx_iov) == NULL) {
2072 iovb = skb_dequeue(&(card->iovpool.queue));
2073 if (iovb == NULL) { /* No buffers in the queue */
2074 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2075 if (iovb == NULL) {
2076 printk("nicstar%d: Out of iovec buffers.\n",
2077 card->index);
2078 atomic_inc(&vcc->stats->rx_drop);
2079 recycle_rx_buf(card, skb);
2080 return;
2081 }
2082 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2083 } else if (--card->iovpool.count < card->iovnr.min) {
2084 struct sk_buff *new_iovb;
2085 if ((new_iovb =
2086 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2087 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2088 skb_queue_tail(&card->iovpool.queue, new_iovb);
2089 card->iovpool.count++;
2090 }
2091 }
2092 vc->rx_iov = iovb;
2093 NS_PRV_IOVCNT(iovb) = 0;
2094 iovb->len = 0;
2095 iovb->data = iovb->head;
2096 skb_reset_tail_pointer(iovb);
2097 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2098 buffer is stored as iovec base, NOT a pointer to the
2099 small or large buffer itself. */
2100 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2101 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2102 atomic_inc(&vcc->stats->rx_err);
2103 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2104 NS_MAX_IOVECS);
2105 NS_PRV_IOVCNT(iovb) = 0;
2106 iovb->len = 0;
2107 iovb->data = iovb->head;
2108 skb_reset_tail_pointer(iovb);
2109 }
2110 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2111 iov->iov_base = (void *)skb;
2112 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2113 iovb->len += iov->iov_len;
2114
2115#ifdef EXTRA_DEBUG
2116 if (NS_PRV_IOVCNT(iovb) == 1) {
2117 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2118 printk
2119 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2120 card->index);
2121 which_list(card, skb);
2122 atomic_inc(&vcc->stats->rx_err);
2123 recycle_rx_buf(card, skb);
2124 vc->rx_iov = NULL;
2125 recycle_iov_buf(card, iovb);
2126 return;
2127 }
2128 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2129
2130 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2131 printk
2132 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2133 card->index);
2134 which_list(card, skb);
2135 atomic_inc(&vcc->stats->rx_err);
2136 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2137 NS_PRV_IOVCNT(iovb));
2138 vc->rx_iov = NULL;
2139 recycle_iov_buf(card, iovb);
2140 return;
2141 }
2142 }
2143#endif /* EXTRA_DEBUG */
2144
2145 if (ns_rsqe_eopdu(rsqe)) {
2146 /* This works correctly regardless of the endianness of the host */
2147 unsigned char *L1L2 = (unsigned char *)
2148 (skb->data + iov->iov_len - 6);
2149 aal5_len = L1L2[0] << 8 | L1L2[1];
2150 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2151 if (ns_rsqe_crcerr(rsqe) ||
2152 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2153 printk("nicstar%d: AAL5 CRC error", card->index);
2154 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2155 printk(" - PDU size mismatch.\n");
2156 else
2157 printk(".\n");
2158 atomic_inc(&vcc->stats->rx_err);
2159 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2160 NS_PRV_IOVCNT(iovb));
2161 vc->rx_iov = NULL;
2162 recycle_iov_buf(card, iovb);
2163 return;
2164 }
2165
2166 /* By this point we (hopefully) have a complete SDU without errors. */
2167
2168 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2169 /* skb points to a small buffer */
2170 if (!atm_charge(vcc, skb->truesize)) {
2171 push_rxbufs(card, skb);
2172 atomic_inc(&vcc->stats->rx_drop);
2173 } else {
2174 skb_put(skb, len);
2175 dequeue_sm_buf(card, skb);
2176 ATM_SKB(skb)->vcc = vcc;
2177 __net_timestamp(skb);
2178 vcc->push(vcc, skb);
2179 atomic_inc(&vcc->stats->rx);
2180 }
2181 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2182 struct sk_buff *sb;
2183
2184 sb = (struct sk_buff *)(iov - 1)->iov_base;
2185 /* skb points to a large buffer */
2186
2187 if (len <= NS_SMBUFSIZE) {
2188 if (!atm_charge(vcc, sb->truesize)) {
2189 push_rxbufs(card, sb);
2190 atomic_inc(&vcc->stats->rx_drop);
2191 } else {
2192 skb_put(sb, len);
2193 dequeue_sm_buf(card, sb);
2194 ATM_SKB(sb)->vcc = vcc;
2195 __net_timestamp(sb);
2196 vcc->push(vcc, sb);
2197 atomic_inc(&vcc->stats->rx);
2198 }
2199
2200 push_rxbufs(card, skb);
2201
2202 } else { /* len > NS_SMBUFSIZE, the usual case */
2203
2204 if (!atm_charge(vcc, skb->truesize)) {
2205 push_rxbufs(card, skb);
2206 atomic_inc(&vcc->stats->rx_drop);
2207 } else {
2208 dequeue_lg_buf(card, skb);
2209 skb_push(skb, NS_SMBUFSIZE);
2210 skb_copy_from_linear_data(sb, skb->data,
2211 NS_SMBUFSIZE);
2212 skb_put(skb, len - NS_SMBUFSIZE);
2213 ATM_SKB(skb)->vcc = vcc;
2214 __net_timestamp(skb);
2215 vcc->push(vcc, skb);
2216 atomic_inc(&vcc->stats->rx);
2217 }
2218
2219 push_rxbufs(card, sb);
2220
2221 }
2222
2223 } else { /* Must push a huge buffer */
2224
2225 struct sk_buff *hb, *sb, *lb;
2226 int remaining, tocopy;
2227 int j;
2228
2229 hb = skb_dequeue(&(card->hbpool.queue));
2230 if (hb == NULL) { /* No buffers in the queue */
2231
2232 hb = dev_alloc_skb(NS_HBUFSIZE);
2233 if (hb == NULL) {
2234 printk
2235 ("nicstar%d: Out of huge buffers.\n",
2236 card->index);
2237 atomic_inc(&vcc->stats->rx_drop);
2238 recycle_iovec_rx_bufs(card,
2239 (struct iovec *)
2240 iovb->data,
2241 NS_PRV_IOVCNT(iovb));
2242 vc->rx_iov = NULL;
2243 recycle_iov_buf(card, iovb);
2244 return;
2245 } else if (card->hbpool.count < card->hbnr.min) {
2246 struct sk_buff *new_hb;
2247 if ((new_hb =
2248 dev_alloc_skb(NS_HBUFSIZE)) !=
2249 NULL) {
2250 skb_queue_tail(&card->hbpool.
2251 queue, new_hb);
2252 card->hbpool.count++;
2253 }
2254 }
2255 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2256 } else if (--card->hbpool.count < card->hbnr.min) {
2257 struct sk_buff *new_hb;
2258 if ((new_hb =
2259 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2260 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2261 skb_queue_tail(&card->hbpool.queue,
2262 new_hb);
2263 card->hbpool.count++;
2264 }
2265 if (card->hbpool.count < card->hbnr.min) {
2266 if ((new_hb =
2267 dev_alloc_skb(NS_HBUFSIZE)) !=
2268 NULL) {
2269 NS_PRV_BUFTYPE(new_hb) =
2270 BUF_NONE;
2271 skb_queue_tail(&card->hbpool.
2272 queue, new_hb);
2273 card->hbpool.count++;
2274 }
2275 }
2276 }
2277
2278 iov = (struct iovec *)iovb->data;
2279
2280 if (!atm_charge(vcc, hb->truesize)) {
2281 recycle_iovec_rx_bufs(card, iov,
2282 NS_PRV_IOVCNT(iovb));
2283 if (card->hbpool.count < card->hbnr.max) {
2284 skb_queue_tail(&card->hbpool.queue, hb);
2285 card->hbpool.count++;
2286 } else
2287 dev_kfree_skb_any(hb);
2288 atomic_inc(&vcc->stats->rx_drop);
2289 } else {
2290 /* Copy the small buffer to the huge buffer */
2291 sb = (struct sk_buff *)iov->iov_base;
2292 skb_copy_from_linear_data(sb, hb->data,
2293 iov->iov_len);
2294 skb_put(hb, iov->iov_len);
2295 remaining = len - iov->iov_len;
2296 iov++;
2297 /* Free the small buffer */
2298 push_rxbufs(card, sb);
2299
2300 /* Copy all large buffers to the huge buffer and free them */
2301 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2302 lb = (struct sk_buff *)iov->iov_base;
2303 tocopy =
2304 min_t(int, remaining, iov->iov_len);
2305 skb_copy_from_linear_data(lb,
2306 skb_tail_pointer
2307 (hb), tocopy);
2308 skb_put(hb, tocopy);
2309 iov++;
2310 remaining -= tocopy;
2311 push_rxbufs(card, lb);
2312 }
2313#ifdef EXTRA_DEBUG
2314 if (remaining != 0 || hb->len != len)
2315 printk
2316 ("nicstar%d: Huge buffer len mismatch.\n",
2317 card->index);
2318#endif /* EXTRA_DEBUG */
2319 ATM_SKB(hb)->vcc = vcc;
2320 __net_timestamp(hb);
2321 vcc->push(vcc, hb);
2322 atomic_inc(&vcc->stats->rx);
2323 }
2324 }
2325
2326 vc->rx_iov = NULL;
2327 recycle_iov_buf(card, iovb);
2328 }
2329
2330}
2331
2332static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2333{
2334 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2335 printk("nicstar%d: What kind of rx buffer is this?\n",
2336 card->index);
2337 dev_kfree_skb_any(skb);
2338 } else
2339 push_rxbufs(card, skb);
2340}
2341
2342static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2343{
2344 while (count-- > 0)
2345 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2346}
2347
2348static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2349{
2350 if (card->iovpool.count < card->iovnr.max) {
2351 skb_queue_tail(&card->iovpool.queue, iovb);
2352 card->iovpool.count++;
2353 } else
2354 dev_kfree_skb_any(iovb);
2355}
2356
2357static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2358{
2359 skb_unlink(sb, &card->sbpool.queue);
2360 if (card->sbfqc < card->sbnr.init) {
2361 struct sk_buff *new_sb;
2362 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2363 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2364 skb_queue_tail(&card->sbpool.queue, new_sb);
2365 skb_reserve(new_sb, NS_AAL0_HEADER);
2366 push_rxbufs(card, new_sb);
2367 }
2368 }
2369 if (card->sbfqc < card->sbnr.init)
2370 {
2371 struct sk_buff *new_sb;
2372 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2373 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2374 skb_queue_tail(&card->sbpool.queue, new_sb);
2375 skb_reserve(new_sb, NS_AAL0_HEADER);
2376 push_rxbufs(card, new_sb);
2377 }
2378 }
2379}
2380
2381static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2382{
2383 skb_unlink(lb, &card->lbpool.queue);
2384 if (card->lbfqc < card->lbnr.init) {
2385 struct sk_buff *new_lb;
2386 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2387 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2388 skb_queue_tail(&card->lbpool.queue, new_lb);
2389 skb_reserve(new_lb, NS_SMBUFSIZE);
2390 push_rxbufs(card, new_lb);
2391 }
2392 }
2393 if (card->lbfqc < card->lbnr.init)
2394 {
2395 struct sk_buff *new_lb;
2396 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2397 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2398 skb_queue_tail(&card->lbpool.queue, new_lb);
2399 skb_reserve(new_lb, NS_SMBUFSIZE);
2400 push_rxbufs(card, new_lb);
2401 }
2402 }
2403}
2404
2405static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2406{
2407 u32 stat;
2408 ns_dev *card;
2409 int left;
2410
2411 left = (int)*pos;
2412 card = (ns_dev *) dev->dev_data;
2413 stat = readl(card->membase + STAT);
2414 if (!left--)
2415 return sprintf(page, "Pool count min init max \n");
2416 if (!left--)
2417 return sprintf(page, "Small %5d %5d %5d %5d \n",
2418 ns_stat_sfbqc_get(stat), card->sbnr.min,
2419 card->sbnr.init, card->sbnr.max);
2420 if (!left--)
2421 return sprintf(page, "Large %5d %5d %5d %5d \n",
2422 ns_stat_lfbqc_get(stat), card->lbnr.min,
2423 card->lbnr.init, card->lbnr.max);
2424 if (!left--)
2425 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2426 card->hbpool.count, card->hbnr.min,
2427 card->hbnr.init, card->hbnr.max);
2428 if (!left--)
2429 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2430 card->iovpool.count, card->iovnr.min,
2431 card->iovnr.init, card->iovnr.max);
2432 if (!left--) {
2433 int retval;
2434 retval =
2435 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2436 card->intcnt = 0;
2437 return retval;
2438 }
2439#if 0
2440 /* Dump 25.6 Mbps PHY registers */
2441 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2442 here just in case it's needed for debugging. */
2443 if (card->max_pcr == ATM_25_PCR && !left--) {
2444 u32 phy_regs[4];
2445 u32 i;
2446
2447 for (i = 0; i < 4; i++) {
2448 while (CMD_BUSY(card)) ;
2449 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2450 card->membase + CMD);
2451 while (CMD_BUSY(card)) ;
2452 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2453 }
2454
2455 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2456 phy_regs[0], phy_regs[1], phy_regs[2],
2457 phy_regs[3]);
2458 }
2459#endif /* 0 - Dump 25.6 Mbps PHY registers */
2460#if 0
2461 /* Dump TST */
2462 if (left-- < NS_TST_NUM_ENTRIES) {
2463 if (card->tste2vc[left + 1] == NULL)
2464 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2465 else
2466 return sprintf(page, "%5d - %d %d \n", left + 1,
2467 card->tste2vc[left + 1]->tx_vcc->vpi,
2468 card->tste2vc[left + 1]->tx_vcc->vci);
2469 }
2470#endif /* 0 */
2471 return 0;
2472}
2473
2474static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2475{
2476 ns_dev *card;
2477 pool_levels pl;
2478 long btype;
2479 unsigned long flags;
2480
2481 card = dev->dev_data;
2482 switch (cmd) {
2483 case NS_GETPSTAT:
2484 if (get_user
2485 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2486 return -EFAULT;
2487 switch (pl.buftype) {
2488 case NS_BUFTYPE_SMALL:
2489 pl.count =
2490 ns_stat_sfbqc_get(readl(card->membase + STAT));
2491 pl.level.min = card->sbnr.min;
2492 pl.level.init = card->sbnr.init;
2493 pl.level.max = card->sbnr.max;
2494 break;
2495
2496 case NS_BUFTYPE_LARGE:
2497 pl.count =
2498 ns_stat_lfbqc_get(readl(card->membase + STAT));
2499 pl.level.min = card->lbnr.min;
2500 pl.level.init = card->lbnr.init;
2501 pl.level.max = card->lbnr.max;
2502 break;
2503
2504 case NS_BUFTYPE_HUGE:
2505 pl.count = card->hbpool.count;
2506 pl.level.min = card->hbnr.min;
2507 pl.level.init = card->hbnr.init;
2508 pl.level.max = card->hbnr.max;
2509 break;
2510
2511 case NS_BUFTYPE_IOVEC:
2512 pl.count = card->iovpool.count;
2513 pl.level.min = card->iovnr.min;
2514 pl.level.init = card->iovnr.init;
2515 pl.level.max = card->iovnr.max;
2516 break;
2517
2518 default:
2519 return -ENOIOCTLCMD;
2520
2521 }
2522 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2523 return (sizeof(pl));
2524 else
2525 return -EFAULT;
2526
2527 case NS_SETBUFLEV:
2528 if (!capable(CAP_NET_ADMIN))
2529 return -EPERM;
2530 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2531 return -EFAULT;
2532 if (pl.level.min >= pl.level.init
2533 || pl.level.init >= pl.level.max)
2534 return -EINVAL;
2535 if (pl.level.min == 0)
2536 return -EINVAL;
2537 switch (pl.buftype) {
2538 case NS_BUFTYPE_SMALL:
2539 if (pl.level.max > TOP_SB)
2540 return -EINVAL;
2541 card->sbnr.min = pl.level.min;
2542 card->sbnr.init = pl.level.init;
2543 card->sbnr.max = pl.level.max;
2544 break;
2545
2546 case NS_BUFTYPE_LARGE:
2547 if (pl.level.max > TOP_LB)
2548 return -EINVAL;
2549 card->lbnr.min = pl.level.min;
2550 card->lbnr.init = pl.level.init;
2551 card->lbnr.max = pl.level.max;
2552 break;
2553
2554 case NS_BUFTYPE_HUGE:
2555 if (pl.level.max > TOP_HB)
2556 return -EINVAL;
2557 card->hbnr.min = pl.level.min;
2558 card->hbnr.init = pl.level.init;
2559 card->hbnr.max = pl.level.max;
2560 break;
2561
2562 case NS_BUFTYPE_IOVEC:
2563 if (pl.level.max > TOP_IOVB)
2564 return -EINVAL;
2565 card->iovnr.min = pl.level.min;
2566 card->iovnr.init = pl.level.init;
2567 card->iovnr.max = pl.level.max;
2568 break;
2569
2570 default:
2571 return -EINVAL;
2572
2573 }
2574 return 0;
2575
2576 case NS_ADJBUFLEV:
2577 if (!capable(CAP_NET_ADMIN))
2578 return -EPERM;
2579 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2580 switch (btype) {
2581 case NS_BUFTYPE_SMALL:
2582 while (card->sbfqc < card->sbnr.init) {
2583 struct sk_buff *sb;
2584
2585 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2586 if (sb == NULL)
2587 return -ENOMEM;
2588 NS_PRV_BUFTYPE(sb) = BUF_SM;
2589 skb_queue_tail(&card->sbpool.queue, sb);
2590 skb_reserve(sb, NS_AAL0_HEADER);
2591 push_rxbufs(card, sb);
2592 }
2593 break;
2594
2595 case NS_BUFTYPE_LARGE:
2596 while (card->lbfqc < card->lbnr.init) {
2597 struct sk_buff *lb;
2598
2599 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2600 if (lb == NULL)
2601 return -ENOMEM;
2602 NS_PRV_BUFTYPE(lb) = BUF_LG;
2603 skb_queue_tail(&card->lbpool.queue, lb);
2604 skb_reserve(lb, NS_SMBUFSIZE);
2605 push_rxbufs(card, lb);
2606 }
2607 break;
2608
2609 case NS_BUFTYPE_HUGE:
2610 while (card->hbpool.count > card->hbnr.init) {
2611 struct sk_buff *hb;
2612
2613 spin_lock_irqsave(&card->int_lock, flags);
2614 hb = skb_dequeue(&card->hbpool.queue);
2615 card->hbpool.count--;
2616 spin_unlock_irqrestore(&card->int_lock, flags);
2617 if (hb == NULL)
2618 printk
2619 ("nicstar%d: huge buffer count inconsistent.\n",
2620 card->index);
2621 else
2622 dev_kfree_skb_any(hb);
2623
2624 }
2625 while (card->hbpool.count < card->hbnr.init) {
2626 struct sk_buff *hb;
2627
2628 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2629 if (hb == NULL)
2630 return -ENOMEM;
2631 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2632 spin_lock_irqsave(&card->int_lock, flags);
2633 skb_queue_tail(&card->hbpool.queue, hb);
2634 card->hbpool.count++;
2635 spin_unlock_irqrestore(&card->int_lock, flags);
2636 }
2637 break;
2638
2639 case NS_BUFTYPE_IOVEC:
2640 while (card->iovpool.count > card->iovnr.init) {
2641 struct sk_buff *iovb;
2642
2643 spin_lock_irqsave(&card->int_lock, flags);
2644 iovb = skb_dequeue(&card->iovpool.queue);
2645 card->iovpool.count--;
2646 spin_unlock_irqrestore(&card->int_lock, flags);
2647 if (iovb == NULL)
2648 printk
2649 ("nicstar%d: iovec buffer count inconsistent.\n",
2650 card->index);
2651 else
2652 dev_kfree_skb_any(iovb);
2653
2654 }
2655 while (card->iovpool.count < card->iovnr.init) {
2656 struct sk_buff *iovb;
2657
2658 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2659 if (iovb == NULL)
2660 return -ENOMEM;
2661 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2662 spin_lock_irqsave(&card->int_lock, flags);
2663 skb_queue_tail(&card->iovpool.queue, iovb);
2664 card->iovpool.count++;
2665 spin_unlock_irqrestore(&card->int_lock, flags);
2666 }
2667 break;
2668
2669 default:
2670 return -EINVAL;
2671
2672 }
2673 return 0;
2674
2675 default:
2676 if (dev->phy && dev->phy->ioctl) {
2677 return dev->phy->ioctl(dev, cmd, arg);
2678 } else {
2679 printk("nicstar%d: %s == NULL \n", card->index,
2680 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2681 return -ENOIOCTLCMD;
2682 }
2683 }
2684}
2685
2686#ifdef EXTRA_DEBUG
2687static void which_list(ns_dev * card, struct sk_buff *skb)
2688{
2689 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2690}
2691#endif /* EXTRA_DEBUG */
2692
2693static void ns_poll(struct timer_list *unused)
2694{
2695 int i;
2696 ns_dev *card;
2697 unsigned long flags;
2698 u32 stat_r, stat_w;
2699
2700 PRINTK("nicstar: Entering ns_poll().\n");
2701 for (i = 0; i < num_cards; i++) {
2702 card = cards[i];
2703 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2704 /* Probably it isn't worth spinning */
2705 continue;
2706 }
2707
2708 stat_w = 0;
2709 stat_r = readl(card->membase + STAT);
2710 if (stat_r & NS_STAT_TSIF)
2711 stat_w |= NS_STAT_TSIF;
2712 if (stat_r & NS_STAT_EOPDU)
2713 stat_w |= NS_STAT_EOPDU;
2714
2715 process_tsq(card);
2716 process_rsq(card);
2717
2718 writel(stat_w, card->membase + STAT);
2719 spin_unlock_irqrestore(&card->int_lock, flags);
2720 }
2721 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2722 PRINTK("nicstar: Leaving ns_poll().\n");
2723}
2724
2725static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2726 unsigned long addr)
2727{
2728 ns_dev *card;
2729 unsigned long flags;
2730
2731 card = dev->dev_data;
2732 spin_lock_irqsave(&card->res_lock, flags);
2733 while (CMD_BUSY(card)) ;
2734 writel((u32) value, card->membase + DR0);
2735 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2736 card->membase + CMD);
2737 spin_unlock_irqrestore(&card->res_lock, flags);
2738}
2739
2740static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2741{
2742 ns_dev *card;
2743 unsigned long flags;
2744 u32 data;
2745
2746 card = dev->dev_data;
2747 spin_lock_irqsave(&card->res_lock, flags);
2748 while (CMD_BUSY(card)) ;
2749 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2750 card->membase + CMD);
2751 while (CMD_BUSY(card)) ;
2752 data = readl(card->membase + DR0) & 0x000000FF;
2753 spin_unlock_irqrestore(&card->res_lock, flags);
2754 return (unsigned char)data;
2755}
2756
2757module_init(nicstar_init);
2758module_exit(nicstar_cleanup);
1/*
2 * nicstar.c
3 *
4 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards.
5 *
6 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME.
7 * It was taken from the frle-0.22 device driver.
8 * As the file doesn't have a copyright notice, in the file
9 * nicstarmac.copyright I put the copyright notice from the
10 * frle-0.22 device driver.
11 * Some code is based on the nicstar driver by M. Welsh.
12 *
13 * Author: Rui Prior (rprior@inescn.pt)
14 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999
15 *
16 *
17 * (C) INESC 1999
18 */
19
20/*
21 * IMPORTANT INFORMATION
22 *
23 * There are currently three types of spinlocks:
24 *
25 * 1 - Per card interrupt spinlock (to protect structures and such)
26 * 2 - Per SCQ scq spinlock
27 * 3 - Per card resource spinlock (to access registers, etc.)
28 *
29 * These must NEVER be grabbed in reverse order.
30 *
31 */
32
33/* Header files */
34
35#include <linux/module.h>
36#include <linux/kernel.h>
37#include <linux/skbuff.h>
38#include <linux/atmdev.h>
39#include <linux/atm.h>
40#include <linux/pci.h>
41#include <linux/dma-mapping.h>
42#include <linux/types.h>
43#include <linux/string.h>
44#include <linux/delay.h>
45#include <linux/init.h>
46#include <linux/sched.h>
47#include <linux/timer.h>
48#include <linux/interrupt.h>
49#include <linux/bitops.h>
50#include <linux/slab.h>
51#include <linux/idr.h>
52#include <asm/io.h>
53#include <asm/uaccess.h>
54#include <linux/atomic.h>
55#include <linux/etherdevice.h>
56#include "nicstar.h"
57#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
58#include "suni.h"
59#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
60#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
61#include "idt77105.h"
62#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
63
64/* Additional code */
65
66#include "nicstarmac.c"
67
68/* Configurable parameters */
69
70#undef PHY_LOOPBACK
71#undef TX_DEBUG
72#undef RX_DEBUG
73#undef GENERAL_DEBUG
74#undef EXTRA_DEBUG
75
76#undef NS_USE_DESTRUCTORS /* For now keep this undefined unless you know
77 you're going to use only raw ATM */
78
79/* Do not touch these */
80
81#ifdef TX_DEBUG
82#define TXPRINTK(args...) printk(args)
83#else
84#define TXPRINTK(args...)
85#endif /* TX_DEBUG */
86
87#ifdef RX_DEBUG
88#define RXPRINTK(args...) printk(args)
89#else
90#define RXPRINTK(args...)
91#endif /* RX_DEBUG */
92
93#ifdef GENERAL_DEBUG
94#define PRINTK(args...) printk(args)
95#else
96#define PRINTK(args...)
97#endif /* GENERAL_DEBUG */
98
99#ifdef EXTRA_DEBUG
100#define XPRINTK(args...) printk(args)
101#else
102#define XPRINTK(args...)
103#endif /* EXTRA_DEBUG */
104
105/* Macros */
106
107#define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
108
109#define NS_DELAY mdelay(1)
110
111#define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b)))
112
113#ifndef ATM_SKB
114#define ATM_SKB(s) (&(s)->atm)
115#endif
116
117#define scq_virt_to_bus(scq, p) \
118 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org))
119
120/* Function declarations */
121
122static u32 ns_read_sram(ns_dev * card, u32 sram_address);
123static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
124 int count);
125static int ns_init_card(int i, struct pci_dev *pcidev);
126static void ns_init_card_error(ns_dev * card, int error);
127static scq_info *get_scq(ns_dev *card, int size, u32 scd);
128static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
129static void push_rxbufs(ns_dev *, struct sk_buff *);
130static irqreturn_t ns_irq_handler(int irq, void *dev_id);
131static int ns_open(struct atm_vcc *vcc);
132static void ns_close(struct atm_vcc *vcc);
133static void fill_tst(ns_dev * card, int n, vc_map * vc);
134static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb);
135static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
136 struct sk_buff *skb);
137static void process_tsq(ns_dev * card);
138static void drain_scq(ns_dev * card, scq_info * scq, int pos);
139static void process_rsq(ns_dev * card);
140static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
141#ifdef NS_USE_DESTRUCTORS
142static void ns_sb_destructor(struct sk_buff *sb);
143static void ns_lb_destructor(struct sk_buff *lb);
144static void ns_hb_destructor(struct sk_buff *hb);
145#endif /* NS_USE_DESTRUCTORS */
146static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
147static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
148static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
149static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
150static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
151static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page);
152static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg);
153#ifdef EXTRA_DEBUG
154static void which_list(ns_dev * card, struct sk_buff *skb);
155#endif
156static void ns_poll(unsigned long arg);
157static void ns_phy_put(struct atm_dev *dev, unsigned char value,
158 unsigned long addr);
159static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr);
160
161/* Global variables */
162
163static struct ns_dev *cards[NS_MAX_CARDS];
164static unsigned num_cards;
165static struct atmdev_ops atm_ops = {
166 .open = ns_open,
167 .close = ns_close,
168 .ioctl = ns_ioctl,
169 .send = ns_send,
170 .phy_put = ns_phy_put,
171 .phy_get = ns_phy_get,
172 .proc_read = ns_proc_read,
173 .owner = THIS_MODULE,
174};
175
176static struct timer_list ns_timer;
177static char *mac[NS_MAX_CARDS];
178module_param_array(mac, charp, NULL, 0);
179MODULE_LICENSE("GPL");
180
181/* Functions */
182
183static int nicstar_init_one(struct pci_dev *pcidev,
184 const struct pci_device_id *ent)
185{
186 static int index = -1;
187 unsigned int error;
188
189 index++;
190 cards[index] = NULL;
191
192 error = ns_init_card(index, pcidev);
193 if (error) {
194 cards[index--] = NULL; /* don't increment index */
195 goto err_out;
196 }
197
198 return 0;
199err_out:
200 return -ENODEV;
201}
202
203static void nicstar_remove_one(struct pci_dev *pcidev)
204{
205 int i, j;
206 ns_dev *card = pci_get_drvdata(pcidev);
207 struct sk_buff *hb;
208 struct sk_buff *iovb;
209 struct sk_buff *lb;
210 struct sk_buff *sb;
211
212 i = card->index;
213
214 if (cards[i] == NULL)
215 return;
216
217 if (card->atmdev->phy && card->atmdev->phy->stop)
218 card->atmdev->phy->stop(card->atmdev);
219
220 /* Stop everything */
221 writel(0x00000000, card->membase + CFG);
222
223 /* De-register device */
224 atm_dev_deregister(card->atmdev);
225
226 /* Disable PCI device */
227 pci_disable_device(pcidev);
228
229 /* Free up resources */
230 j = 0;
231 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
232 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
233 dev_kfree_skb_any(hb);
234 j++;
235 }
236 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j);
237 j = 0;
238 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i,
239 card->iovpool.count);
240 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
241 dev_kfree_skb_any(iovb);
242 j++;
243 }
244 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j);
245 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
246 dev_kfree_skb_any(lb);
247 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
248 dev_kfree_skb_any(sb);
249 free_scq(card, card->scq0, NULL);
250 for (j = 0; j < NS_FRSCD_NUM; j++) {
251 if (card->scd2vc[j] != NULL)
252 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
253 }
254 idr_destroy(&card->idr);
255 pci_free_consistent(card->pcidev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
256 card->rsq.org, card->rsq.dma);
257 pci_free_consistent(card->pcidev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
258 card->tsq.org, card->tsq.dma);
259 free_irq(card->pcidev->irq, card);
260 iounmap(card->membase);
261 kfree(card);
262}
263
264static struct pci_device_id nicstar_pci_tbl[] = {
265 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 },
266 {0,} /* terminate list */
267};
268
269MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl);
270
271static struct pci_driver nicstar_driver = {
272 .name = "nicstar",
273 .id_table = nicstar_pci_tbl,
274 .probe = nicstar_init_one,
275 .remove = nicstar_remove_one,
276};
277
278static int __init nicstar_init(void)
279{
280 unsigned error = 0; /* Initialized to remove compile warning */
281
282 XPRINTK("nicstar: nicstar_init() called.\n");
283
284 error = pci_register_driver(&nicstar_driver);
285
286 TXPRINTK("nicstar: TX debug enabled.\n");
287 RXPRINTK("nicstar: RX debug enabled.\n");
288 PRINTK("nicstar: General debug enabled.\n");
289#ifdef PHY_LOOPBACK
290 printk("nicstar: using PHY loopback.\n");
291#endif /* PHY_LOOPBACK */
292 XPRINTK("nicstar: nicstar_init() returned.\n");
293
294 if (!error) {
295 init_timer(&ns_timer);
296 ns_timer.expires = jiffies + NS_POLL_PERIOD;
297 ns_timer.data = 0UL;
298 ns_timer.function = ns_poll;
299 add_timer(&ns_timer);
300 }
301
302 return error;
303}
304
305static void __exit nicstar_cleanup(void)
306{
307 XPRINTK("nicstar: nicstar_cleanup() called.\n");
308
309 del_timer(&ns_timer);
310
311 pci_unregister_driver(&nicstar_driver);
312
313 XPRINTK("nicstar: nicstar_cleanup() returned.\n");
314}
315
316static u32 ns_read_sram(ns_dev * card, u32 sram_address)
317{
318 unsigned long flags;
319 u32 data;
320 sram_address <<= 2;
321 sram_address &= 0x0007FFFC; /* address must be dword aligned */
322 sram_address |= 0x50000000; /* SRAM read command */
323 spin_lock_irqsave(&card->res_lock, flags);
324 while (CMD_BUSY(card)) ;
325 writel(sram_address, card->membase + CMD);
326 while (CMD_BUSY(card)) ;
327 data = readl(card->membase + DR0);
328 spin_unlock_irqrestore(&card->res_lock, flags);
329 return data;
330}
331
332static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
333 int count)
334{
335 unsigned long flags;
336 int i, c;
337 count--; /* count range now is 0..3 instead of 1..4 */
338 c = count;
339 c <<= 2; /* to use increments of 4 */
340 spin_lock_irqsave(&card->res_lock, flags);
341 while (CMD_BUSY(card)) ;
342 for (i = 0; i <= c; i += 4)
343 writel(*(value++), card->membase + i);
344 /* Note: DR# registers are the first 4 dwords in nicstar's memspace,
345 so card->membase + DR0 == card->membase */
346 sram_address <<= 2;
347 sram_address &= 0x0007FFFC;
348 sram_address |= (0x40000000 | count);
349 writel(sram_address, card->membase + CMD);
350 spin_unlock_irqrestore(&card->res_lock, flags);
351}
352
353static int ns_init_card(int i, struct pci_dev *pcidev)
354{
355 int j;
356 struct ns_dev *card = NULL;
357 unsigned char pci_latency;
358 unsigned error;
359 u32 data;
360 u32 u32d[4];
361 u32 ns_cfg_rctsize;
362 int bcount;
363 unsigned long membase;
364
365 error = 0;
366
367 if (pci_enable_device(pcidev)) {
368 printk("nicstar%d: can't enable PCI device\n", i);
369 error = 2;
370 ns_init_card_error(card, error);
371 return error;
372 }
373 if ((pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)) != 0) ||
374 (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32)) != 0)) {
375 printk(KERN_WARNING
376 "nicstar%d: No suitable DMA available.\n", i);
377 error = 2;
378 ns_init_card_error(card, error);
379 return error;
380 }
381
382 if ((card = kmalloc(sizeof(ns_dev), GFP_KERNEL)) == NULL) {
383 printk
384 ("nicstar%d: can't allocate memory for device structure.\n",
385 i);
386 error = 2;
387 ns_init_card_error(card, error);
388 return error;
389 }
390 cards[i] = card;
391 spin_lock_init(&card->int_lock);
392 spin_lock_init(&card->res_lock);
393
394 pci_set_drvdata(pcidev, card);
395
396 card->index = i;
397 card->atmdev = NULL;
398 card->pcidev = pcidev;
399 membase = pci_resource_start(pcidev, 1);
400 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
401 if (!card->membase) {
402 printk("nicstar%d: can't ioremap() membase.\n", i);
403 error = 3;
404 ns_init_card_error(card, error);
405 return error;
406 }
407 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
408
409 pci_set_master(pcidev);
410
411 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) {
412 printk("nicstar%d: can't read PCI latency timer.\n", i);
413 error = 6;
414 ns_init_card_error(card, error);
415 return error;
416 }
417#ifdef NS_PCI_LATENCY
418 if (pci_latency < NS_PCI_LATENCY) {
419 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i,
420 NS_PCI_LATENCY);
421 for (j = 1; j < 4; j++) {
422 if (pci_write_config_byte
423 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0)
424 break;
425 }
426 if (j == 4) {
427 printk
428 ("nicstar%d: can't set PCI latency timer to %d.\n",
429 i, NS_PCI_LATENCY);
430 error = 7;
431 ns_init_card_error(card, error);
432 return error;
433 }
434 }
435#endif /* NS_PCI_LATENCY */
436
437 /* Clear timer overflow */
438 data = readl(card->membase + STAT);
439 if (data & NS_STAT_TMROF)
440 writel(NS_STAT_TMROF, card->membase + STAT);
441
442 /* Software reset */
443 writel(NS_CFG_SWRST, card->membase + CFG);
444 NS_DELAY;
445 writel(0x00000000, card->membase + CFG);
446
447 /* PHY reset */
448 writel(0x00000008, card->membase + GP);
449 NS_DELAY;
450 writel(0x00000001, card->membase + GP);
451 NS_DELAY;
452 while (CMD_BUSY(card)) ;
453 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
454 NS_DELAY;
455
456 /* Detect PHY type */
457 while (CMD_BUSY(card)) ;
458 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
459 while (CMD_BUSY(card)) ;
460 data = readl(card->membase + DR0);
461 switch (data) {
462 case 0x00000009:
463 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i);
464 card->max_pcr = ATM_25_PCR;
465 while (CMD_BUSY(card)) ;
466 writel(0x00000008, card->membase + DR0);
467 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
468 /* Clear an eventual pending interrupt */
469 writel(NS_STAT_SFBQF, card->membase + STAT);
470#ifdef PHY_LOOPBACK
471 while (CMD_BUSY(card)) ;
472 writel(0x00000022, card->membase + DR0);
473 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
474#endif /* PHY_LOOPBACK */
475 break;
476 case 0x00000030:
477 case 0x00000031:
478 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i);
479 card->max_pcr = ATM_OC3_PCR;
480#ifdef PHY_LOOPBACK
481 while (CMD_BUSY(card)) ;
482 writel(0x00000002, card->membase + DR0);
483 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
484#endif /* PHY_LOOPBACK */
485 break;
486 default:
487 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data);
488 error = 8;
489 ns_init_card_error(card, error);
490 return error;
491 }
492 writel(0x00000000, card->membase + GP);
493
494 /* Determine SRAM size */
495 data = 0x76543210;
496 ns_write_sram(card, 0x1C003, &data, 1);
497 data = 0x89ABCDEF;
498 ns_write_sram(card, 0x14003, &data, 1);
499 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
500 ns_read_sram(card, 0x1C003) == 0x76543210)
501 card->sram_size = 128;
502 else
503 card->sram_size = 32;
504 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
505
506 card->rct_size = NS_MAX_RCTSIZE;
507
508#if (NS_MAX_RCTSIZE == 4096)
509 if (card->sram_size == 128)
510 printk
511 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n",
512 i);
513#elif (NS_MAX_RCTSIZE == 16384)
514 if (card->sram_size == 32) {
515 printk
516 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n",
517 i);
518 card->rct_size = 4096;
519 }
520#else
521#error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c
522#endif
523
524 card->vpibits = NS_VPIBITS;
525 if (card->rct_size == 4096)
526 card->vcibits = 12 - NS_VPIBITS;
527 else /* card->rct_size == 16384 */
528 card->vcibits = 14 - NS_VPIBITS;
529
530 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */
531 if (mac[i] == NULL)
532 nicstar_init_eprom(card->membase);
533
534 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */
535 writel(0x00000000, card->membase + VPM);
536
537 /* Initialize TSQ */
538 card->tsq.org = pci_alloc_consistent(card->pcidev,
539 NS_TSQSIZE + NS_TSQ_ALIGNMENT,
540 &card->tsq.dma);
541 if (card->tsq.org == NULL) {
542 printk("nicstar%d: can't allocate TSQ.\n", i);
543 error = 10;
544 ns_init_card_error(card, error);
545 return error;
546 }
547 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
548 card->tsq.next = card->tsq.base;
549 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
550 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++)
551 ns_tsi_init(card->tsq.base + j);
552 writel(0x00000000, card->membase + TSQH);
553 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
554 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
555
556 /* Initialize RSQ */
557 card->rsq.org = pci_alloc_consistent(card->pcidev,
558 NS_RSQSIZE + NS_RSQ_ALIGNMENT,
559 &card->rsq.dma);
560 if (card->rsq.org == NULL) {
561 printk("nicstar%d: can't allocate RSQ.\n", i);
562 error = 11;
563 ns_init_card_error(card, error);
564 return error;
565 }
566 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
567 card->rsq.next = card->rsq.base;
568 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
569 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++)
570 ns_rsqe_init(card->rsq.base + j);
571 writel(0x00000000, card->membase + RSQH);
572 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
573 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
574
575 /* Initialize SCQ0, the only VBR SCQ used */
576 card->scq1 = NULL;
577 card->scq2 = NULL;
578 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
579 if (card->scq0 == NULL) {
580 printk("nicstar%d: can't get SCQ0.\n", i);
581 error = 12;
582 ns_init_card_error(card, error);
583 return error;
584 }
585 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
586 u32d[1] = (u32) 0x00000000;
587 u32d[2] = (u32) 0xffffffff;
588 u32d[3] = (u32) 0x00000000;
589 ns_write_sram(card, NS_VRSCD0, u32d, 4);
590 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
591 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
592 card->scq0->scd = NS_VRSCD0;
593 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
594
595 /* Initialize TSTs */
596 card->tst_addr = NS_TST0;
597 card->tst_free_entries = NS_TST_NUM_ENTRIES;
598 data = NS_TST_OPCODE_VARIABLE;
599 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
600 ns_write_sram(card, NS_TST0 + j, &data, 1);
601 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0);
602 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
603 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
604 ns_write_sram(card, NS_TST1 + j, &data, 1);
605 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1);
606 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
607 for (j = 0; j < NS_TST_NUM_ENTRIES; j++)
608 card->tste2vc[j] = NULL;
609 writel(NS_TST0 << 2, card->membase + TSTB);
610
611 /* Initialize RCT. AAL type is set on opening the VC. */
612#ifdef RCQ_SUPPORT
613 u32d[0] = NS_RCTE_RAWCELLINTEN;
614#else
615 u32d[0] = 0x00000000;
616#endif /* RCQ_SUPPORT */
617 u32d[1] = 0x00000000;
618 u32d[2] = 0x00000000;
619 u32d[3] = 0xFFFFFFFF;
620 for (j = 0; j < card->rct_size; j++)
621 ns_write_sram(card, j * 4, u32d, 4);
622
623 memset(card->vcmap, 0, NS_MAX_RCTSIZE * sizeof(vc_map));
624
625 for (j = 0; j < NS_FRSCD_NUM; j++)
626 card->scd2vc[j] = NULL;
627
628 /* Initialize buffer levels */
629 card->sbnr.min = MIN_SB;
630 card->sbnr.init = NUM_SB;
631 card->sbnr.max = MAX_SB;
632 card->lbnr.min = MIN_LB;
633 card->lbnr.init = NUM_LB;
634 card->lbnr.max = MAX_LB;
635 card->iovnr.min = MIN_IOVB;
636 card->iovnr.init = NUM_IOVB;
637 card->iovnr.max = MAX_IOVB;
638 card->hbnr.min = MIN_HB;
639 card->hbnr.init = NUM_HB;
640 card->hbnr.max = MAX_HB;
641
642 card->sm_handle = NULL;
643 card->sm_addr = 0x00000000;
644 card->lg_handle = NULL;
645 card->lg_addr = 0x00000000;
646
647 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
648
649 idr_init(&card->idr);
650
651 /* Pre-allocate some huge buffers */
652 skb_queue_head_init(&card->hbpool.queue);
653 card->hbpool.count = 0;
654 for (j = 0; j < NUM_HB; j++) {
655 struct sk_buff *hb;
656 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
657 if (hb == NULL) {
658 printk
659 ("nicstar%d: can't allocate %dth of %d huge buffers.\n",
660 i, j, NUM_HB);
661 error = 13;
662 ns_init_card_error(card, error);
663 return error;
664 }
665 NS_PRV_BUFTYPE(hb) = BUF_NONE;
666 skb_queue_tail(&card->hbpool.queue, hb);
667 card->hbpool.count++;
668 }
669
670 /* Allocate large buffers */
671 skb_queue_head_init(&card->lbpool.queue);
672 card->lbpool.count = 0; /* Not used */
673 for (j = 0; j < NUM_LB; j++) {
674 struct sk_buff *lb;
675 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
676 if (lb == NULL) {
677 printk
678 ("nicstar%d: can't allocate %dth of %d large buffers.\n",
679 i, j, NUM_LB);
680 error = 14;
681 ns_init_card_error(card, error);
682 return error;
683 }
684 NS_PRV_BUFTYPE(lb) = BUF_LG;
685 skb_queue_tail(&card->lbpool.queue, lb);
686 skb_reserve(lb, NS_SMBUFSIZE);
687 push_rxbufs(card, lb);
688 /* Due to the implementation of push_rxbufs() this is 1, not 0 */
689 if (j == 1) {
690 card->rcbuf = lb;
691 card->rawcell = (struct ns_rcqe *) lb->data;
692 card->rawch = NS_PRV_DMA(lb);
693 }
694 }
695 /* Test for strange behaviour which leads to crashes */
696 if ((bcount =
697 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
698 printk
699 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n",
700 i, j, bcount);
701 error = 14;
702 ns_init_card_error(card, error);
703 return error;
704 }
705
706 /* Allocate small buffers */
707 skb_queue_head_init(&card->sbpool.queue);
708 card->sbpool.count = 0; /* Not used */
709 for (j = 0; j < NUM_SB; j++) {
710 struct sk_buff *sb;
711 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
712 if (sb == NULL) {
713 printk
714 ("nicstar%d: can't allocate %dth of %d small buffers.\n",
715 i, j, NUM_SB);
716 error = 15;
717 ns_init_card_error(card, error);
718 return error;
719 }
720 NS_PRV_BUFTYPE(sb) = BUF_SM;
721 skb_queue_tail(&card->sbpool.queue, sb);
722 skb_reserve(sb, NS_AAL0_HEADER);
723 push_rxbufs(card, sb);
724 }
725 /* Test for strange behaviour which leads to crashes */
726 if ((bcount =
727 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
728 printk
729 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n",
730 i, j, bcount);
731 error = 15;
732 ns_init_card_error(card, error);
733 return error;
734 }
735
736 /* Allocate iovec buffers */
737 skb_queue_head_init(&card->iovpool.queue);
738 card->iovpool.count = 0;
739 for (j = 0; j < NUM_IOVB; j++) {
740 struct sk_buff *iovb;
741 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
742 if (iovb == NULL) {
743 printk
744 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n",
745 i, j, NUM_IOVB);
746 error = 16;
747 ns_init_card_error(card, error);
748 return error;
749 }
750 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
751 skb_queue_tail(&card->iovpool.queue, iovb);
752 card->iovpool.count++;
753 }
754
755 /* Configure NICStAR */
756 if (card->rct_size == 4096)
757 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES;
758 else /* (card->rct_size == 16384) */
759 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES;
760
761 card->efbie = 1;
762
763 card->intcnt = 0;
764 if (request_irq
765 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
766 printk("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq);
767 error = 9;
768 ns_init_card_error(card, error);
769 return error;
770 }
771
772 /* Register device */
773 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
774 -1, NULL);
775 if (card->atmdev == NULL) {
776 printk("nicstar%d: can't register device.\n", i);
777 error = 17;
778 ns_init_card_error(card, error);
779 return error;
780 }
781
782 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
783 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
784 card->atmdev->esi, 6);
785 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
786 nicstar_read_eprom(card->membase,
787 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT,
788 card->atmdev->esi, 6);
789 }
790 }
791
792 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
793
794 card->atmdev->dev_data = card;
795 card->atmdev->ci_range.vpi_bits = card->vpibits;
796 card->atmdev->ci_range.vci_bits = card->vcibits;
797 card->atmdev->link_rate = card->max_pcr;
798 card->atmdev->phy = NULL;
799
800#ifdef CONFIG_ATM_NICSTAR_USE_SUNI
801 if (card->max_pcr == ATM_OC3_PCR)
802 suni_init(card->atmdev);
803#endif /* CONFIG_ATM_NICSTAR_USE_SUNI */
804
805#ifdef CONFIG_ATM_NICSTAR_USE_IDT77105
806 if (card->max_pcr == ATM_25_PCR)
807 idt77105_init(card->atmdev);
808#endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */
809
810 if (card->atmdev->phy && card->atmdev->phy->start)
811 card->atmdev->phy->start(card->atmdev);
812
813 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */
814 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */
815 NS_CFG_PHYIE, card->membase + CFG);
816
817 num_cards++;
818
819 return error;
820}
821
822static void ns_init_card_error(ns_dev *card, int error)
823{
824 if (error >= 17) {
825 writel(0x00000000, card->membase + CFG);
826 }
827 if (error >= 16) {
828 struct sk_buff *iovb;
829 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
830 dev_kfree_skb_any(iovb);
831 }
832 if (error >= 15) {
833 struct sk_buff *sb;
834 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
835 dev_kfree_skb_any(sb);
836 free_scq(card, card->scq0, NULL);
837 }
838 if (error >= 14) {
839 struct sk_buff *lb;
840 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
841 dev_kfree_skb_any(lb);
842 }
843 if (error >= 13) {
844 struct sk_buff *hb;
845 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
846 dev_kfree_skb_any(hb);
847 }
848 if (error >= 12) {
849 kfree(card->rsq.org);
850 }
851 if (error >= 11) {
852 kfree(card->tsq.org);
853 }
854 if (error >= 10) {
855 free_irq(card->pcidev->irq, card);
856 }
857 if (error >= 4) {
858 iounmap(card->membase);
859 }
860 if (error >= 3) {
861 pci_disable_device(card->pcidev);
862 kfree(card);
863 }
864}
865
866static scq_info *get_scq(ns_dev *card, int size, u32 scd)
867{
868 scq_info *scq;
869 int i;
870
871 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE)
872 return NULL;
873
874 scq = kmalloc(sizeof(scq_info), GFP_KERNEL);
875 if (!scq)
876 return NULL;
877 scq->org = pci_alloc_consistent(card->pcidev, 2 * size, &scq->dma);
878 if (!scq->org) {
879 kfree(scq);
880 return NULL;
881 }
882 scq->skb = kmalloc(sizeof(struct sk_buff *) *
883 (size / NS_SCQE_SIZE), GFP_KERNEL);
884 if (!scq->skb) {
885 kfree(scq->org);
886 kfree(scq);
887 return NULL;
888 }
889 scq->num_entries = size / NS_SCQE_SIZE;
890 scq->base = PTR_ALIGN(scq->org, size);
891 scq->next = scq->base;
892 scq->last = scq->base + (scq->num_entries - 1);
893 scq->tail = scq->last;
894 scq->scd = scd;
895 scq->num_entries = size / NS_SCQE_SIZE;
896 scq->tbd_count = 0;
897 init_waitqueue_head(&scq->scqfull_waitq);
898 scq->full = 0;
899 spin_lock_init(&scq->lock);
900
901 for (i = 0; i < scq->num_entries; i++)
902 scq->skb[i] = NULL;
903
904 return scq;
905}
906
907/* For variable rate SCQ vcc must be NULL */
908static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
909{
910 int i;
911
912 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES)
913 for (i = 0; i < scq->num_entries; i++) {
914 if (scq->skb[i] != NULL) {
915 vcc = ATM_SKB(scq->skb[i])->vcc;
916 if (vcc->pop != NULL)
917 vcc->pop(vcc, scq->skb[i]);
918 else
919 dev_kfree_skb_any(scq->skb[i]);
920 }
921 } else { /* vcc must be != NULL */
922
923 if (vcc == NULL) {
924 printk
925 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq.");
926 for (i = 0; i < scq->num_entries; i++)
927 dev_kfree_skb_any(scq->skb[i]);
928 } else
929 for (i = 0; i < scq->num_entries; i++) {
930 if (scq->skb[i] != NULL) {
931 if (vcc->pop != NULL)
932 vcc->pop(vcc, scq->skb[i]);
933 else
934 dev_kfree_skb_any(scq->skb[i]);
935 }
936 }
937 }
938 kfree(scq->skb);
939 pci_free_consistent(card->pcidev,
940 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ?
941 VBR_SCQSIZE : CBR_SCQSIZE),
942 scq->org, scq->dma);
943 kfree(scq);
944}
945
946/* The handles passed must be pointers to the sk_buff containing the small
947 or large buffer(s) cast to u32. */
948static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
949{
950 struct sk_buff *handle1, *handle2;
951 int id1, id2;
952 u32 addr1, addr2;
953 u32 stat;
954 unsigned long flags;
955
956 /* *BARF* */
957 handle2 = NULL;
958 addr2 = 0;
959 handle1 = skb;
960 addr1 = pci_map_single(card->pcidev,
961 skb->data,
962 (NS_PRV_BUFTYPE(skb) == BUF_SM
963 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
964 PCI_DMA_TODEVICE);
965 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */
966
967#ifdef GENERAL_DEBUG
968 if (!addr1)
969 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n",
970 card->index);
971#endif /* GENERAL_DEBUG */
972
973 stat = readl(card->membase + STAT);
974 card->sbfqc = ns_stat_sfbqc_get(stat);
975 card->lbfqc = ns_stat_lfbqc_get(stat);
976 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
977 if (!addr2) {
978 if (card->sm_addr) {
979 addr2 = card->sm_addr;
980 handle2 = card->sm_handle;
981 card->sm_addr = 0x00000000;
982 card->sm_handle = NULL;
983 } else { /* (!sm_addr) */
984
985 card->sm_addr = addr1;
986 card->sm_handle = handle1;
987 }
988 }
989 } else { /* buf_type == BUF_LG */
990
991 if (!addr2) {
992 if (card->lg_addr) {
993 addr2 = card->lg_addr;
994 handle2 = card->lg_handle;
995 card->lg_addr = 0x00000000;
996 card->lg_handle = NULL;
997 } else { /* (!lg_addr) */
998
999 card->lg_addr = addr1;
1000 card->lg_handle = handle1;
1001 }
1002 }
1003 }
1004
1005 if (addr2) {
1006 if (NS_PRV_BUFTYPE(skb) == BUF_SM) {
1007 if (card->sbfqc >= card->sbnr.max) {
1008 skb_unlink(handle1, &card->sbpool.queue);
1009 dev_kfree_skb_any(handle1);
1010 skb_unlink(handle2, &card->sbpool.queue);
1011 dev_kfree_skb_any(handle2);
1012 return;
1013 } else
1014 card->sbfqc += 2;
1015 } else { /* (buf_type == BUF_LG) */
1016
1017 if (card->lbfqc >= card->lbnr.max) {
1018 skb_unlink(handle1, &card->lbpool.queue);
1019 dev_kfree_skb_any(handle1);
1020 skb_unlink(handle2, &card->lbpool.queue);
1021 dev_kfree_skb_any(handle2);
1022 return;
1023 } else
1024 card->lbfqc += 2;
1025 }
1026
1027 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1028 if (id1 < 0)
1029 goto out;
1030
1031 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1032 if (id2 < 0)
1033 goto out;
1034
1035 spin_lock_irqsave(&card->res_lock, flags);
1036 while (CMD_BUSY(card)) ;
1037 writel(addr2, card->membase + DR3);
1038 writel(id2, card->membase + DR2);
1039 writel(addr1, card->membase + DR1);
1040 writel(id1, card->membase + DR0);
1041 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb),
1042 card->membase + CMD);
1043 spin_unlock_irqrestore(&card->res_lock, flags);
1044
1045 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n",
1046 card->index,
1047 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"),
1048 addr1, addr2);
1049 }
1050
1051 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1052 card->lbfqc >= card->lbnr.min) {
1053 card->efbie = 1;
1054 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1055 card->membase + CFG);
1056 }
1057
1058out:
1059 return;
1060}
1061
1062static irqreturn_t ns_irq_handler(int irq, void *dev_id)
1063{
1064 u32 stat_r;
1065 ns_dev *card;
1066 struct atm_dev *dev;
1067 unsigned long flags;
1068
1069 card = (ns_dev *) dev_id;
1070 dev = card->atmdev;
1071 card->intcnt++;
1072
1073 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1074
1075 spin_lock_irqsave(&card->int_lock, flags);
1076
1077 stat_r = readl(card->membase + STAT);
1078
1079 /* Transmit Status Indicator has been written to T. S. Queue */
1080 if (stat_r & NS_STAT_TSIF) {
1081 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1082 process_tsq(card);
1083 writel(NS_STAT_TSIF, card->membase + STAT);
1084 }
1085
1086 /* Incomplete CS-PDU has been transmitted */
1087 if (stat_r & NS_STAT_TXICP) {
1088 writel(NS_STAT_TXICP, card->membase + STAT);
1089 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n",
1090 card->index);
1091 }
1092
1093 /* Transmit Status Queue 7/8 full */
1094 if (stat_r & NS_STAT_TSQF) {
1095 writel(NS_STAT_TSQF, card->membase + STAT);
1096 PRINTK("nicstar%d: TSQ full.\n", card->index);
1097 process_tsq(card);
1098 }
1099
1100 /* Timer overflow */
1101 if (stat_r & NS_STAT_TMROF) {
1102 writel(NS_STAT_TMROF, card->membase + STAT);
1103 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1104 }
1105
1106 /* PHY device interrupt signal active */
1107 if (stat_r & NS_STAT_PHYI) {
1108 writel(NS_STAT_PHYI, card->membase + STAT);
1109 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1110 if (dev->phy && dev->phy->interrupt) {
1111 dev->phy->interrupt(dev);
1112 }
1113 }
1114
1115 /* Small Buffer Queue is full */
1116 if (stat_r & NS_STAT_SFBQF) {
1117 writel(NS_STAT_SFBQF, card->membase + STAT);
1118 printk("nicstar%d: Small free buffer queue is full.\n",
1119 card->index);
1120 }
1121
1122 /* Large Buffer Queue is full */
1123 if (stat_r & NS_STAT_LFBQF) {
1124 writel(NS_STAT_LFBQF, card->membase + STAT);
1125 printk("nicstar%d: Large free buffer queue is full.\n",
1126 card->index);
1127 }
1128
1129 /* Receive Status Queue is full */
1130 if (stat_r & NS_STAT_RSQF) {
1131 writel(NS_STAT_RSQF, card->membase + STAT);
1132 printk("nicstar%d: RSQ full.\n", card->index);
1133 process_rsq(card);
1134 }
1135
1136 /* Complete CS-PDU received */
1137 if (stat_r & NS_STAT_EOPDU) {
1138 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1139 process_rsq(card);
1140 writel(NS_STAT_EOPDU, card->membase + STAT);
1141 }
1142
1143 /* Raw cell received */
1144 if (stat_r & NS_STAT_RAWCF) {
1145 writel(NS_STAT_RAWCF, card->membase + STAT);
1146#ifndef RCQ_SUPPORT
1147 printk("nicstar%d: Raw cell received and no support yet...\n",
1148 card->index);
1149#endif /* RCQ_SUPPORT */
1150 /* NOTE: the following procedure may keep a raw cell pending until the
1151 next interrupt. As this preliminary support is only meant to
1152 avoid buffer leakage, this is not an issue. */
1153 while (readl(card->membase + RAWCT) != card->rawch) {
1154
1155 if (ns_rcqe_islast(card->rawcell)) {
1156 struct sk_buff *oldbuf;
1157
1158 oldbuf = card->rcbuf;
1159 card->rcbuf = idr_find(&card->idr,
1160 ns_rcqe_nextbufhandle(card->rawcell));
1161 card->rawch = NS_PRV_DMA(card->rcbuf);
1162 card->rawcell = (struct ns_rcqe *)
1163 card->rcbuf->data;
1164 recycle_rx_buf(card, oldbuf);
1165 } else {
1166 card->rawch += NS_RCQE_SIZE;
1167 card->rawcell++;
1168 }
1169 }
1170 }
1171
1172 /* Small buffer queue is empty */
1173 if (stat_r & NS_STAT_SFBQE) {
1174 int i;
1175 struct sk_buff *sb;
1176
1177 writel(NS_STAT_SFBQE, card->membase + STAT);
1178 printk("nicstar%d: Small free buffer queue empty.\n",
1179 card->index);
1180 for (i = 0; i < card->sbnr.min; i++) {
1181 sb = dev_alloc_skb(NS_SMSKBSIZE);
1182 if (sb == NULL) {
1183 writel(readl(card->membase + CFG) &
1184 ~NS_CFG_EFBIE, card->membase + CFG);
1185 card->efbie = 0;
1186 break;
1187 }
1188 NS_PRV_BUFTYPE(sb) = BUF_SM;
1189 skb_queue_tail(&card->sbpool.queue, sb);
1190 skb_reserve(sb, NS_AAL0_HEADER);
1191 push_rxbufs(card, sb);
1192 }
1193 card->sbfqc = i;
1194 process_rsq(card);
1195 }
1196
1197 /* Large buffer queue empty */
1198 if (stat_r & NS_STAT_LFBQE) {
1199 int i;
1200 struct sk_buff *lb;
1201
1202 writel(NS_STAT_LFBQE, card->membase + STAT);
1203 printk("nicstar%d: Large free buffer queue empty.\n",
1204 card->index);
1205 for (i = 0; i < card->lbnr.min; i++) {
1206 lb = dev_alloc_skb(NS_LGSKBSIZE);
1207 if (lb == NULL) {
1208 writel(readl(card->membase + CFG) &
1209 ~NS_CFG_EFBIE, card->membase + CFG);
1210 card->efbie = 0;
1211 break;
1212 }
1213 NS_PRV_BUFTYPE(lb) = BUF_LG;
1214 skb_queue_tail(&card->lbpool.queue, lb);
1215 skb_reserve(lb, NS_SMBUFSIZE);
1216 push_rxbufs(card, lb);
1217 }
1218 card->lbfqc = i;
1219 process_rsq(card);
1220 }
1221
1222 /* Receive Status Queue is 7/8 full */
1223 if (stat_r & NS_STAT_RSQAF) {
1224 writel(NS_STAT_RSQAF, card->membase + STAT);
1225 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1226 process_rsq(card);
1227 }
1228
1229 spin_unlock_irqrestore(&card->int_lock, flags);
1230 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1231 return IRQ_HANDLED;
1232}
1233
1234static int ns_open(struct atm_vcc *vcc)
1235{
1236 ns_dev *card;
1237 vc_map *vc;
1238 unsigned long tmpl, modl;
1239 int tcr, tcra; /* target cell rate, and absolute value */
1240 int n = 0; /* Number of entries in the TST. Initialized to remove
1241 the compiler warning. */
1242 u32 u32d[4];
1243 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler
1244 warning. How I wish compilers were clever enough to
1245 tell which variables can truly be used
1246 uninitialized... */
1247 int inuse; /* tx or rx vc already in use by another vcc */
1248 short vpi = vcc->vpi;
1249 int vci = vcc->vci;
1250
1251 card = (ns_dev *) vcc->dev->dev_data;
1252 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1253 vci);
1254 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1255 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1256 return -EINVAL;
1257 }
1258
1259 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1260 vcc->dev_data = vc;
1261
1262 inuse = 0;
1263 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx)
1264 inuse = 1;
1265 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx)
1266 inuse += 2;
1267 if (inuse) {
1268 printk("nicstar%d: %s vci already in use.\n", card->index,
1269 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
1270 return -EINVAL;
1271 }
1272
1273 set_bit(ATM_VF_ADDR, &vcc->flags);
1274
1275 /* NOTE: You are not allowed to modify an open connection's QOS. To change
1276 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes
1277 needed to do that. */
1278 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) {
1279 scq_info *scq;
1280
1281 set_bit(ATM_VF_PARTIAL, &vcc->flags);
1282 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1283 /* Check requested cell rate and availability of SCD */
1284 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0
1285 && vcc->qos.txtp.min_pcr == 0) {
1286 PRINTK
1287 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n",
1288 card->index);
1289 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1290 clear_bit(ATM_VF_ADDR, &vcc->flags);
1291 return -EINVAL;
1292 }
1293
1294 tcr = atm_pcr_goal(&(vcc->qos.txtp));
1295 tcra = tcr >= 0 ? tcr : -tcr;
1296
1297 PRINTK("nicstar%d: target cell rate = %d.\n",
1298 card->index, vcc->qos.txtp.max_pcr);
1299
1300 tmpl =
1301 (unsigned long)tcra *(unsigned long)
1302 NS_TST_NUM_ENTRIES;
1303 modl = tmpl % card->max_pcr;
1304
1305 n = (int)(tmpl / card->max_pcr);
1306 if (tcr > 0) {
1307 if (modl > 0)
1308 n++;
1309 } else if (tcr == 0) {
1310 if ((n =
1311 (card->tst_free_entries -
1312 NS_TST_RESERVED)) <= 0) {
1313 PRINTK
1314 ("nicstar%d: no CBR bandwidth free.\n",
1315 card->index);
1316 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1317 clear_bit(ATM_VF_ADDR, &vcc->flags);
1318 return -EINVAL;
1319 }
1320 }
1321
1322 if (n == 0) {
1323 printk
1324 ("nicstar%d: selected bandwidth < granularity.\n",
1325 card->index);
1326 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1327 clear_bit(ATM_VF_ADDR, &vcc->flags);
1328 return -EINVAL;
1329 }
1330
1331 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1332 PRINTK
1333 ("nicstar%d: not enough free CBR bandwidth.\n",
1334 card->index);
1335 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1336 clear_bit(ATM_VF_ADDR, &vcc->flags);
1337 return -EINVAL;
1338 } else
1339 card->tst_free_entries -= n;
1340
1341 XPRINTK("nicstar%d: writing %d tst entries.\n",
1342 card->index, n);
1343 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) {
1344 if (card->scd2vc[frscdi] == NULL) {
1345 card->scd2vc[frscdi] = vc;
1346 break;
1347 }
1348 }
1349 if (frscdi == NS_FRSCD_NUM) {
1350 PRINTK
1351 ("nicstar%d: no SCD available for CBR channel.\n",
1352 card->index);
1353 card->tst_free_entries += n;
1354 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1355 clear_bit(ATM_VF_ADDR, &vcc->flags);
1356 return -EBUSY;
1357 }
1358
1359 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE;
1360
1361 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1362 if (scq == NULL) {
1363 PRINTK("nicstar%d: can't get fixed rate SCQ.\n",
1364 card->index);
1365 card->scd2vc[frscdi] = NULL;
1366 card->tst_free_entries += n;
1367 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1368 clear_bit(ATM_VF_ADDR, &vcc->flags);
1369 return -ENOMEM;
1370 }
1371 vc->scq = scq;
1372 u32d[0] = scq_virt_to_bus(scq, scq->base);
1373 u32d[1] = (u32) 0x00000000;
1374 u32d[2] = (u32) 0xffffffff;
1375 u32d[3] = (u32) 0x00000000;
1376 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1377
1378 fill_tst(card, n, vc);
1379 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) {
1380 vc->cbr_scd = 0x00000000;
1381 vc->scq = card->scq0;
1382 }
1383
1384 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1385 vc->tx = 1;
1386 vc->tx_vcc = vcc;
1387 vc->tbd_count = 0;
1388 }
1389 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1390 u32 status;
1391
1392 vc->rx = 1;
1393 vc->rx_vcc = vcc;
1394 vc->rx_iov = NULL;
1395
1396 /* Open the connection in hardware */
1397 if (vcc->qos.aal == ATM_AAL5)
1398 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN;
1399 else /* vcc->qos.aal == ATM_AAL0 */
1400 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN;
1401#ifdef RCQ_SUPPORT
1402 status |= NS_RCTE_RAWCELLINTEN;
1403#endif /* RCQ_SUPPORT */
1404 ns_write_sram(card,
1405 NS_RCT +
1406 (vpi << card->vcibits | vci) *
1407 NS_RCT_ENTRY_SIZE, &status, 1);
1408 }
1409
1410 }
1411
1412 set_bit(ATM_VF_READY, &vcc->flags);
1413 return 0;
1414}
1415
1416static void ns_close(struct atm_vcc *vcc)
1417{
1418 vc_map *vc;
1419 ns_dev *card;
1420 u32 data;
1421 int i;
1422
1423 vc = vcc->dev_data;
1424 card = vcc->dev->dev_data;
1425 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1426 (int)vcc->vpi, vcc->vci);
1427
1428 clear_bit(ATM_VF_READY, &vcc->flags);
1429
1430 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
1431 u32 addr;
1432 unsigned long flags;
1433
1434 addr =
1435 NS_RCT +
1436 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1437 spin_lock_irqsave(&card->res_lock, flags);
1438 while (CMD_BUSY(card)) ;
1439 writel(NS_CMD_CLOSE_CONNECTION | addr << 2,
1440 card->membase + CMD);
1441 spin_unlock_irqrestore(&card->res_lock, flags);
1442
1443 vc->rx = 0;
1444 if (vc->rx_iov != NULL) {
1445 struct sk_buff *iovb;
1446 u32 stat;
1447
1448 stat = readl(card->membase + STAT);
1449 card->sbfqc = ns_stat_sfbqc_get(stat);
1450 card->lbfqc = ns_stat_lfbqc_get(stat);
1451
1452 PRINTK
1453 ("nicstar%d: closing a VC with pending rx buffers.\n",
1454 card->index);
1455 iovb = vc->rx_iov;
1456 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1457 NS_PRV_IOVCNT(iovb));
1458 NS_PRV_IOVCNT(iovb) = 0;
1459 spin_lock_irqsave(&card->int_lock, flags);
1460 recycle_iov_buf(card, iovb);
1461 spin_unlock_irqrestore(&card->int_lock, flags);
1462 vc->rx_iov = NULL;
1463 }
1464 }
1465
1466 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1467 vc->tx = 0;
1468 }
1469
1470 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1471 unsigned long flags;
1472 ns_scqe *scqep;
1473 scq_info *scq;
1474
1475 scq = vc->scq;
1476
1477 for (;;) {
1478 spin_lock_irqsave(&scq->lock, flags);
1479 scqep = scq->next;
1480 if (scqep == scq->base)
1481 scqep = scq->last;
1482 else
1483 scqep--;
1484 if (scqep == scq->tail) {
1485 spin_unlock_irqrestore(&scq->lock, flags);
1486 break;
1487 }
1488 /* If the last entry is not a TSR, place one in the SCQ in order to
1489 be able to completely drain it and then close. */
1490 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) {
1491 ns_scqe tsr;
1492 u32 scdi, scqi;
1493 u32 data;
1494 int index;
1495
1496 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1497 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1498 scqi = scq->next - scq->base;
1499 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1500 tsr.word_3 = 0x00000000;
1501 tsr.word_4 = 0x00000000;
1502 *scq->next = tsr;
1503 index = (int)scqi;
1504 scq->skb[index] = NULL;
1505 if (scq->next == scq->last)
1506 scq->next = scq->base;
1507 else
1508 scq->next++;
1509 data = scq_virt_to_bus(scq, scq->next);
1510 ns_write_sram(card, scq->scd, &data, 1);
1511 }
1512 spin_unlock_irqrestore(&scq->lock, flags);
1513 schedule();
1514 }
1515
1516 /* Free all TST entries */
1517 data = NS_TST_OPCODE_VARIABLE;
1518 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) {
1519 if (card->tste2vc[i] == vc) {
1520 ns_write_sram(card, card->tst_addr + i, &data,
1521 1);
1522 card->tste2vc[i] = NULL;
1523 card->tst_free_entries++;
1524 }
1525 }
1526
1527 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1528 free_scq(card, vc->scq, vcc);
1529 }
1530
1531 /* remove all references to vcc before deleting it */
1532 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
1533 unsigned long flags;
1534 scq_info *scq = card->scq0;
1535
1536 spin_lock_irqsave(&scq->lock, flags);
1537
1538 for (i = 0; i < scq->num_entries; i++) {
1539 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) {
1540 ATM_SKB(scq->skb[i])->vcc = NULL;
1541 atm_return(vcc, scq->skb[i]->truesize);
1542 PRINTK
1543 ("nicstar: deleted pending vcc mapping\n");
1544 }
1545 }
1546
1547 spin_unlock_irqrestore(&scq->lock, flags);
1548 }
1549
1550 vcc->dev_data = NULL;
1551 clear_bit(ATM_VF_PARTIAL, &vcc->flags);
1552 clear_bit(ATM_VF_ADDR, &vcc->flags);
1553
1554#ifdef RX_DEBUG
1555 {
1556 u32 stat, cfg;
1557 stat = readl(card->membase + STAT);
1558 cfg = readl(card->membase + CFG);
1559 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg);
1560 printk
1561 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n",
1562 card->tsq.base, card->tsq.next,
1563 card->tsq.last, readl(card->membase + TSQT));
1564 printk
1565 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n",
1566 card->rsq.base, card->rsq.next,
1567 card->rsq.last, readl(card->membase + RSQT));
1568 printk("Empty free buffer queue interrupt %s \n",
1569 card->efbie ? "enabled" : "disabled");
1570 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n",
1571 ns_stat_sfbqc_get(stat), card->sbpool.count,
1572 ns_stat_lfbqc_get(stat), card->lbpool.count);
1573 printk("hbpool.count = %d iovpool.count = %d \n",
1574 card->hbpool.count, card->iovpool.count);
1575 }
1576#endif /* RX_DEBUG */
1577}
1578
1579static void fill_tst(ns_dev * card, int n, vc_map * vc)
1580{
1581 u32 new_tst;
1582 unsigned long cl;
1583 int e, r;
1584 u32 data;
1585
1586 /* It would be very complicated to keep the two TSTs synchronized while
1587 assuring that writes are only made to the inactive TST. So, for now I
1588 will use only one TST. If problems occur, I will change this again */
1589
1590 new_tst = card->tst_addr;
1591
1592 /* Fill procedure */
1593
1594 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) {
1595 if (card->tste2vc[e] == NULL)
1596 break;
1597 }
1598 if (e == NS_TST_NUM_ENTRIES) {
1599 printk("nicstar%d: No free TST entries found. \n", card->index);
1600 return;
1601 }
1602
1603 r = n;
1604 cl = NS_TST_NUM_ENTRIES;
1605 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd);
1606
1607 while (r > 0) {
1608 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1609 card->tste2vc[e] = vc;
1610 ns_write_sram(card, new_tst + e, &data, 1);
1611 cl -= NS_TST_NUM_ENTRIES;
1612 r--;
1613 }
1614
1615 if (++e == NS_TST_NUM_ENTRIES) {
1616 e = 0;
1617 }
1618 cl += n;
1619 }
1620
1621 /* End of fill procedure */
1622
1623 data = ns_tste_make(NS_TST_OPCODE_END, new_tst);
1624 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1625 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1626 card->tst_addr = new_tst;
1627}
1628
1629static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb)
1630{
1631 ns_dev *card;
1632 vc_map *vc;
1633 scq_info *scq;
1634 unsigned long buflen;
1635 ns_scqe scqe;
1636 u32 flags; /* TBD flags, not CPU flags */
1637
1638 card = vcc->dev->dev_data;
1639 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1640 if ((vc = (vc_map *) vcc->dev_data) == NULL) {
1641 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n",
1642 card->index);
1643 atomic_inc(&vcc->stats->tx_err);
1644 dev_kfree_skb_any(skb);
1645 return -EINVAL;
1646 }
1647
1648 if (!vc->tx) {
1649 printk("nicstar%d: Trying to transmit on a non-tx VC.\n",
1650 card->index);
1651 atomic_inc(&vcc->stats->tx_err);
1652 dev_kfree_skb_any(skb);
1653 return -EINVAL;
1654 }
1655
1656 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) {
1657 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n",
1658 card->index);
1659 atomic_inc(&vcc->stats->tx_err);
1660 dev_kfree_skb_any(skb);
1661 return -EINVAL;
1662 }
1663
1664 if (skb_shinfo(skb)->nr_frags != 0) {
1665 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1666 atomic_inc(&vcc->stats->tx_err);
1667 dev_kfree_skb_any(skb);
1668 return -EINVAL;
1669 }
1670
1671 ATM_SKB(skb)->vcc = vcc;
1672
1673 NS_PRV_DMA(skb) = pci_map_single(card->pcidev, skb->data,
1674 skb->len, PCI_DMA_TODEVICE);
1675
1676 if (vcc->qos.aal == ATM_AAL5) {
1677 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */
1678 flags = NS_TBD_AAL5;
1679 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb));
1680 scqe.word_3 = cpu_to_le32(skb->len);
1681 scqe.word_4 =
1682 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0,
1683 ATM_SKB(skb)->
1684 atm_options & ATM_ATMOPT_CLP ? 1 : 0);
1685 flags |= NS_TBD_EOPDU;
1686 } else { /* (vcc->qos.aal == ATM_AAL0) */
1687
1688 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */
1689 flags = NS_TBD_AAL0;
1690 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER);
1691 scqe.word_3 = cpu_to_le32(0x00000000);
1692 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */
1693 flags |= NS_TBD_EOPDU;
1694 scqe.word_4 =
1695 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK);
1696 /* Force the VPI/VCI to be the same as in VCC struct */
1697 scqe.word_4 |=
1698 cpu_to_le32((((u32) vcc->
1699 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc->
1700 vci) <<
1701 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK);
1702 }
1703
1704 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1705 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen);
1706 scq = ((vc_map *) vcc->dev_data)->scq;
1707 } else {
1708 scqe.word_1 =
1709 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen);
1710 scq = card->scq0;
1711 }
1712
1713 if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
1714 atomic_inc(&vcc->stats->tx_err);
1715 dev_kfree_skb_any(skb);
1716 return -EIO;
1717 }
1718 atomic_inc(&vcc->stats->tx);
1719
1720 return 0;
1721}
1722
1723static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1724 struct sk_buff *skb)
1725{
1726 unsigned long flags;
1727 ns_scqe tsr;
1728 u32 scdi, scqi;
1729 int scq_is_vbr;
1730 u32 data;
1731 int index;
1732
1733 spin_lock_irqsave(&scq->lock, flags);
1734 while (scq->tail == scq->next) {
1735 if (in_interrupt()) {
1736 spin_unlock_irqrestore(&scq->lock, flags);
1737 printk("nicstar%d: Error pushing TBD.\n", card->index);
1738 return 1;
1739 }
1740
1741 scq->full = 1;
1742 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1743 scq->tail != scq->next,
1744 scq->lock,
1745 SCQFULL_TIMEOUT);
1746
1747 if (scq->full) {
1748 spin_unlock_irqrestore(&scq->lock, flags);
1749 printk("nicstar%d: Timeout pushing TBD.\n",
1750 card->index);
1751 return 1;
1752 }
1753 }
1754 *scq->next = *tbd;
1755 index = (int)(scq->next - scq->base);
1756 scq->skb[index] = skb;
1757 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n",
1758 card->index, skb, index);
1759 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1760 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1761 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4),
1762 scq->next);
1763 if (scq->next == scq->last)
1764 scq->next = scq->base;
1765 else
1766 scq->next++;
1767
1768 vc->tbd_count++;
1769 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) {
1770 scq->tbd_count++;
1771 scq_is_vbr = 1;
1772 } else
1773 scq_is_vbr = 0;
1774
1775 if (vc->tbd_count >= MAX_TBD_PER_VC
1776 || scq->tbd_count >= MAX_TBD_PER_SCQ) {
1777 int has_run = 0;
1778
1779 while (scq->tail == scq->next) {
1780 if (in_interrupt()) {
1781 data = scq_virt_to_bus(scq, scq->next);
1782 ns_write_sram(card, scq->scd, &data, 1);
1783 spin_unlock_irqrestore(&scq->lock, flags);
1784 printk("nicstar%d: Error pushing TSR.\n",
1785 card->index);
1786 return 0;
1787 }
1788
1789 scq->full = 1;
1790 if (has_run++)
1791 break;
1792 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq,
1793 scq->tail != scq->next,
1794 scq->lock,
1795 SCQFULL_TIMEOUT);
1796 }
1797
1798 if (!scq->full) {
1799 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE);
1800 if (scq_is_vbr)
1801 scdi = NS_TSR_SCDISVBR;
1802 else
1803 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE;
1804 scqi = scq->next - scq->base;
1805 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi);
1806 tsr.word_3 = 0x00000000;
1807 tsr.word_4 = 0x00000000;
1808
1809 *scq->next = tsr;
1810 index = (int)scqi;
1811 scq->skb[index] = NULL;
1812 XPRINTK
1813 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n",
1814 card->index, le32_to_cpu(tsr.word_1),
1815 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3),
1816 le32_to_cpu(tsr.word_4), scq->next);
1817 if (scq->next == scq->last)
1818 scq->next = scq->base;
1819 else
1820 scq->next++;
1821 vc->tbd_count = 0;
1822 scq->tbd_count = 0;
1823 } else
1824 PRINTK("nicstar%d: Timeout pushing TSR.\n",
1825 card->index);
1826 }
1827 data = scq_virt_to_bus(scq, scq->next);
1828 ns_write_sram(card, scq->scd, &data, 1);
1829
1830 spin_unlock_irqrestore(&scq->lock, flags);
1831
1832 return 0;
1833}
1834
1835static void process_tsq(ns_dev * card)
1836{
1837 u32 scdi;
1838 scq_info *scq;
1839 ns_tsi *previous = NULL, *one_ahead, *two_ahead;
1840 int serviced_entries; /* flag indicating at least on entry was serviced */
1841
1842 serviced_entries = 0;
1843
1844 if (card->tsq.next == card->tsq.last)
1845 one_ahead = card->tsq.base;
1846 else
1847 one_ahead = card->tsq.next + 1;
1848
1849 if (one_ahead == card->tsq.last)
1850 two_ahead = card->tsq.base;
1851 else
1852 two_ahead = one_ahead + 1;
1853
1854 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1855 !ns_tsi_isempty(two_ahead))
1856 /* At most two empty, as stated in the 77201 errata */
1857 {
1858 serviced_entries = 1;
1859
1860 /* Skip the one or two possible empty entries */
1861 while (ns_tsi_isempty(card->tsq.next)) {
1862 if (card->tsq.next == card->tsq.last)
1863 card->tsq.next = card->tsq.base;
1864 else
1865 card->tsq.next++;
1866 }
1867
1868 if (!ns_tsi_tmrof(card->tsq.next)) {
1869 scdi = ns_tsi_getscdindex(card->tsq.next);
1870 if (scdi == NS_TSI_SCDISVBR)
1871 scq = card->scq0;
1872 else {
1873 if (card->scd2vc[scdi] == NULL) {
1874 printk
1875 ("nicstar%d: could not find VC from SCD index.\n",
1876 card->index);
1877 ns_tsi_init(card->tsq.next);
1878 return;
1879 }
1880 scq = card->scd2vc[scdi]->scq;
1881 }
1882 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1883 scq->full = 0;
1884 wake_up_interruptible(&(scq->scqfull_waitq));
1885 }
1886
1887 ns_tsi_init(card->tsq.next);
1888 previous = card->tsq.next;
1889 if (card->tsq.next == card->tsq.last)
1890 card->tsq.next = card->tsq.base;
1891 else
1892 card->tsq.next++;
1893
1894 if (card->tsq.next == card->tsq.last)
1895 one_ahead = card->tsq.base;
1896 else
1897 one_ahead = card->tsq.next + 1;
1898
1899 if (one_ahead == card->tsq.last)
1900 two_ahead = card->tsq.base;
1901 else
1902 two_ahead = one_ahead + 1;
1903 }
1904
1905 if (serviced_entries)
1906 writel(PTR_DIFF(previous, card->tsq.base),
1907 card->membase + TSQH);
1908}
1909
1910static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1911{
1912 struct atm_vcc *vcc;
1913 struct sk_buff *skb;
1914 int i;
1915 unsigned long flags;
1916
1917 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n",
1918 card->index, scq, pos);
1919 if (pos >= scq->num_entries) {
1920 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1921 return;
1922 }
1923
1924 spin_lock_irqsave(&scq->lock, flags);
1925 i = (int)(scq->tail - scq->base);
1926 if (++i == scq->num_entries)
1927 i = 0;
1928 while (i != pos) {
1929 skb = scq->skb[i];
1930 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n",
1931 card->index, skb, i);
1932 if (skb != NULL) {
1933 pci_unmap_single(card->pcidev,
1934 NS_PRV_DMA(skb),
1935 skb->len,
1936 PCI_DMA_TODEVICE);
1937 vcc = ATM_SKB(skb)->vcc;
1938 if (vcc && vcc->pop != NULL) {
1939 vcc->pop(vcc, skb);
1940 } else {
1941 dev_kfree_skb_irq(skb);
1942 }
1943 scq->skb[i] = NULL;
1944 }
1945 if (++i == scq->num_entries)
1946 i = 0;
1947 }
1948 scq->tail = scq->base + pos;
1949 spin_unlock_irqrestore(&scq->lock, flags);
1950}
1951
1952static void process_rsq(ns_dev * card)
1953{
1954 ns_rsqe *previous;
1955
1956 if (!ns_rsqe_valid(card->rsq.next))
1957 return;
1958 do {
1959 dequeue_rx(card, card->rsq.next);
1960 ns_rsqe_init(card->rsq.next);
1961 previous = card->rsq.next;
1962 if (card->rsq.next == card->rsq.last)
1963 card->rsq.next = card->rsq.base;
1964 else
1965 card->rsq.next++;
1966 } while (ns_rsqe_valid(card->rsq.next));
1967 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1968}
1969
1970static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1971{
1972 u32 vpi, vci;
1973 vc_map *vc;
1974 struct sk_buff *iovb;
1975 struct iovec *iov;
1976 struct atm_vcc *vcc;
1977 struct sk_buff *skb;
1978 unsigned short aal5_len;
1979 int len;
1980 u32 stat;
1981 u32 id;
1982
1983 stat = readl(card->membase + STAT);
1984 card->sbfqc = ns_stat_sfbqc_get(stat);
1985 card->lbfqc = ns_stat_lfbqc_get(stat);
1986
1987 id = le32_to_cpu(rsqe->buffer_handle);
1988 skb = idr_find(&card->idr, id);
1989 if (!skb) {
1990 RXPRINTK(KERN_ERR
1991 "nicstar%d: idr_find() failed!\n", card->index);
1992 return;
1993 }
1994 idr_remove(&card->idr, id);
1995 pci_dma_sync_single_for_cpu(card->pcidev,
1996 NS_PRV_DMA(skb),
1997 (NS_PRV_BUFTYPE(skb) == BUF_SM
1998 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
1999 PCI_DMA_FROMDEVICE);
2000 pci_unmap_single(card->pcidev,
2001 NS_PRV_DMA(skb),
2002 (NS_PRV_BUFTYPE(skb) == BUF_SM
2003 ? NS_SMSKBSIZE : NS_LGSKBSIZE),
2004 PCI_DMA_FROMDEVICE);
2005 vpi = ns_rsqe_vpi(rsqe);
2006 vci = ns_rsqe_vci(rsqe);
2007 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2008 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n",
2009 card->index, vpi, vci);
2010 recycle_rx_buf(card, skb);
2011 return;
2012 }
2013
2014 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2015 if (!vc->rx) {
2016 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n",
2017 card->index, vpi, vci);
2018 recycle_rx_buf(card, skb);
2019 return;
2020 }
2021
2022 vcc = vc->rx_vcc;
2023
2024 if (vcc->qos.aal == ATM_AAL0) {
2025 struct sk_buff *sb;
2026 unsigned char *cell;
2027 int i;
2028
2029 cell = skb->data;
2030 for (i = ns_rsqe_cellcount(rsqe); i; i--) {
2031 if ((sb = dev_alloc_skb(NS_SMSKBSIZE)) == NULL) {
2032 printk
2033 ("nicstar%d: Can't allocate buffers for aal0.\n",
2034 card->index);
2035 atomic_add(i, &vcc->stats->rx_drop);
2036 break;
2037 }
2038 if (!atm_charge(vcc, sb->truesize)) {
2039 RXPRINTK
2040 ("nicstar%d: atm_charge() dropped aal0 packets.\n",
2041 card->index);
2042 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */
2043 dev_kfree_skb_any(sb);
2044 break;
2045 }
2046 /* Rebuild the header */
2047 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 |
2048 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000);
2049 if (i == 1 && ns_rsqe_eopdu(rsqe))
2050 *((u32 *) sb->data) |= 0x00000002;
2051 skb_put(sb, NS_AAL0_HEADER);
2052 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD);
2053 skb_put(sb, ATM_CELL_PAYLOAD);
2054 ATM_SKB(sb)->vcc = vcc;
2055 __net_timestamp(sb);
2056 vcc->push(vcc, sb);
2057 atomic_inc(&vcc->stats->rx);
2058 cell += ATM_CELL_PAYLOAD;
2059 }
2060
2061 recycle_rx_buf(card, skb);
2062 return;
2063 }
2064
2065 /* To reach this point, the AAL layer can only be AAL5 */
2066
2067 if ((iovb = vc->rx_iov) == NULL) {
2068 iovb = skb_dequeue(&(card->iovpool.queue));
2069 if (iovb == NULL) { /* No buffers in the queue */
2070 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC);
2071 if (iovb == NULL) {
2072 printk("nicstar%d: Out of iovec buffers.\n",
2073 card->index);
2074 atomic_inc(&vcc->stats->rx_drop);
2075 recycle_rx_buf(card, skb);
2076 return;
2077 }
2078 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2079 } else if (--card->iovpool.count < card->iovnr.min) {
2080 struct sk_buff *new_iovb;
2081 if ((new_iovb =
2082 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) {
2083 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2084 skb_queue_tail(&card->iovpool.queue, new_iovb);
2085 card->iovpool.count++;
2086 }
2087 }
2088 vc->rx_iov = iovb;
2089 NS_PRV_IOVCNT(iovb) = 0;
2090 iovb->len = 0;
2091 iovb->data = iovb->head;
2092 skb_reset_tail_pointer(iovb);
2093 /* IMPORTANT: a pointer to the sk_buff containing the small or large
2094 buffer is stored as iovec base, NOT a pointer to the
2095 small or large buffer itself. */
2096 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) {
2097 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2098 atomic_inc(&vcc->stats->rx_err);
2099 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2100 NS_MAX_IOVECS);
2101 NS_PRV_IOVCNT(iovb) = 0;
2102 iovb->len = 0;
2103 iovb->data = iovb->head;
2104 skb_reset_tail_pointer(iovb);
2105 }
2106 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++];
2107 iov->iov_base = (void *)skb;
2108 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48;
2109 iovb->len += iov->iov_len;
2110
2111#ifdef EXTRA_DEBUG
2112 if (NS_PRV_IOVCNT(iovb) == 1) {
2113 if (NS_PRV_BUFTYPE(skb) != BUF_SM) {
2114 printk
2115 ("nicstar%d: Expected a small buffer, and this is not one.\n",
2116 card->index);
2117 which_list(card, skb);
2118 atomic_inc(&vcc->stats->rx_err);
2119 recycle_rx_buf(card, skb);
2120 vc->rx_iov = NULL;
2121 recycle_iov_buf(card, iovb);
2122 return;
2123 }
2124 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */
2125
2126 if (NS_PRV_BUFTYPE(skb) != BUF_LG) {
2127 printk
2128 ("nicstar%d: Expected a large buffer, and this is not one.\n",
2129 card->index);
2130 which_list(card, skb);
2131 atomic_inc(&vcc->stats->rx_err);
2132 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2133 NS_PRV_IOVCNT(iovb));
2134 vc->rx_iov = NULL;
2135 recycle_iov_buf(card, iovb);
2136 return;
2137 }
2138 }
2139#endif /* EXTRA_DEBUG */
2140
2141 if (ns_rsqe_eopdu(rsqe)) {
2142 /* This works correctly regardless of the endianness of the host */
2143 unsigned char *L1L2 = (unsigned char *)
2144 (skb->data + iov->iov_len - 6);
2145 aal5_len = L1L2[0] << 8 | L1L2[1];
2146 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len;
2147 if (ns_rsqe_crcerr(rsqe) ||
2148 len + 8 > iovb->len || len + (47 + 8) < iovb->len) {
2149 printk("nicstar%d: AAL5 CRC error", card->index);
2150 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len)
2151 printk(" - PDU size mismatch.\n");
2152 else
2153 printk(".\n");
2154 atomic_inc(&vcc->stats->rx_err);
2155 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2156 NS_PRV_IOVCNT(iovb));
2157 vc->rx_iov = NULL;
2158 recycle_iov_buf(card, iovb);
2159 return;
2160 }
2161
2162 /* By this point we (hopefully) have a complete SDU without errors. */
2163
2164 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */
2165 /* skb points to a small buffer */
2166 if (!atm_charge(vcc, skb->truesize)) {
2167 push_rxbufs(card, skb);
2168 atomic_inc(&vcc->stats->rx_drop);
2169 } else {
2170 skb_put(skb, len);
2171 dequeue_sm_buf(card, skb);
2172#ifdef NS_USE_DESTRUCTORS
2173 skb->destructor = ns_sb_destructor;
2174#endif /* NS_USE_DESTRUCTORS */
2175 ATM_SKB(skb)->vcc = vcc;
2176 __net_timestamp(skb);
2177 vcc->push(vcc, skb);
2178 atomic_inc(&vcc->stats->rx);
2179 }
2180 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */
2181 struct sk_buff *sb;
2182
2183 sb = (struct sk_buff *)(iov - 1)->iov_base;
2184 /* skb points to a large buffer */
2185
2186 if (len <= NS_SMBUFSIZE) {
2187 if (!atm_charge(vcc, sb->truesize)) {
2188 push_rxbufs(card, sb);
2189 atomic_inc(&vcc->stats->rx_drop);
2190 } else {
2191 skb_put(sb, len);
2192 dequeue_sm_buf(card, sb);
2193#ifdef NS_USE_DESTRUCTORS
2194 sb->destructor = ns_sb_destructor;
2195#endif /* NS_USE_DESTRUCTORS */
2196 ATM_SKB(sb)->vcc = vcc;
2197 __net_timestamp(sb);
2198 vcc->push(vcc, sb);
2199 atomic_inc(&vcc->stats->rx);
2200 }
2201
2202 push_rxbufs(card, skb);
2203
2204 } else { /* len > NS_SMBUFSIZE, the usual case */
2205
2206 if (!atm_charge(vcc, skb->truesize)) {
2207 push_rxbufs(card, skb);
2208 atomic_inc(&vcc->stats->rx_drop);
2209 } else {
2210 dequeue_lg_buf(card, skb);
2211#ifdef NS_USE_DESTRUCTORS
2212 skb->destructor = ns_lb_destructor;
2213#endif /* NS_USE_DESTRUCTORS */
2214 skb_push(skb, NS_SMBUFSIZE);
2215 skb_copy_from_linear_data(sb, skb->data,
2216 NS_SMBUFSIZE);
2217 skb_put(skb, len - NS_SMBUFSIZE);
2218 ATM_SKB(skb)->vcc = vcc;
2219 __net_timestamp(skb);
2220 vcc->push(vcc, skb);
2221 atomic_inc(&vcc->stats->rx);
2222 }
2223
2224 push_rxbufs(card, sb);
2225
2226 }
2227
2228 } else { /* Must push a huge buffer */
2229
2230 struct sk_buff *hb, *sb, *lb;
2231 int remaining, tocopy;
2232 int j;
2233
2234 hb = skb_dequeue(&(card->hbpool.queue));
2235 if (hb == NULL) { /* No buffers in the queue */
2236
2237 hb = dev_alloc_skb(NS_HBUFSIZE);
2238 if (hb == NULL) {
2239 printk
2240 ("nicstar%d: Out of huge buffers.\n",
2241 card->index);
2242 atomic_inc(&vcc->stats->rx_drop);
2243 recycle_iovec_rx_bufs(card,
2244 (struct iovec *)
2245 iovb->data,
2246 NS_PRV_IOVCNT(iovb));
2247 vc->rx_iov = NULL;
2248 recycle_iov_buf(card, iovb);
2249 return;
2250 } else if (card->hbpool.count < card->hbnr.min) {
2251 struct sk_buff *new_hb;
2252 if ((new_hb =
2253 dev_alloc_skb(NS_HBUFSIZE)) !=
2254 NULL) {
2255 skb_queue_tail(&card->hbpool.
2256 queue, new_hb);
2257 card->hbpool.count++;
2258 }
2259 }
2260 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2261 } else if (--card->hbpool.count < card->hbnr.min) {
2262 struct sk_buff *new_hb;
2263 if ((new_hb =
2264 dev_alloc_skb(NS_HBUFSIZE)) != NULL) {
2265 NS_PRV_BUFTYPE(new_hb) = BUF_NONE;
2266 skb_queue_tail(&card->hbpool.queue,
2267 new_hb);
2268 card->hbpool.count++;
2269 }
2270 if (card->hbpool.count < card->hbnr.min) {
2271 if ((new_hb =
2272 dev_alloc_skb(NS_HBUFSIZE)) !=
2273 NULL) {
2274 NS_PRV_BUFTYPE(new_hb) =
2275 BUF_NONE;
2276 skb_queue_tail(&card->hbpool.
2277 queue, new_hb);
2278 card->hbpool.count++;
2279 }
2280 }
2281 }
2282
2283 iov = (struct iovec *)iovb->data;
2284
2285 if (!atm_charge(vcc, hb->truesize)) {
2286 recycle_iovec_rx_bufs(card, iov,
2287 NS_PRV_IOVCNT(iovb));
2288 if (card->hbpool.count < card->hbnr.max) {
2289 skb_queue_tail(&card->hbpool.queue, hb);
2290 card->hbpool.count++;
2291 } else
2292 dev_kfree_skb_any(hb);
2293 atomic_inc(&vcc->stats->rx_drop);
2294 } else {
2295 /* Copy the small buffer to the huge buffer */
2296 sb = (struct sk_buff *)iov->iov_base;
2297 skb_copy_from_linear_data(sb, hb->data,
2298 iov->iov_len);
2299 skb_put(hb, iov->iov_len);
2300 remaining = len - iov->iov_len;
2301 iov++;
2302 /* Free the small buffer */
2303 push_rxbufs(card, sb);
2304
2305 /* Copy all large buffers to the huge buffer and free them */
2306 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) {
2307 lb = (struct sk_buff *)iov->iov_base;
2308 tocopy =
2309 min_t(int, remaining, iov->iov_len);
2310 skb_copy_from_linear_data(lb,
2311 skb_tail_pointer
2312 (hb), tocopy);
2313 skb_put(hb, tocopy);
2314 iov++;
2315 remaining -= tocopy;
2316 push_rxbufs(card, lb);
2317 }
2318#ifdef EXTRA_DEBUG
2319 if (remaining != 0 || hb->len != len)
2320 printk
2321 ("nicstar%d: Huge buffer len mismatch.\n",
2322 card->index);
2323#endif /* EXTRA_DEBUG */
2324 ATM_SKB(hb)->vcc = vcc;
2325#ifdef NS_USE_DESTRUCTORS
2326 hb->destructor = ns_hb_destructor;
2327#endif /* NS_USE_DESTRUCTORS */
2328 __net_timestamp(hb);
2329 vcc->push(vcc, hb);
2330 atomic_inc(&vcc->stats->rx);
2331 }
2332 }
2333
2334 vc->rx_iov = NULL;
2335 recycle_iov_buf(card, iovb);
2336 }
2337
2338}
2339
2340#ifdef NS_USE_DESTRUCTORS
2341
2342static void ns_sb_destructor(struct sk_buff *sb)
2343{
2344 ns_dev *card;
2345 u32 stat;
2346
2347 card = (ns_dev *) ATM_SKB(sb)->vcc->dev->dev_data;
2348 stat = readl(card->membase + STAT);
2349 card->sbfqc = ns_stat_sfbqc_get(stat);
2350 card->lbfqc = ns_stat_lfbqc_get(stat);
2351
2352 do {
2353 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2354 if (sb == NULL)
2355 break;
2356 NS_PRV_BUFTYPE(sb) = BUF_SM;
2357 skb_queue_tail(&card->sbpool.queue, sb);
2358 skb_reserve(sb, NS_AAL0_HEADER);
2359 push_rxbufs(card, sb);
2360 } while (card->sbfqc < card->sbnr.min);
2361}
2362
2363static void ns_lb_destructor(struct sk_buff *lb)
2364{
2365 ns_dev *card;
2366 u32 stat;
2367
2368 card = (ns_dev *) ATM_SKB(lb)->vcc->dev->dev_data;
2369 stat = readl(card->membase + STAT);
2370 card->sbfqc = ns_stat_sfbqc_get(stat);
2371 card->lbfqc = ns_stat_lfbqc_get(stat);
2372
2373 do {
2374 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2375 if (lb == NULL)
2376 break;
2377 NS_PRV_BUFTYPE(lb) = BUF_LG;
2378 skb_queue_tail(&card->lbpool.queue, lb);
2379 skb_reserve(lb, NS_SMBUFSIZE);
2380 push_rxbufs(card, lb);
2381 } while (card->lbfqc < card->lbnr.min);
2382}
2383
2384static void ns_hb_destructor(struct sk_buff *hb)
2385{
2386 ns_dev *card;
2387
2388 card = (ns_dev *) ATM_SKB(hb)->vcc->dev->dev_data;
2389
2390 while (card->hbpool.count < card->hbnr.init) {
2391 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2392 if (hb == NULL)
2393 break;
2394 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2395 skb_queue_tail(&card->hbpool.queue, hb);
2396 card->hbpool.count++;
2397 }
2398}
2399
2400#endif /* NS_USE_DESTRUCTORS */
2401
2402static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2403{
2404 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) {
2405 printk("nicstar%d: What kind of rx buffer is this?\n",
2406 card->index);
2407 dev_kfree_skb_any(skb);
2408 } else
2409 push_rxbufs(card, skb);
2410}
2411
2412static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2413{
2414 while (count-- > 0)
2415 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2416}
2417
2418static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2419{
2420 if (card->iovpool.count < card->iovnr.max) {
2421 skb_queue_tail(&card->iovpool.queue, iovb);
2422 card->iovpool.count++;
2423 } else
2424 dev_kfree_skb_any(iovb);
2425}
2426
2427static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2428{
2429 skb_unlink(sb, &card->sbpool.queue);
2430#ifdef NS_USE_DESTRUCTORS
2431 if (card->sbfqc < card->sbnr.min)
2432#else
2433 if (card->sbfqc < card->sbnr.init) {
2434 struct sk_buff *new_sb;
2435 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2436 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2437 skb_queue_tail(&card->sbpool.queue, new_sb);
2438 skb_reserve(new_sb, NS_AAL0_HEADER);
2439 push_rxbufs(card, new_sb);
2440 }
2441 }
2442 if (card->sbfqc < card->sbnr.init)
2443#endif /* NS_USE_DESTRUCTORS */
2444 {
2445 struct sk_buff *new_sb;
2446 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) {
2447 NS_PRV_BUFTYPE(new_sb) = BUF_SM;
2448 skb_queue_tail(&card->sbpool.queue, new_sb);
2449 skb_reserve(new_sb, NS_AAL0_HEADER);
2450 push_rxbufs(card, new_sb);
2451 }
2452 }
2453}
2454
2455static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2456{
2457 skb_unlink(lb, &card->lbpool.queue);
2458#ifdef NS_USE_DESTRUCTORS
2459 if (card->lbfqc < card->lbnr.min)
2460#else
2461 if (card->lbfqc < card->lbnr.init) {
2462 struct sk_buff *new_lb;
2463 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2464 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2465 skb_queue_tail(&card->lbpool.queue, new_lb);
2466 skb_reserve(new_lb, NS_SMBUFSIZE);
2467 push_rxbufs(card, new_lb);
2468 }
2469 }
2470 if (card->lbfqc < card->lbnr.init)
2471#endif /* NS_USE_DESTRUCTORS */
2472 {
2473 struct sk_buff *new_lb;
2474 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) {
2475 NS_PRV_BUFTYPE(new_lb) = BUF_LG;
2476 skb_queue_tail(&card->lbpool.queue, new_lb);
2477 skb_reserve(new_lb, NS_SMBUFSIZE);
2478 push_rxbufs(card, new_lb);
2479 }
2480 }
2481}
2482
2483static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2484{
2485 u32 stat;
2486 ns_dev *card;
2487 int left;
2488
2489 left = (int)*pos;
2490 card = (ns_dev *) dev->dev_data;
2491 stat = readl(card->membase + STAT);
2492 if (!left--)
2493 return sprintf(page, "Pool count min init max \n");
2494 if (!left--)
2495 return sprintf(page, "Small %5d %5d %5d %5d \n",
2496 ns_stat_sfbqc_get(stat), card->sbnr.min,
2497 card->sbnr.init, card->sbnr.max);
2498 if (!left--)
2499 return sprintf(page, "Large %5d %5d %5d %5d \n",
2500 ns_stat_lfbqc_get(stat), card->lbnr.min,
2501 card->lbnr.init, card->lbnr.max);
2502 if (!left--)
2503 return sprintf(page, "Huge %5d %5d %5d %5d \n",
2504 card->hbpool.count, card->hbnr.min,
2505 card->hbnr.init, card->hbnr.max);
2506 if (!left--)
2507 return sprintf(page, "Iovec %5d %5d %5d %5d \n",
2508 card->iovpool.count, card->iovnr.min,
2509 card->iovnr.init, card->iovnr.max);
2510 if (!left--) {
2511 int retval;
2512 retval =
2513 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2514 card->intcnt = 0;
2515 return retval;
2516 }
2517#if 0
2518 /* Dump 25.6 Mbps PHY registers */
2519 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it
2520 here just in case it's needed for debugging. */
2521 if (card->max_pcr == ATM_25_PCR && !left--) {
2522 u32 phy_regs[4];
2523 u32 i;
2524
2525 for (i = 0; i < 4; i++) {
2526 while (CMD_BUSY(card)) ;
2527 writel(NS_CMD_READ_UTILITY | 0x00000200 | i,
2528 card->membase + CMD);
2529 while (CMD_BUSY(card)) ;
2530 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2531 }
2532
2533 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n",
2534 phy_regs[0], phy_regs[1], phy_regs[2],
2535 phy_regs[3]);
2536 }
2537#endif /* 0 - Dump 25.6 Mbps PHY registers */
2538#if 0
2539 /* Dump TST */
2540 if (left-- < NS_TST_NUM_ENTRIES) {
2541 if (card->tste2vc[left + 1] == NULL)
2542 return sprintf(page, "%5d - VBR/UBR \n", left + 1);
2543 else
2544 return sprintf(page, "%5d - %d %d \n", left + 1,
2545 card->tste2vc[left + 1]->tx_vcc->vpi,
2546 card->tste2vc[left + 1]->tx_vcc->vci);
2547 }
2548#endif /* 0 */
2549 return 0;
2550}
2551
2552static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg)
2553{
2554 ns_dev *card;
2555 pool_levels pl;
2556 long btype;
2557 unsigned long flags;
2558
2559 card = dev->dev_data;
2560 switch (cmd) {
2561 case NS_GETPSTAT:
2562 if (get_user
2563 (pl.buftype, &((pool_levels __user *) arg)->buftype))
2564 return -EFAULT;
2565 switch (pl.buftype) {
2566 case NS_BUFTYPE_SMALL:
2567 pl.count =
2568 ns_stat_sfbqc_get(readl(card->membase + STAT));
2569 pl.level.min = card->sbnr.min;
2570 pl.level.init = card->sbnr.init;
2571 pl.level.max = card->sbnr.max;
2572 break;
2573
2574 case NS_BUFTYPE_LARGE:
2575 pl.count =
2576 ns_stat_lfbqc_get(readl(card->membase + STAT));
2577 pl.level.min = card->lbnr.min;
2578 pl.level.init = card->lbnr.init;
2579 pl.level.max = card->lbnr.max;
2580 break;
2581
2582 case NS_BUFTYPE_HUGE:
2583 pl.count = card->hbpool.count;
2584 pl.level.min = card->hbnr.min;
2585 pl.level.init = card->hbnr.init;
2586 pl.level.max = card->hbnr.max;
2587 break;
2588
2589 case NS_BUFTYPE_IOVEC:
2590 pl.count = card->iovpool.count;
2591 pl.level.min = card->iovnr.min;
2592 pl.level.init = card->iovnr.init;
2593 pl.level.max = card->iovnr.max;
2594 break;
2595
2596 default:
2597 return -ENOIOCTLCMD;
2598
2599 }
2600 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl)))
2601 return (sizeof(pl));
2602 else
2603 return -EFAULT;
2604
2605 case NS_SETBUFLEV:
2606 if (!capable(CAP_NET_ADMIN))
2607 return -EPERM;
2608 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl)))
2609 return -EFAULT;
2610 if (pl.level.min >= pl.level.init
2611 || pl.level.init >= pl.level.max)
2612 return -EINVAL;
2613 if (pl.level.min == 0)
2614 return -EINVAL;
2615 switch (pl.buftype) {
2616 case NS_BUFTYPE_SMALL:
2617 if (pl.level.max > TOP_SB)
2618 return -EINVAL;
2619 card->sbnr.min = pl.level.min;
2620 card->sbnr.init = pl.level.init;
2621 card->sbnr.max = pl.level.max;
2622 break;
2623
2624 case NS_BUFTYPE_LARGE:
2625 if (pl.level.max > TOP_LB)
2626 return -EINVAL;
2627 card->lbnr.min = pl.level.min;
2628 card->lbnr.init = pl.level.init;
2629 card->lbnr.max = pl.level.max;
2630 break;
2631
2632 case NS_BUFTYPE_HUGE:
2633 if (pl.level.max > TOP_HB)
2634 return -EINVAL;
2635 card->hbnr.min = pl.level.min;
2636 card->hbnr.init = pl.level.init;
2637 card->hbnr.max = pl.level.max;
2638 break;
2639
2640 case NS_BUFTYPE_IOVEC:
2641 if (pl.level.max > TOP_IOVB)
2642 return -EINVAL;
2643 card->iovnr.min = pl.level.min;
2644 card->iovnr.init = pl.level.init;
2645 card->iovnr.max = pl.level.max;
2646 break;
2647
2648 default:
2649 return -EINVAL;
2650
2651 }
2652 return 0;
2653
2654 case NS_ADJBUFLEV:
2655 if (!capable(CAP_NET_ADMIN))
2656 return -EPERM;
2657 btype = (long)arg; /* a long is the same size as a pointer or bigger */
2658 switch (btype) {
2659 case NS_BUFTYPE_SMALL:
2660 while (card->sbfqc < card->sbnr.init) {
2661 struct sk_buff *sb;
2662
2663 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL);
2664 if (sb == NULL)
2665 return -ENOMEM;
2666 NS_PRV_BUFTYPE(sb) = BUF_SM;
2667 skb_queue_tail(&card->sbpool.queue, sb);
2668 skb_reserve(sb, NS_AAL0_HEADER);
2669 push_rxbufs(card, sb);
2670 }
2671 break;
2672
2673 case NS_BUFTYPE_LARGE:
2674 while (card->lbfqc < card->lbnr.init) {
2675 struct sk_buff *lb;
2676
2677 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL);
2678 if (lb == NULL)
2679 return -ENOMEM;
2680 NS_PRV_BUFTYPE(lb) = BUF_LG;
2681 skb_queue_tail(&card->lbpool.queue, lb);
2682 skb_reserve(lb, NS_SMBUFSIZE);
2683 push_rxbufs(card, lb);
2684 }
2685 break;
2686
2687 case NS_BUFTYPE_HUGE:
2688 while (card->hbpool.count > card->hbnr.init) {
2689 struct sk_buff *hb;
2690
2691 spin_lock_irqsave(&card->int_lock, flags);
2692 hb = skb_dequeue(&card->hbpool.queue);
2693 card->hbpool.count--;
2694 spin_unlock_irqrestore(&card->int_lock, flags);
2695 if (hb == NULL)
2696 printk
2697 ("nicstar%d: huge buffer count inconsistent.\n",
2698 card->index);
2699 else
2700 dev_kfree_skb_any(hb);
2701
2702 }
2703 while (card->hbpool.count < card->hbnr.init) {
2704 struct sk_buff *hb;
2705
2706 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL);
2707 if (hb == NULL)
2708 return -ENOMEM;
2709 NS_PRV_BUFTYPE(hb) = BUF_NONE;
2710 spin_lock_irqsave(&card->int_lock, flags);
2711 skb_queue_tail(&card->hbpool.queue, hb);
2712 card->hbpool.count++;
2713 spin_unlock_irqrestore(&card->int_lock, flags);
2714 }
2715 break;
2716
2717 case NS_BUFTYPE_IOVEC:
2718 while (card->iovpool.count > card->iovnr.init) {
2719 struct sk_buff *iovb;
2720
2721 spin_lock_irqsave(&card->int_lock, flags);
2722 iovb = skb_dequeue(&card->iovpool.queue);
2723 card->iovpool.count--;
2724 spin_unlock_irqrestore(&card->int_lock, flags);
2725 if (iovb == NULL)
2726 printk
2727 ("nicstar%d: iovec buffer count inconsistent.\n",
2728 card->index);
2729 else
2730 dev_kfree_skb_any(iovb);
2731
2732 }
2733 while (card->iovpool.count < card->iovnr.init) {
2734 struct sk_buff *iovb;
2735
2736 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL);
2737 if (iovb == NULL)
2738 return -ENOMEM;
2739 NS_PRV_BUFTYPE(iovb) = BUF_NONE;
2740 spin_lock_irqsave(&card->int_lock, flags);
2741 skb_queue_tail(&card->iovpool.queue, iovb);
2742 card->iovpool.count++;
2743 spin_unlock_irqrestore(&card->int_lock, flags);
2744 }
2745 break;
2746
2747 default:
2748 return -EINVAL;
2749
2750 }
2751 return 0;
2752
2753 default:
2754 if (dev->phy && dev->phy->ioctl) {
2755 return dev->phy->ioctl(dev, cmd, arg);
2756 } else {
2757 printk("nicstar%d: %s == NULL \n", card->index,
2758 dev->phy ? "dev->phy->ioctl" : "dev->phy");
2759 return -ENOIOCTLCMD;
2760 }
2761 }
2762}
2763
2764#ifdef EXTRA_DEBUG
2765static void which_list(ns_dev * card, struct sk_buff *skb)
2766{
2767 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb));
2768}
2769#endif /* EXTRA_DEBUG */
2770
2771static void ns_poll(unsigned long arg)
2772{
2773 int i;
2774 ns_dev *card;
2775 unsigned long flags;
2776 u32 stat_r, stat_w;
2777
2778 PRINTK("nicstar: Entering ns_poll().\n");
2779 for (i = 0; i < num_cards; i++) {
2780 card = cards[i];
2781 if (spin_is_locked(&card->int_lock)) {
2782 /* Probably it isn't worth spinning */
2783 continue;
2784 }
2785 spin_lock_irqsave(&card->int_lock, flags);
2786
2787 stat_w = 0;
2788 stat_r = readl(card->membase + STAT);
2789 if (stat_r & NS_STAT_TSIF)
2790 stat_w |= NS_STAT_TSIF;
2791 if (stat_r & NS_STAT_EOPDU)
2792 stat_w |= NS_STAT_EOPDU;
2793
2794 process_tsq(card);
2795 process_rsq(card);
2796
2797 writel(stat_w, card->membase + STAT);
2798 spin_unlock_irqrestore(&card->int_lock, flags);
2799 }
2800 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD);
2801 PRINTK("nicstar: Leaving ns_poll().\n");
2802}
2803
2804static void ns_phy_put(struct atm_dev *dev, unsigned char value,
2805 unsigned long addr)
2806{
2807 ns_dev *card;
2808 unsigned long flags;
2809
2810 card = dev->dev_data;
2811 spin_lock_irqsave(&card->res_lock, flags);
2812 while (CMD_BUSY(card)) ;
2813 writel((u32) value, card->membase + DR0);
2814 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF),
2815 card->membase + CMD);
2816 spin_unlock_irqrestore(&card->res_lock, flags);
2817}
2818
2819static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr)
2820{
2821 ns_dev *card;
2822 unsigned long flags;
2823 u32 data;
2824
2825 card = dev->dev_data;
2826 spin_lock_irqsave(&card->res_lock, flags);
2827 while (CMD_BUSY(card)) ;
2828 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF),
2829 card->membase + CMD);
2830 while (CMD_BUSY(card)) ;
2831 data = readl(card->membase + DR0) & 0x000000FF;
2832 spin_unlock_irqrestore(&card->res_lock, flags);
2833 return (unsigned char)data;
2834}
2835
2836module_init(nicstar_init);
2837module_exit(nicstar_cleanup);