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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * Jiang Liu <jiang.liu@linux.intel.com>
8 * Enable support of hierarchical irqdomains
9 */
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12#include <linux/seq_file.h>
13#include <linux/init.h>
14#include <linux/compiler.h>
15#include <linux/slab.h>
16#include <asm/irqdomain.h>
17#include <asm/hw_irq.h>
18#include <asm/traps.h>
19#include <asm/apic.h>
20#include <asm/i8259.h>
21#include <asm/desc.h>
22#include <asm/irq_remapping.h>
23
24#include <asm/trace/irq_vectors.h>
25
26struct apic_chip_data {
27 struct irq_cfg hw_irq_cfg;
28 unsigned int vector;
29 unsigned int prev_vector;
30 unsigned int cpu;
31 unsigned int prev_cpu;
32 unsigned int irq;
33 struct hlist_node clist;
34 unsigned int move_in_progress : 1,
35 is_managed : 1,
36 can_reserve : 1,
37 has_reserved : 1;
38};
39
40struct irq_domain *x86_vector_domain;
41EXPORT_SYMBOL_GPL(x86_vector_domain);
42static DEFINE_RAW_SPINLOCK(vector_lock);
43static cpumask_var_t vector_searchmask;
44static struct irq_chip lapic_controller;
45static struct irq_matrix *vector_matrix;
46#ifdef CONFIG_SMP
47static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
48#endif
49
50void lock_vector_lock(void)
51{
52 /* Used to the online set of cpus does not change
53 * during assign_irq_vector.
54 */
55 raw_spin_lock(&vector_lock);
56}
57
58void unlock_vector_lock(void)
59{
60 raw_spin_unlock(&vector_lock);
61}
62
63void init_irq_alloc_info(struct irq_alloc_info *info,
64 const struct cpumask *mask)
65{
66 memset(info, 0, sizeof(*info));
67 info->mask = mask;
68}
69
70void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
71{
72 if (src)
73 *dst = *src;
74 else
75 memset(dst, 0, sizeof(*dst));
76}
77
78static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
79{
80 if (!irqd)
81 return NULL;
82
83 while (irqd->parent_data)
84 irqd = irqd->parent_data;
85
86 return irqd->chip_data;
87}
88
89struct irq_cfg *irqd_cfg(struct irq_data *irqd)
90{
91 struct apic_chip_data *apicd = apic_chip_data(irqd);
92
93 return apicd ? &apicd->hw_irq_cfg : NULL;
94}
95EXPORT_SYMBOL_GPL(irqd_cfg);
96
97struct irq_cfg *irq_cfg(unsigned int irq)
98{
99 return irqd_cfg(irq_get_irq_data(irq));
100}
101
102static struct apic_chip_data *alloc_apic_chip_data(int node)
103{
104 struct apic_chip_data *apicd;
105
106 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
107 if (apicd)
108 INIT_HLIST_NODE(&apicd->clist);
109 return apicd;
110}
111
112static void free_apic_chip_data(struct apic_chip_data *apicd)
113{
114 kfree(apicd);
115}
116
117static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
118 unsigned int cpu)
119{
120 struct apic_chip_data *apicd = apic_chip_data(irqd);
121
122 lockdep_assert_held(&vector_lock);
123
124 apicd->hw_irq_cfg.vector = vector;
125 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
126 irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
127 trace_vector_config(irqd->irq, vector, cpu,
128 apicd->hw_irq_cfg.dest_apicid);
129}
130
131static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
132 unsigned int newcpu)
133{
134 struct apic_chip_data *apicd = apic_chip_data(irqd);
135 struct irq_desc *desc = irq_data_to_desc(irqd);
136 bool managed = irqd_affinity_is_managed(irqd);
137
138 lockdep_assert_held(&vector_lock);
139
140 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
141 apicd->cpu);
142
143 /*
144 * If there is no vector associated or if the associated vector is
145 * the shutdown vector, which is associated to make PCI/MSI
146 * shutdown mode work, then there is nothing to release. Clear out
147 * prev_vector for this and the offlined target case.
148 */
149 apicd->prev_vector = 0;
150 if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
151 goto setnew;
152 /*
153 * If the target CPU of the previous vector is online, then mark
154 * the vector as move in progress and store it for cleanup when the
155 * first interrupt on the new vector arrives. If the target CPU is
156 * offline then the regular release mechanism via the cleanup
157 * vector is not possible and the vector can be immediately freed
158 * in the underlying matrix allocator.
159 */
160 if (cpu_online(apicd->cpu)) {
161 apicd->move_in_progress = true;
162 apicd->prev_vector = apicd->vector;
163 apicd->prev_cpu = apicd->cpu;
164 WARN_ON_ONCE(apicd->cpu == newcpu);
165 } else {
166 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
167 managed);
168 }
169
170setnew:
171 apicd->vector = newvec;
172 apicd->cpu = newcpu;
173 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
174 per_cpu(vector_irq, newcpu)[newvec] = desc;
175}
176
177static void vector_assign_managed_shutdown(struct irq_data *irqd)
178{
179 unsigned int cpu = cpumask_first(cpu_online_mask);
180
181 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
182}
183
184static int reserve_managed_vector(struct irq_data *irqd)
185{
186 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
187 struct apic_chip_data *apicd = apic_chip_data(irqd);
188 unsigned long flags;
189 int ret;
190
191 raw_spin_lock_irqsave(&vector_lock, flags);
192 apicd->is_managed = true;
193 ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
194 raw_spin_unlock_irqrestore(&vector_lock, flags);
195 trace_vector_reserve_managed(irqd->irq, ret);
196 return ret;
197}
198
199static void reserve_irq_vector_locked(struct irq_data *irqd)
200{
201 struct apic_chip_data *apicd = apic_chip_data(irqd);
202
203 irq_matrix_reserve(vector_matrix);
204 apicd->can_reserve = true;
205 apicd->has_reserved = true;
206 irqd_set_can_reserve(irqd);
207 trace_vector_reserve(irqd->irq, 0);
208 vector_assign_managed_shutdown(irqd);
209}
210
211static int reserve_irq_vector(struct irq_data *irqd)
212{
213 unsigned long flags;
214
215 raw_spin_lock_irqsave(&vector_lock, flags);
216 reserve_irq_vector_locked(irqd);
217 raw_spin_unlock_irqrestore(&vector_lock, flags);
218 return 0;
219}
220
221static int
222assign_vector_locked(struct irq_data *irqd, const struct cpumask *dest)
223{
224 struct apic_chip_data *apicd = apic_chip_data(irqd);
225 bool resvd = apicd->has_reserved;
226 unsigned int cpu = apicd->cpu;
227 int vector = apicd->vector;
228
229 lockdep_assert_held(&vector_lock);
230
231 /*
232 * If the current target CPU is online and in the new requested
233 * affinity mask, there is no point in moving the interrupt from
234 * one CPU to another.
235 */
236 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
237 return 0;
238
239 /*
240 * Careful here. @apicd might either have move_in_progress set or
241 * be enqueued for cleanup. Assigning a new vector would either
242 * leave a stale vector on some CPU around or in case of a pending
243 * cleanup corrupt the hlist.
244 */
245 if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist))
246 return -EBUSY;
247
248 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
249 trace_vector_alloc(irqd->irq, vector, resvd, vector);
250 if (vector < 0)
251 return vector;
252 apic_update_vector(irqd, vector, cpu);
253 apic_update_irq_cfg(irqd, vector, cpu);
254
255 return 0;
256}
257
258static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
259{
260 unsigned long flags;
261 int ret;
262
263 raw_spin_lock_irqsave(&vector_lock, flags);
264 cpumask_and(vector_searchmask, dest, cpu_online_mask);
265 ret = assign_vector_locked(irqd, vector_searchmask);
266 raw_spin_unlock_irqrestore(&vector_lock, flags);
267 return ret;
268}
269
270static int assign_irq_vector_any_locked(struct irq_data *irqd)
271{
272 /* Get the affinity mask - either irq_default_affinity or (user) set */
273 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
274 int node = irq_data_get_node(irqd);
275
276 if (node != NUMA_NO_NODE) {
277 /* Try the intersection of @affmsk and node mask */
278 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
279 if (!assign_vector_locked(irqd, vector_searchmask))
280 return 0;
281 }
282
283 /* Try the full affinity mask */
284 cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
285 if (!assign_vector_locked(irqd, vector_searchmask))
286 return 0;
287
288 if (node != NUMA_NO_NODE) {
289 /* Try the node mask */
290 if (!assign_vector_locked(irqd, cpumask_of_node(node)))
291 return 0;
292 }
293
294 /* Try the full online mask */
295 return assign_vector_locked(irqd, cpu_online_mask);
296}
297
298static int
299assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
300{
301 if (irqd_affinity_is_managed(irqd))
302 return reserve_managed_vector(irqd);
303 if (info->mask)
304 return assign_irq_vector(irqd, info->mask);
305 /*
306 * Make only a global reservation with no guarantee. A real vector
307 * is associated at activation time.
308 */
309 return reserve_irq_vector(irqd);
310}
311
312static int
313assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
314{
315 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
316 struct apic_chip_data *apicd = apic_chip_data(irqd);
317 int vector, cpu;
318
319 cpumask_and(vector_searchmask, dest, affmsk);
320
321 /* set_affinity might call here for nothing */
322 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
323 return 0;
324 vector = irq_matrix_alloc_managed(vector_matrix, vector_searchmask,
325 &cpu);
326 trace_vector_alloc_managed(irqd->irq, vector, vector);
327 if (vector < 0)
328 return vector;
329 apic_update_vector(irqd, vector, cpu);
330 apic_update_irq_cfg(irqd, vector, cpu);
331 return 0;
332}
333
334static void clear_irq_vector(struct irq_data *irqd)
335{
336 struct apic_chip_data *apicd = apic_chip_data(irqd);
337 bool managed = irqd_affinity_is_managed(irqd);
338 unsigned int vector = apicd->vector;
339
340 lockdep_assert_held(&vector_lock);
341
342 if (!vector)
343 return;
344
345 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
346 apicd->prev_cpu);
347
348 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_SHUTDOWN;
349 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
350 apicd->vector = 0;
351
352 /* Clean up move in progress */
353 vector = apicd->prev_vector;
354 if (!vector)
355 return;
356
357 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_SHUTDOWN;
358 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
359 apicd->prev_vector = 0;
360 apicd->move_in_progress = 0;
361 hlist_del_init(&apicd->clist);
362}
363
364static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
365{
366 struct apic_chip_data *apicd = apic_chip_data(irqd);
367 unsigned long flags;
368
369 trace_vector_deactivate(irqd->irq, apicd->is_managed,
370 apicd->can_reserve, false);
371
372 /* Regular fixed assigned interrupt */
373 if (!apicd->is_managed && !apicd->can_reserve)
374 return;
375 /* If the interrupt has a global reservation, nothing to do */
376 if (apicd->has_reserved)
377 return;
378
379 raw_spin_lock_irqsave(&vector_lock, flags);
380 clear_irq_vector(irqd);
381 if (apicd->can_reserve)
382 reserve_irq_vector_locked(irqd);
383 else
384 vector_assign_managed_shutdown(irqd);
385 raw_spin_unlock_irqrestore(&vector_lock, flags);
386}
387
388static int activate_reserved(struct irq_data *irqd)
389{
390 struct apic_chip_data *apicd = apic_chip_data(irqd);
391 int ret;
392
393 ret = assign_irq_vector_any_locked(irqd);
394 if (!ret) {
395 apicd->has_reserved = false;
396 /*
397 * Core might have disabled reservation mode after
398 * allocating the irq descriptor. Ideally this should
399 * happen before allocation time, but that would require
400 * completely convoluted ways of transporting that
401 * information.
402 */
403 if (!irqd_can_reserve(irqd))
404 apicd->can_reserve = false;
405 }
406
407 /*
408 * Check to ensure that the effective affinity mask is a subset
409 * the user supplied affinity mask, and warn the user if it is not
410 */
411 if (!cpumask_subset(irq_data_get_effective_affinity_mask(irqd),
412 irq_data_get_affinity_mask(irqd))) {
413 pr_warn("irq %u: Affinity broken due to vector space exhaustion.\n",
414 irqd->irq);
415 }
416
417 return ret;
418}
419
420static int activate_managed(struct irq_data *irqd)
421{
422 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
423 int ret;
424
425 cpumask_and(vector_searchmask, dest, cpu_online_mask);
426 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
427 /* Something in the core code broke! Survive gracefully */
428 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
429 return -EINVAL;
430 }
431
432 ret = assign_managed_vector(irqd, vector_searchmask);
433 /*
434 * This should not happen. The vector reservation got buggered. Handle
435 * it gracefully.
436 */
437 if (WARN_ON_ONCE(ret < 0)) {
438 pr_err("Managed startup irq %u, no vector available\n",
439 irqd->irq);
440 }
441 return ret;
442}
443
444static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
445 bool reserve)
446{
447 struct apic_chip_data *apicd = apic_chip_data(irqd);
448 unsigned long flags;
449 int ret = 0;
450
451 trace_vector_activate(irqd->irq, apicd->is_managed,
452 apicd->can_reserve, reserve);
453
454 raw_spin_lock_irqsave(&vector_lock, flags);
455 if (!apicd->can_reserve && !apicd->is_managed)
456 assign_irq_vector_any_locked(irqd);
457 else if (reserve || irqd_is_managed_and_shutdown(irqd))
458 vector_assign_managed_shutdown(irqd);
459 else if (apicd->is_managed)
460 ret = activate_managed(irqd);
461 else if (apicd->has_reserved)
462 ret = activate_reserved(irqd);
463 raw_spin_unlock_irqrestore(&vector_lock, flags);
464 return ret;
465}
466
467static void vector_free_reserved_and_managed(struct irq_data *irqd)
468{
469 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
470 struct apic_chip_data *apicd = apic_chip_data(irqd);
471
472 trace_vector_teardown(irqd->irq, apicd->is_managed,
473 apicd->has_reserved);
474
475 if (apicd->has_reserved)
476 irq_matrix_remove_reserved(vector_matrix);
477 if (apicd->is_managed)
478 irq_matrix_remove_managed(vector_matrix, dest);
479}
480
481static void x86_vector_free_irqs(struct irq_domain *domain,
482 unsigned int virq, unsigned int nr_irqs)
483{
484 struct apic_chip_data *apicd;
485 struct irq_data *irqd;
486 unsigned long flags;
487 int i;
488
489 for (i = 0; i < nr_irqs; i++) {
490 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
491 if (irqd && irqd->chip_data) {
492 raw_spin_lock_irqsave(&vector_lock, flags);
493 clear_irq_vector(irqd);
494 vector_free_reserved_and_managed(irqd);
495 apicd = irqd->chip_data;
496 irq_domain_reset_irq_data(irqd);
497 raw_spin_unlock_irqrestore(&vector_lock, flags);
498 free_apic_chip_data(apicd);
499 }
500 }
501}
502
503static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
504 struct apic_chip_data *apicd)
505{
506 unsigned long flags;
507 bool realloc = false;
508
509 apicd->vector = ISA_IRQ_VECTOR(virq);
510 apicd->cpu = 0;
511
512 raw_spin_lock_irqsave(&vector_lock, flags);
513 /*
514 * If the interrupt is activated, then it must stay at this vector
515 * position. That's usually the timer interrupt (0).
516 */
517 if (irqd_is_activated(irqd)) {
518 trace_vector_setup(virq, true, 0);
519 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
520 } else {
521 /* Release the vector */
522 apicd->can_reserve = true;
523 irqd_set_can_reserve(irqd);
524 clear_irq_vector(irqd);
525 realloc = true;
526 }
527 raw_spin_unlock_irqrestore(&vector_lock, flags);
528 return realloc;
529}
530
531static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
532 unsigned int nr_irqs, void *arg)
533{
534 struct irq_alloc_info *info = arg;
535 struct apic_chip_data *apicd;
536 struct irq_data *irqd;
537 int i, err, node;
538
539 if (disable_apic)
540 return -ENXIO;
541
542 /*
543 * Catch any attempt to touch the cascade interrupt on a PIC
544 * equipped system.
545 */
546 if (WARN_ON_ONCE(info->flags & X86_IRQ_ALLOC_LEGACY &&
547 virq == PIC_CASCADE_IR))
548 return -EINVAL;
549
550 for (i = 0; i < nr_irqs; i++) {
551 irqd = irq_domain_get_irq_data(domain, virq + i);
552 BUG_ON(!irqd);
553 node = irq_data_get_node(irqd);
554 WARN_ON_ONCE(irqd->chip_data);
555 apicd = alloc_apic_chip_data(node);
556 if (!apicd) {
557 err = -ENOMEM;
558 goto error;
559 }
560
561 apicd->irq = virq + i;
562 irqd->chip = &lapic_controller;
563 irqd->chip_data = apicd;
564 irqd->hwirq = virq + i;
565 irqd_set_single_target(irqd);
566 /*
567 * Prevent that any of these interrupts is invoked in
568 * non interrupt context via e.g. generic_handle_irq()
569 * as that can corrupt the affinity move state.
570 */
571 irqd_set_handle_enforce_irqctx(irqd);
572
573 /* Don't invoke affinity setter on deactivated interrupts */
574 irqd_set_affinity_on_activate(irqd);
575
576 /*
577 * Legacy vectors are already assigned when the IOAPIC
578 * takes them over. They stay on the same vector. This is
579 * required for check_timer() to work correctly as it might
580 * switch back to legacy mode. Only update the hardware
581 * config.
582 */
583 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
584 if (!vector_configure_legacy(virq + i, irqd, apicd))
585 continue;
586 }
587
588 err = assign_irq_vector_policy(irqd, info);
589 trace_vector_setup(virq + i, false, err);
590 if (err) {
591 irqd->chip_data = NULL;
592 free_apic_chip_data(apicd);
593 goto error;
594 }
595 }
596
597 return 0;
598
599error:
600 x86_vector_free_irqs(domain, virq, i);
601 return err;
602}
603
604#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
605static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
606 struct irq_data *irqd, int ind)
607{
608 struct apic_chip_data apicd;
609 unsigned long flags;
610 int irq;
611
612 if (!irqd) {
613 irq_matrix_debug_show(m, vector_matrix, ind);
614 return;
615 }
616
617 irq = irqd->irq;
618 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
619 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
620 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
621 return;
622 }
623
624 if (!irqd->chip_data) {
625 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
626 return;
627 }
628
629 raw_spin_lock_irqsave(&vector_lock, flags);
630 memcpy(&apicd, irqd->chip_data, sizeof(apicd));
631 raw_spin_unlock_irqrestore(&vector_lock, flags);
632
633 seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector);
634 seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu);
635 if (apicd.prev_vector) {
636 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector);
637 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu);
638 }
639 seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0);
640 seq_printf(m, "%*sis_managed: %u\n", ind, "", apicd.is_managed ? 1 : 0);
641 seq_printf(m, "%*scan_reserve: %u\n", ind, "", apicd.can_reserve ? 1 : 0);
642 seq_printf(m, "%*shas_reserved: %u\n", ind, "", apicd.has_reserved ? 1 : 0);
643 seq_printf(m, "%*scleanup_pending: %u\n", ind, "", !hlist_unhashed(&apicd.clist));
644}
645#endif
646
647int x86_fwspec_is_ioapic(struct irq_fwspec *fwspec)
648{
649 if (fwspec->param_count != 1)
650 return 0;
651
652 if (is_fwnode_irqchip(fwspec->fwnode)) {
653 const char *fwname = fwnode_get_name(fwspec->fwnode);
654 return fwname && !strncmp(fwname, "IO-APIC-", 8) &&
655 simple_strtol(fwname+8, NULL, 10) == fwspec->param[0];
656 }
657 return to_of_node(fwspec->fwnode) &&
658 of_device_is_compatible(to_of_node(fwspec->fwnode),
659 "intel,ce4100-ioapic");
660}
661
662int x86_fwspec_is_hpet(struct irq_fwspec *fwspec)
663{
664 if (fwspec->param_count != 1)
665 return 0;
666
667 if (is_fwnode_irqchip(fwspec->fwnode)) {
668 const char *fwname = fwnode_get_name(fwspec->fwnode);
669 return fwname && !strncmp(fwname, "HPET-MSI-", 9) &&
670 simple_strtol(fwname+9, NULL, 10) == fwspec->param[0];
671 }
672 return 0;
673}
674
675static int x86_vector_select(struct irq_domain *d, struct irq_fwspec *fwspec,
676 enum irq_domain_bus_token bus_token)
677{
678 /*
679 * HPET and I/OAPIC cannot be parented in the vector domain
680 * if IRQ remapping is enabled. APIC IDs above 15 bits are
681 * only permitted if IRQ remapping is enabled, so check that.
682 */
683 if (apic->apic_id_valid(32768))
684 return 0;
685
686 return x86_fwspec_is_ioapic(fwspec) || x86_fwspec_is_hpet(fwspec);
687}
688
689static const struct irq_domain_ops x86_vector_domain_ops = {
690 .select = x86_vector_select,
691 .alloc = x86_vector_alloc_irqs,
692 .free = x86_vector_free_irqs,
693 .activate = x86_vector_activate,
694 .deactivate = x86_vector_deactivate,
695#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
696 .debug_show = x86_vector_debug_show,
697#endif
698};
699
700int __init arch_probe_nr_irqs(void)
701{
702 int nr;
703
704 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
705 nr_irqs = NR_VECTORS * nr_cpu_ids;
706
707 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
708#if defined(CONFIG_PCI_MSI)
709 /*
710 * for MSI and HT dyn irq
711 */
712 if (gsi_top <= NR_IRQS_LEGACY)
713 nr += 8 * nr_cpu_ids;
714 else
715 nr += gsi_top * 16;
716#endif
717 if (nr < nr_irqs)
718 nr_irqs = nr;
719
720 /*
721 * We don't know if PIC is present at this point so we need to do
722 * probe() to get the right number of legacy IRQs.
723 */
724 return legacy_pic->probe();
725}
726
727void lapic_assign_legacy_vector(unsigned int irq, bool replace)
728{
729 /*
730 * Use assign system here so it wont get accounted as allocated
731 * and moveable in the cpu hotplug check and it prevents managed
732 * irq reservation from touching it.
733 */
734 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
735}
736
737void __init lapic_update_legacy_vectors(void)
738{
739 unsigned int i;
740
741 if (IS_ENABLED(CONFIG_X86_IO_APIC) && nr_ioapics > 0)
742 return;
743
744 /*
745 * If the IO/APIC is disabled via config, kernel command line or
746 * lack of enumeration then all legacy interrupts are routed
747 * through the PIC. Make sure that they are marked as legacy
748 * vectors. PIC_CASCADE_IRQ has already been marked in
749 * lapic_assign_system_vectors().
750 */
751 for (i = 0; i < nr_legacy_irqs(); i++) {
752 if (i != PIC_CASCADE_IR)
753 lapic_assign_legacy_vector(i, true);
754 }
755}
756
757void __init lapic_assign_system_vectors(void)
758{
759 unsigned int i, vector;
760
761 for_each_set_bit(vector, system_vectors, NR_VECTORS)
762 irq_matrix_assign_system(vector_matrix, vector, false);
763
764 if (nr_legacy_irqs() > 1)
765 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
766
767 /* System vectors are reserved, online it */
768 irq_matrix_online(vector_matrix);
769
770 /* Mark the preallocated legacy interrupts */
771 for (i = 0; i < nr_legacy_irqs(); i++) {
772 /*
773 * Don't touch the cascade interrupt. It's unusable
774 * on PIC equipped machines. See the large comment
775 * in the IO/APIC code.
776 */
777 if (i != PIC_CASCADE_IR)
778 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
779 }
780}
781
782int __init arch_early_irq_init(void)
783{
784 struct fwnode_handle *fn;
785
786 fn = irq_domain_alloc_named_fwnode("VECTOR");
787 BUG_ON(!fn);
788 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
789 NULL);
790 BUG_ON(x86_vector_domain == NULL);
791 irq_set_default_host(x86_vector_domain);
792
793 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
794
795 /*
796 * Allocate the vector matrix allocator data structure and limit the
797 * search area.
798 */
799 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
800 FIRST_SYSTEM_VECTOR);
801 BUG_ON(!vector_matrix);
802
803 return arch_early_ioapic_init();
804}
805
806#ifdef CONFIG_SMP
807
808static struct irq_desc *__setup_vector_irq(int vector)
809{
810 int isairq = vector - ISA_IRQ_VECTOR(0);
811
812 /* Check whether the irq is in the legacy space */
813 if (isairq < 0 || isairq >= nr_legacy_irqs())
814 return VECTOR_UNUSED;
815 /* Check whether the irq is handled by the IOAPIC */
816 if (test_bit(isairq, &io_apic_irqs))
817 return VECTOR_UNUSED;
818 return irq_to_desc(isairq);
819}
820
821/* Online the local APIC infrastructure and initialize the vectors */
822void lapic_online(void)
823{
824 unsigned int vector;
825
826 lockdep_assert_held(&vector_lock);
827
828 /* Online the vector matrix array for this CPU */
829 irq_matrix_online(vector_matrix);
830
831 /*
832 * The interrupt affinity logic never targets interrupts to offline
833 * CPUs. The exception are the legacy PIC interrupts. In general
834 * they are only targeted to CPU0, but depending on the platform
835 * they can be distributed to any online CPU in hardware. The
836 * kernel has no influence on that. So all active legacy vectors
837 * must be installed on all CPUs. All non legacy interrupts can be
838 * cleared.
839 */
840 for (vector = 0; vector < NR_VECTORS; vector++)
841 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
842}
843
844void lapic_offline(void)
845{
846 lock_vector_lock();
847 irq_matrix_offline(vector_matrix);
848 unlock_vector_lock();
849}
850
851static int apic_set_affinity(struct irq_data *irqd,
852 const struct cpumask *dest, bool force)
853{
854 int err;
855
856 if (WARN_ON_ONCE(!irqd_is_activated(irqd)))
857 return -EIO;
858
859 raw_spin_lock(&vector_lock);
860 cpumask_and(vector_searchmask, dest, cpu_online_mask);
861 if (irqd_affinity_is_managed(irqd))
862 err = assign_managed_vector(irqd, vector_searchmask);
863 else
864 err = assign_vector_locked(irqd, vector_searchmask);
865 raw_spin_unlock(&vector_lock);
866 return err ? err : IRQ_SET_MASK_OK;
867}
868
869#else
870# define apic_set_affinity NULL
871#endif
872
873static int apic_retrigger_irq(struct irq_data *irqd)
874{
875 struct apic_chip_data *apicd = apic_chip_data(irqd);
876 unsigned long flags;
877
878 raw_spin_lock_irqsave(&vector_lock, flags);
879 apic->send_IPI(apicd->cpu, apicd->vector);
880 raw_spin_unlock_irqrestore(&vector_lock, flags);
881
882 return 1;
883}
884
885void apic_ack_irq(struct irq_data *irqd)
886{
887 irq_move_irq(irqd);
888 ack_APIC_irq();
889}
890
891void apic_ack_edge(struct irq_data *irqd)
892{
893 irq_complete_move(irqd_cfg(irqd));
894 apic_ack_irq(irqd);
895}
896
897static void x86_vector_msi_compose_msg(struct irq_data *data,
898 struct msi_msg *msg)
899{
900 __irq_msi_compose_msg(irqd_cfg(data), msg, false);
901}
902
903static struct irq_chip lapic_controller = {
904 .name = "APIC",
905 .irq_ack = apic_ack_edge,
906 .irq_set_affinity = apic_set_affinity,
907 .irq_compose_msi_msg = x86_vector_msi_compose_msg,
908 .irq_retrigger = apic_retrigger_irq,
909};
910
911#ifdef CONFIG_SMP
912
913static void free_moved_vector(struct apic_chip_data *apicd)
914{
915 unsigned int vector = apicd->prev_vector;
916 unsigned int cpu = apicd->prev_cpu;
917 bool managed = apicd->is_managed;
918
919 /*
920 * Managed interrupts are usually not migrated away
921 * from an online CPU, but CPU isolation 'managed_irq'
922 * can make that happen.
923 * 1) Activation does not take the isolation into account
924 * to keep the code simple
925 * 2) Migration away from an isolated CPU can happen when
926 * a non-isolated CPU which is in the calculated
927 * affinity mask comes online.
928 */
929 trace_vector_free_moved(apicd->irq, cpu, vector, managed);
930 irq_matrix_free(vector_matrix, cpu, vector, managed);
931 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
932 hlist_del_init(&apicd->clist);
933 apicd->prev_vector = 0;
934 apicd->move_in_progress = 0;
935}
936
937DEFINE_IDTENTRY_SYSVEC(sysvec_irq_move_cleanup)
938{
939 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
940 struct apic_chip_data *apicd;
941 struct hlist_node *tmp;
942
943 ack_APIC_irq();
944 /* Prevent vectors vanishing under us */
945 raw_spin_lock(&vector_lock);
946
947 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
948 unsigned int irr, vector = apicd->prev_vector;
949
950 /*
951 * Paranoia: Check if the vector that needs to be cleaned
952 * up is registered at the APICs IRR. If so, then this is
953 * not the best time to clean it up. Clean it up in the
954 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
955 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
956 * priority external vector, so on return from this
957 * interrupt the device interrupt will happen first.
958 */
959 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
960 if (irr & (1U << (vector % 32))) {
961 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
962 continue;
963 }
964 free_moved_vector(apicd);
965 }
966
967 raw_spin_unlock(&vector_lock);
968}
969
970static void __send_cleanup_vector(struct apic_chip_data *apicd)
971{
972 unsigned int cpu;
973
974 raw_spin_lock(&vector_lock);
975 apicd->move_in_progress = 0;
976 cpu = apicd->prev_cpu;
977 if (cpu_online(cpu)) {
978 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
979 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
980 } else {
981 apicd->prev_vector = 0;
982 }
983 raw_spin_unlock(&vector_lock);
984}
985
986void send_cleanup_vector(struct irq_cfg *cfg)
987{
988 struct apic_chip_data *apicd;
989
990 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
991 if (apicd->move_in_progress)
992 __send_cleanup_vector(apicd);
993}
994
995void irq_complete_move(struct irq_cfg *cfg)
996{
997 struct apic_chip_data *apicd;
998
999 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
1000 if (likely(!apicd->move_in_progress))
1001 return;
1002
1003 /*
1004 * If the interrupt arrived on the new target CPU, cleanup the
1005 * vector on the old target CPU. A vector check is not required
1006 * because an interrupt can never move from one vector to another
1007 * on the same CPU.
1008 */
1009 if (apicd->cpu == smp_processor_id())
1010 __send_cleanup_vector(apicd);
1011}
1012
1013/*
1014 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
1015 */
1016void irq_force_complete_move(struct irq_desc *desc)
1017{
1018 struct apic_chip_data *apicd;
1019 struct irq_data *irqd;
1020 unsigned int vector;
1021
1022 /*
1023 * The function is called for all descriptors regardless of which
1024 * irqdomain they belong to. For example if an IRQ is provided by
1025 * an irq_chip as part of a GPIO driver, the chip data for that
1026 * descriptor is specific to the irq_chip in question.
1027 *
1028 * Check first that the chip_data is what we expect
1029 * (apic_chip_data) before touching it any further.
1030 */
1031 irqd = irq_domain_get_irq_data(x86_vector_domain,
1032 irq_desc_get_irq(desc));
1033 if (!irqd)
1034 return;
1035
1036 raw_spin_lock(&vector_lock);
1037 apicd = apic_chip_data(irqd);
1038 if (!apicd)
1039 goto unlock;
1040
1041 /*
1042 * If prev_vector is empty, no action required.
1043 */
1044 vector = apicd->prev_vector;
1045 if (!vector)
1046 goto unlock;
1047
1048 /*
1049 * This is tricky. If the cleanup of the old vector has not been
1050 * done yet, then the following setaffinity call will fail with
1051 * -EBUSY. This can leave the interrupt in a stale state.
1052 *
1053 * All CPUs are stuck in stop machine with interrupts disabled so
1054 * calling __irq_complete_move() would be completely pointless.
1055 *
1056 * 1) The interrupt is in move_in_progress state. That means that we
1057 * have not seen an interrupt since the io_apic was reprogrammed to
1058 * the new vector.
1059 *
1060 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
1061 * have not been processed yet.
1062 */
1063 if (apicd->move_in_progress) {
1064 /*
1065 * In theory there is a race:
1066 *
1067 * set_ioapic(new_vector) <-- Interrupt is raised before update
1068 * is effective, i.e. it's raised on
1069 * the old vector.
1070 *
1071 * So if the target cpu cannot handle that interrupt before
1072 * the old vector is cleaned up, we get a spurious interrupt
1073 * and in the worst case the ioapic irq line becomes stale.
1074 *
1075 * But in case of cpu hotplug this should be a non issue
1076 * because if the affinity update happens right before all
1077 * cpus rendezvous in stop machine, there is no way that the
1078 * interrupt can be blocked on the target cpu because all cpus
1079 * loops first with interrupts enabled in stop machine, so the
1080 * old vector is not yet cleaned up when the interrupt fires.
1081 *
1082 * So the only way to run into this issue is if the delivery
1083 * of the interrupt on the apic/system bus would be delayed
1084 * beyond the point where the target cpu disables interrupts
1085 * in stop machine. I doubt that it can happen, but at least
1086 * there is a theoretical chance. Virtualization might be
1087 * able to expose this, but AFAICT the IOAPIC emulation is not
1088 * as stupid as the real hardware.
1089 *
1090 * Anyway, there is nothing we can do about that at this point
1091 * w/o refactoring the whole fixup_irq() business completely.
1092 * We print at least the irq number and the old vector number,
1093 * so we have the necessary information when a problem in that
1094 * area arises.
1095 */
1096 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
1097 irqd->irq, vector);
1098 }
1099 free_moved_vector(apicd);
1100unlock:
1101 raw_spin_unlock(&vector_lock);
1102}
1103
1104#ifdef CONFIG_HOTPLUG_CPU
1105/*
1106 * Note, this is not accurate accounting, but at least good enough to
1107 * prevent that the actual interrupt move will run out of vectors.
1108 */
1109int lapic_can_unplug_cpu(void)
1110{
1111 unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
1112 int ret = 0;
1113
1114 raw_spin_lock(&vector_lock);
1115 tomove = irq_matrix_allocated(vector_matrix);
1116 avl = irq_matrix_available(vector_matrix, true);
1117 if (avl < tomove) {
1118 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1119 cpu, tomove, avl);
1120 ret = -ENOSPC;
1121 goto out;
1122 }
1123 rsvd = irq_matrix_reserved(vector_matrix);
1124 if (avl < rsvd) {
1125 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1126 rsvd, avl);
1127 }
1128out:
1129 raw_spin_unlock(&vector_lock);
1130 return ret;
1131}
1132#endif /* HOTPLUG_CPU */
1133#endif /* SMP */
1134
1135static void __init print_APIC_field(int base)
1136{
1137 int i;
1138
1139 printk(KERN_DEBUG);
1140
1141 for (i = 0; i < 8; i++)
1142 pr_cont("%08x", apic_read(base + i*0x10));
1143
1144 pr_cont("\n");
1145}
1146
1147static void __init print_local_APIC(void *dummy)
1148{
1149 unsigned int i, v, ver, maxlvt;
1150 u64 icr;
1151
1152 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1153 smp_processor_id(), hard_smp_processor_id());
1154 v = apic_read(APIC_ID);
1155 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
1156 v = apic_read(APIC_LVR);
1157 pr_info("... APIC VERSION: %08x\n", v);
1158 ver = GET_APIC_VERSION(v);
1159 maxlvt = lapic_get_maxlvt();
1160
1161 v = apic_read(APIC_TASKPRI);
1162 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1163
1164 /* !82489DX */
1165 if (APIC_INTEGRATED(ver)) {
1166 if (!APIC_XAPIC(ver)) {
1167 v = apic_read(APIC_ARBPRI);
1168 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1169 v, v & APIC_ARBPRI_MASK);
1170 }
1171 v = apic_read(APIC_PROCPRI);
1172 pr_debug("... APIC PROCPRI: %08x\n", v);
1173 }
1174
1175 /*
1176 * Remote read supported only in the 82489DX and local APIC for
1177 * Pentium processors.
1178 */
1179 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1180 v = apic_read(APIC_RRR);
1181 pr_debug("... APIC RRR: %08x\n", v);
1182 }
1183
1184 v = apic_read(APIC_LDR);
1185 pr_debug("... APIC LDR: %08x\n", v);
1186 if (!x2apic_enabled()) {
1187 v = apic_read(APIC_DFR);
1188 pr_debug("... APIC DFR: %08x\n", v);
1189 }
1190 v = apic_read(APIC_SPIV);
1191 pr_debug("... APIC SPIV: %08x\n", v);
1192
1193 pr_debug("... APIC ISR field:\n");
1194 print_APIC_field(APIC_ISR);
1195 pr_debug("... APIC TMR field:\n");
1196 print_APIC_field(APIC_TMR);
1197 pr_debug("... APIC IRR field:\n");
1198 print_APIC_field(APIC_IRR);
1199
1200 /* !82489DX */
1201 if (APIC_INTEGRATED(ver)) {
1202 /* Due to the Pentium erratum 3AP. */
1203 if (maxlvt > 3)
1204 apic_write(APIC_ESR, 0);
1205
1206 v = apic_read(APIC_ESR);
1207 pr_debug("... APIC ESR: %08x\n", v);
1208 }
1209
1210 icr = apic_icr_read();
1211 pr_debug("... APIC ICR: %08x\n", (u32)icr);
1212 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1213
1214 v = apic_read(APIC_LVTT);
1215 pr_debug("... APIC LVTT: %08x\n", v);
1216
1217 if (maxlvt > 3) {
1218 /* PC is LVT#4. */
1219 v = apic_read(APIC_LVTPC);
1220 pr_debug("... APIC LVTPC: %08x\n", v);
1221 }
1222 v = apic_read(APIC_LVT0);
1223 pr_debug("... APIC LVT0: %08x\n", v);
1224 v = apic_read(APIC_LVT1);
1225 pr_debug("... APIC LVT1: %08x\n", v);
1226
1227 if (maxlvt > 2) {
1228 /* ERR is LVT#3. */
1229 v = apic_read(APIC_LVTERR);
1230 pr_debug("... APIC LVTERR: %08x\n", v);
1231 }
1232
1233 v = apic_read(APIC_TMICT);
1234 pr_debug("... APIC TMICT: %08x\n", v);
1235 v = apic_read(APIC_TMCCT);
1236 pr_debug("... APIC TMCCT: %08x\n", v);
1237 v = apic_read(APIC_TDCR);
1238 pr_debug("... APIC TDCR: %08x\n", v);
1239
1240 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1241 v = apic_read(APIC_EFEAT);
1242 maxlvt = (v >> 16) & 0xff;
1243 pr_debug("... APIC EFEAT: %08x\n", v);
1244 v = apic_read(APIC_ECTRL);
1245 pr_debug("... APIC ECTRL: %08x\n", v);
1246 for (i = 0; i < maxlvt; i++) {
1247 v = apic_read(APIC_EILVTn(i));
1248 pr_debug("... APIC EILVT%d: %08x\n", i, v);
1249 }
1250 }
1251 pr_cont("\n");
1252}
1253
1254static void __init print_local_APICs(int maxcpu)
1255{
1256 int cpu;
1257
1258 if (!maxcpu)
1259 return;
1260
1261 preempt_disable();
1262 for_each_online_cpu(cpu) {
1263 if (cpu >= maxcpu)
1264 break;
1265 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1266 }
1267 preempt_enable();
1268}
1269
1270static void __init print_PIC(void)
1271{
1272 unsigned int v;
1273 unsigned long flags;
1274
1275 if (!nr_legacy_irqs())
1276 return;
1277
1278 pr_debug("\nprinting PIC contents\n");
1279
1280 raw_spin_lock_irqsave(&i8259A_lock, flags);
1281
1282 v = inb(0xa1) << 8 | inb(0x21);
1283 pr_debug("... PIC IMR: %04x\n", v);
1284
1285 v = inb(0xa0) << 8 | inb(0x20);
1286 pr_debug("... PIC IRR: %04x\n", v);
1287
1288 outb(0x0b, 0xa0);
1289 outb(0x0b, 0x20);
1290 v = inb(0xa0) << 8 | inb(0x20);
1291 outb(0x0a, 0xa0);
1292 outb(0x0a, 0x20);
1293
1294 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1295
1296 pr_debug("... PIC ISR: %04x\n", v);
1297
1298 v = inb(PIC_ELCR2) << 8 | inb(PIC_ELCR1);
1299 pr_debug("... PIC ELCR: %04x\n", v);
1300}
1301
1302static int show_lapic __initdata = 1;
1303static __init int setup_show_lapic(char *arg)
1304{
1305 int num = -1;
1306
1307 if (strcmp(arg, "all") == 0) {
1308 show_lapic = CONFIG_NR_CPUS;
1309 } else {
1310 get_option(&arg, &num);
1311 if (num >= 0)
1312 show_lapic = num;
1313 }
1314
1315 return 1;
1316}
1317__setup("show_lapic=", setup_show_lapic);
1318
1319static int __init print_ICs(void)
1320{
1321 if (apic_verbosity == APIC_QUIET)
1322 return 0;
1323
1324 print_PIC();
1325
1326 /* don't print out if apic is not there */
1327 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1328 return 0;
1329
1330 print_local_APICs(show_lapic);
1331 print_IO_APICs();
1332
1333 return 0;
1334}
1335
1336late_initcall(print_ICs);