Loading...
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale MPC85xx/MPC86xx RapidIO support
4 *
5 * Copyright 2009 Sysgo AG
6 * Thomas Moll <thomas.moll@sysgo.com>
7 * - fixed maintenance access routines, check for aligned access
8 *
9 * Copyright 2009 Integrated Device Technology, Inc.
10 * Alex Bounine <alexandre.bounine@idt.com>
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
13 *
14 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
15 * Zhang Wei <wei.zhang@freescale.com>
16 *
17 * Copyright 2005 MontaVista Software, Inc.
18 * Matt Porter <mporter@kernel.crashing.org>
19 */
20
21#include <linux/init.h>
22#include <linux/extable.h>
23#include <linux/types.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/device.h>
27#include <linux/of_address.h>
28#include <linux/of_irq.h>
29#include <linux/of_platform.h>
30#include <linux/delay.h>
31#include <linux/slab.h>
32
33#include <linux/io.h>
34#include <linux/uaccess.h>
35#include <asm/machdep.h>
36
37#include "fsl_rio.h"
38
39#undef DEBUG_PW /* Port-Write debugging */
40
41#define RIO_PORT1_EDCSR 0x0640
42#define RIO_PORT2_EDCSR 0x0680
43#define RIO_PORT1_IECSR 0x10130
44#define RIO_PORT2_IECSR 0x101B0
45
46#define RIO_GCCSR 0x13c
47#define RIO_ESCSR 0x158
48#define ESCSR_CLEAR 0x07120204
49#define RIO_PORT2_ESCSR 0x178
50#define RIO_CCSR 0x15c
51#define RIO_LTLEDCSR_IER 0x80000000
52#define RIO_LTLEDCSR_PRT 0x01000000
53#define IECSR_CLEAR 0x80000000
54#define RIO_ISR_AACR 0x10120
55#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
56
57#define RIWTAR_TRAD_VAL_SHIFT 12
58#define RIWTAR_TRAD_MASK 0x00FFFFFF
59#define RIWBAR_BADD_VAL_SHIFT 12
60#define RIWBAR_BADD_MASK 0x003FFFFF
61#define RIWAR_ENABLE 0x80000000
62#define RIWAR_TGINT_LOCAL 0x00F00000
63#define RIWAR_RDTYP_NO_SNOOP 0x00040000
64#define RIWAR_RDTYP_SNOOP 0x00050000
65#define RIWAR_WRTYP_NO_SNOOP 0x00004000
66#define RIWAR_WRTYP_SNOOP 0x00005000
67#define RIWAR_WRTYP_ALLOC 0x00006000
68#define RIWAR_SIZE_MASK 0x0000003F
69
70static DEFINE_SPINLOCK(fsl_rio_config_lock);
71
72#define ___fsl_read_rio_config(x, addr, err, op, barrier) \
73 __asm__ __volatile__( \
74 "1: "op" %1,0(%2)\n" \
75 " "barrier"\n" \
76 "2:\n" \
77 ".section .fixup,\"ax\"\n" \
78 "3: li %1,-1\n" \
79 " li %0,%3\n" \
80 " b 2b\n" \
81 ".previous\n" \
82 EX_TABLE(1b, 3b) \
83 : "=r" (err), "=r" (x) \
84 : "b" (addr), "i" (-EFAULT), "0" (err))
85
86#ifdef CONFIG_BOOKE
87#define __fsl_read_rio_config(x, addr, err, op) \
88 ___fsl_read_rio_config(x, addr, err, op, "mbar")
89#else
90#define __fsl_read_rio_config(x, addr, err, op) \
91 ___fsl_read_rio_config(x, addr, err, op, "eieio")
92#endif
93
94void __iomem *rio_regs_win;
95void __iomem *rmu_regs_win;
96resource_size_t rio_law_start;
97
98struct fsl_rio_dbell *dbell;
99struct fsl_rio_pw *pw;
100
101#ifdef CONFIG_PPC_E500
102int fsl_rio_mcheck_exception(struct pt_regs *regs)
103{
104 const struct exception_table_entry *entry;
105 unsigned long reason;
106
107 if (!rio_regs_win)
108 return 0;
109
110 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
111 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
112 /* Check if we are prepared to handle this fault */
113 entry = search_exception_tables(regs->nip);
114 if (entry) {
115 pr_debug("RIO: %s - MC Exception handled\n",
116 __func__);
117 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
118 0);
119 regs_set_recoverable(regs);
120 regs_set_return_ip(regs, extable_fixup(entry));
121 return 1;
122 }
123 }
124
125 return 0;
126}
127EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
128#endif
129
130/**
131 * fsl_local_config_read - Generate a MPC85xx local config space read
132 * @mport: RapidIO master port info
133 * @index: ID of RapdiIO interface
134 * @offset: Offset into configuration space
135 * @len: Length (in bytes) of the maintenance transaction
136 * @data: Value to be read into
137 *
138 * Generates a MPC85xx local configuration space read. Returns %0 on
139 * success or %-EINVAL on failure.
140 */
141static int fsl_local_config_read(struct rio_mport *mport,
142 int index, u32 offset, int len, u32 *data)
143{
144 struct rio_priv *priv = mport->priv;
145 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
146 offset);
147 *data = in_be32(priv->regs_win + offset);
148
149 return 0;
150}
151
152/**
153 * fsl_local_config_write - Generate a MPC85xx local config space write
154 * @mport: RapidIO master port info
155 * @index: ID of RapdiIO interface
156 * @offset: Offset into configuration space
157 * @len: Length (in bytes) of the maintenance transaction
158 * @data: Value to be written
159 *
160 * Generates a MPC85xx local configuration space write. Returns %0 on
161 * success or %-EINVAL on failure.
162 */
163static int fsl_local_config_write(struct rio_mport *mport,
164 int index, u32 offset, int len, u32 data)
165{
166 struct rio_priv *priv = mport->priv;
167 pr_debug
168 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
169 index, offset, data);
170 out_be32(priv->regs_win + offset, data);
171
172 return 0;
173}
174
175/**
176 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
177 * @mport: RapidIO master port info
178 * @index: ID of RapdiIO interface
179 * @destid: Destination ID of transaction
180 * @hopcount: Number of hops to target device
181 * @offset: Offset into configuration space
182 * @len: Length (in bytes) of the maintenance transaction
183 * @val: Location to be read into
184 *
185 * Generates a MPC85xx read maintenance transaction. Returns %0 on
186 * success or %-EINVAL on failure.
187 */
188static int
189fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
190 u8 hopcount, u32 offset, int len, u32 *val)
191{
192 struct rio_priv *priv = mport->priv;
193 unsigned long flags;
194 u8 *data;
195 u32 rval, err = 0;
196
197 pr_debug
198 ("fsl_rio_config_read:"
199 " index %d destid %d hopcount %d offset %8.8x len %d\n",
200 index, destid, hopcount, offset, len);
201
202 /* 16MB maintenance window possible */
203 /* allow only aligned access to maintenance registers */
204 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
205 return -EINVAL;
206
207 spin_lock_irqsave(&fsl_rio_config_lock, flags);
208
209 out_be32(&priv->maint_atmu_regs->rowtar,
210 (destid << 22) | (hopcount << 12) | (offset >> 12));
211 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
212
213 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
214 switch (len) {
215 case 1:
216 __fsl_read_rio_config(rval, data, err, "lbz");
217 break;
218 case 2:
219 __fsl_read_rio_config(rval, data, err, "lhz");
220 break;
221 case 4:
222 __fsl_read_rio_config(rval, data, err, "lwz");
223 break;
224 default:
225 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
226 return -EINVAL;
227 }
228
229 if (err) {
230 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
231 err, destid, hopcount, offset);
232 }
233
234 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
235 *val = rval;
236
237 return err;
238}
239
240/**
241 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
242 * @mport: RapidIO master port info
243 * @index: ID of RapdiIO interface
244 * @destid: Destination ID of transaction
245 * @hopcount: Number of hops to target device
246 * @offset: Offset into configuration space
247 * @len: Length (in bytes) of the maintenance transaction
248 * @val: Value to be written
249 *
250 * Generates an MPC85xx write maintenance transaction. Returns %0 on
251 * success or %-EINVAL on failure.
252 */
253static int
254fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
255 u8 hopcount, u32 offset, int len, u32 val)
256{
257 struct rio_priv *priv = mport->priv;
258 unsigned long flags;
259 u8 *data;
260 int ret = 0;
261
262 pr_debug
263 ("fsl_rio_config_write:"
264 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
265 index, destid, hopcount, offset, len, val);
266
267 /* 16MB maintenance windows possible */
268 /* allow only aligned access to maintenance registers */
269 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
270 return -EINVAL;
271
272 spin_lock_irqsave(&fsl_rio_config_lock, flags);
273
274 out_be32(&priv->maint_atmu_regs->rowtar,
275 (destid << 22) | (hopcount << 12) | (offset >> 12));
276 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
277
278 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
279 switch (len) {
280 case 1:
281 out_8((u8 *) data, val);
282 break;
283 case 2:
284 out_be16((u16 *) data, val);
285 break;
286 case 4:
287 out_be32((u32 *) data, val);
288 break;
289 default:
290 ret = -EINVAL;
291 }
292 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
293
294 return ret;
295}
296
297static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
298{
299 int i;
300
301 /* close inbound windows */
302 for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
303 out_be32(&priv->inb_atmu_regs[i].riwar, 0);
304}
305
306int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
307 u64 rstart, u64 size, u32 flags)
308{
309 struct rio_priv *priv = mport->priv;
310 u32 base_size;
311 unsigned int base_size_log;
312 u64 win_start, win_end;
313 u32 riwar;
314 int i;
315
316 if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
317 return -EINVAL;
318
319 base_size_log = ilog2(size);
320 base_size = 1 << base_size_log;
321
322 /* check if addresses are aligned with the window size */
323 if (lstart & (base_size - 1))
324 return -EINVAL;
325 if (rstart & (base_size - 1))
326 return -EINVAL;
327
328 /* check for conflicting ranges */
329 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
330 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
331 if ((riwar & RIWAR_ENABLE) == 0)
332 continue;
333 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
334 << RIWBAR_BADD_VAL_SHIFT;
335 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
336 if (rstart < win_end && (rstart + size) > win_start)
337 return -EINVAL;
338 }
339
340 /* find unused atmu */
341 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
342 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
343 if ((riwar & RIWAR_ENABLE) == 0)
344 break;
345 }
346 if (i >= RIO_INB_ATMU_COUNT)
347 return -ENOMEM;
348
349 out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
350 out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
351 out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
352 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
353
354 return 0;
355}
356
357void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
358{
359 u32 win_start_shift, base_start_shift;
360 struct rio_priv *priv = mport->priv;
361 u32 riwar, riwtar;
362 int i;
363
364 /* skip default window */
365 base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
366 for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
367 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
368 if ((riwar & RIWAR_ENABLE) == 0)
369 continue;
370
371 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
372 win_start_shift = riwtar & RIWTAR_TRAD_MASK;
373 if (win_start_shift == base_start_shift) {
374 out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
375 return;
376 }
377 }
378}
379
380void fsl_rio_port_error_handler(int offset)
381{
382 /*XXX: Error recovery is not implemented, we just clear errors */
383 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
384
385 if (offset == 0) {
386 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
387 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
388 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
389 } else {
390 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
391 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
392 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
393 }
394}
395static inline void fsl_rio_info(struct device *dev, u32 ccsr)
396{
397 const char *str;
398 if (ccsr & 1) {
399 /* Serial phy */
400 switch (ccsr >> 30) {
401 case 0:
402 str = "1";
403 break;
404 case 1:
405 str = "4";
406 break;
407 default:
408 str = "Unknown";
409 break;
410 }
411 dev_info(dev, "Hardware port width: %s\n", str);
412
413 switch ((ccsr >> 27) & 7) {
414 case 0:
415 str = "Single-lane 0";
416 break;
417 case 1:
418 str = "Single-lane 2";
419 break;
420 case 2:
421 str = "Four-lane";
422 break;
423 default:
424 str = "Unknown";
425 break;
426 }
427 dev_info(dev, "Training connection status: %s\n", str);
428 } else {
429 /* Parallel phy */
430 if (!(ccsr & 0x80000000))
431 dev_info(dev, "Output port operating in 8-bit mode\n");
432 if (!(ccsr & 0x08000000))
433 dev_info(dev, "Input port operating in 8-bit mode\n");
434 }
435}
436
437/**
438 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
439 * @dev: platform_device pointer
440 *
441 * Initializes MPC85xx RapidIO hardware interface, configures
442 * master port with system-specific info, and registers the
443 * master port with the RapidIO subsystem.
444 */
445int fsl_rio_setup(struct platform_device *dev)
446{
447 struct rio_ops *ops;
448 struct rio_mport *port;
449 struct rio_priv *priv;
450 int rc = 0;
451 const u32 *dt_range, *cell, *port_index;
452 u32 active_ports = 0;
453 struct resource regs, rmu_regs;
454 struct device_node *np, *rmu_node;
455 int rlen;
456 u32 ccsr;
457 u64 range_start, range_size;
458 int paw, aw, sw;
459 u32 i;
460 static int tmp;
461 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
462
463 if (!dev->dev.of_node) {
464 dev_err(&dev->dev, "Device OF-Node is NULL");
465 return -ENODEV;
466 }
467
468 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
469 if (rc) {
470 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
471 dev->dev.of_node);
472 return -EFAULT;
473 }
474 dev_info(&dev->dev, "Of-device full name %pOF\n",
475 dev->dev.of_node);
476 dev_info(&dev->dev, "Regs: %pR\n", ®s);
477
478 rio_regs_win = ioremap(regs.start, resource_size(®s));
479 if (!rio_regs_win) {
480 dev_err(&dev->dev, "Unable to map rio register window\n");
481 rc = -ENOMEM;
482 goto err_rio_regs;
483 }
484
485 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
486 if (!ops) {
487 rc = -ENOMEM;
488 goto err_ops;
489 }
490 ops->lcread = fsl_local_config_read;
491 ops->lcwrite = fsl_local_config_write;
492 ops->cread = fsl_rio_config_read;
493 ops->cwrite = fsl_rio_config_write;
494 ops->dsend = fsl_rio_doorbell_send;
495 ops->pwenable = fsl_rio_pw_enable;
496 ops->open_outb_mbox = fsl_open_outb_mbox;
497 ops->open_inb_mbox = fsl_open_inb_mbox;
498 ops->close_outb_mbox = fsl_close_outb_mbox;
499 ops->close_inb_mbox = fsl_close_inb_mbox;
500 ops->add_outb_message = fsl_add_outb_message;
501 ops->add_inb_buffer = fsl_add_inb_buffer;
502 ops->get_inb_message = fsl_get_inb_message;
503 ops->map_inb = fsl_map_inb_mem;
504 ops->unmap_inb = fsl_unmap_inb_mem;
505
506 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
507 if (!rmu_node) {
508 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
509 rc = -ENOENT;
510 goto err_rmu;
511 }
512 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
513 if (rc) {
514 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
515 rmu_node);
516 of_node_put(rmu_node);
517 goto err_rmu;
518 }
519 of_node_put(rmu_node);
520 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
521 if (!rmu_regs_win) {
522 dev_err(&dev->dev, "Unable to map rmu register window\n");
523 rc = -ENOMEM;
524 goto err_rmu;
525 }
526 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
527 rmu_np[tmp] = np;
528 tmp++;
529 }
530
531 /*set up doobell node*/
532 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
533 if (!np) {
534 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
535 rc = -ENODEV;
536 goto err_dbell;
537 }
538 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
539 if (!(dbell)) {
540 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
541 rc = -ENOMEM;
542 goto err_dbell;
543 }
544 dbell->dev = &dev->dev;
545 dbell->bellirq = irq_of_parse_and_map(np, 1);
546 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
547
548 aw = of_n_addr_cells(np);
549 dt_range = of_get_property(np, "reg", &rlen);
550 if (!dt_range) {
551 pr_err("%pOF: unable to find 'reg' property\n",
552 np);
553 rc = -ENOMEM;
554 goto err_pw;
555 }
556 range_start = of_read_number(dt_range, aw);
557 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
558 (u32)range_start);
559
560 /*set up port write node*/
561 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
562 if (!np) {
563 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
564 rc = -ENODEV;
565 goto err_pw;
566 }
567 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
568 if (!(pw)) {
569 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
570 rc = -ENOMEM;
571 goto err_pw;
572 }
573 pw->dev = &dev->dev;
574 pw->pwirq = irq_of_parse_and_map(np, 0);
575 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
576 aw = of_n_addr_cells(np);
577 dt_range = of_get_property(np, "reg", &rlen);
578 if (!dt_range) {
579 pr_err("%pOF: unable to find 'reg' property\n",
580 np);
581 rc = -ENOMEM;
582 goto err;
583 }
584 range_start = of_read_number(dt_range, aw);
585 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
586
587 /*set up ports node*/
588 for_each_child_of_node(dev->dev.of_node, np) {
589 port_index = of_get_property(np, "cell-index", NULL);
590 if (!port_index) {
591 dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
592 np);
593 continue;
594 }
595
596 dt_range = of_get_property(np, "ranges", &rlen);
597 if (!dt_range) {
598 dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
599 np);
600 continue;
601 }
602
603 /* Get node address wide */
604 cell = of_get_property(np, "#address-cells", NULL);
605 if (cell)
606 aw = *cell;
607 else
608 aw = of_n_addr_cells(np);
609 /* Get node size wide */
610 cell = of_get_property(np, "#size-cells", NULL);
611 if (cell)
612 sw = *cell;
613 else
614 sw = of_n_size_cells(np);
615 /* Get parent address wide wide */
616 paw = of_n_addr_cells(np);
617 range_start = of_read_number(dt_range + aw, paw);
618 range_size = of_read_number(dt_range + aw + paw, sw);
619
620 dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n",
621 np, range_start, range_size);
622
623 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
624 if (!port)
625 continue;
626
627 rc = rio_mport_initialize(port);
628 if (rc) {
629 kfree(port);
630 continue;
631 }
632
633 i = *port_index - 1;
634 port->index = (unsigned char)i;
635
636 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
637 if (!priv) {
638 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
639 kfree(port);
640 continue;
641 }
642
643 INIT_LIST_HEAD(&port->dbells);
644 port->iores.start = range_start;
645 port->iores.end = port->iores.start + range_size - 1;
646 port->iores.flags = IORESOURCE_MEM;
647 port->iores.name = "rio_io_win";
648
649 if (request_resource(&iomem_resource, &port->iores) < 0) {
650 dev_err(&dev->dev, "RIO: Error requesting master port region"
651 " 0x%016llx-0x%016llx\n",
652 (u64)port->iores.start, (u64)port->iores.end);
653 kfree(priv);
654 kfree(port);
655 continue;
656 }
657 sprintf(port->name, "RIO mport %d", i);
658
659 priv->dev = &dev->dev;
660 port->dev.parent = &dev->dev;
661 port->ops = ops;
662 port->priv = priv;
663 port->phys_efptr = 0x100;
664 port->phys_rmap = 1;
665 priv->regs_win = rio_regs_win;
666
667 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
668
669 /* Checking the port training status */
670 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
671 dev_err(&dev->dev, "Port %d is not ready. "
672 "Try to restart connection...\n", i);
673 /* Disable ports */
674 out_be32(priv->regs_win
675 + RIO_CCSR + i*0x20, 0);
676 /* Set 1x lane */
677 setbits32(priv->regs_win
678 + RIO_CCSR + i*0x20, 0x02000000);
679 /* Enable ports */
680 setbits32(priv->regs_win
681 + RIO_CCSR + i*0x20, 0x00600000);
682 msleep(100);
683 if (in_be32((priv->regs_win
684 + RIO_ESCSR + i*0x20)) & 1) {
685 dev_err(&dev->dev,
686 "Port %d restart failed.\n", i);
687 release_resource(&port->iores);
688 kfree(priv);
689 kfree(port);
690 continue;
691 }
692 dev_info(&dev->dev, "Port %d restart success!\n", i);
693 }
694 fsl_rio_info(&dev->dev, ccsr);
695
696 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
697 & RIO_PEF_CTLS) >> 4;
698 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
699 port->sys_size ? 65536 : 256);
700
701 if (port->host_deviceid >= 0)
702 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
703 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
704 else
705 out_be32(priv->regs_win + RIO_GCCSR,
706 RIO_PORT_GEN_MASTER);
707
708 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
709 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
710 RIO_ATMU_REGS_PORT2_OFFSET));
711
712 priv->maint_atmu_regs = priv->atmu_regs + 1;
713 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
714 (priv->regs_win +
715 ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
716 RIO_INB_ATMU_REGS_PORT2_OFFSET));
717
718 /* Set to receive packets with any dest ID */
719 out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
720 RIO_ISR_AACR_AA);
721
722 /* Configure maintenance transaction window */
723 out_be32(&priv->maint_atmu_regs->rowbar,
724 port->iores.start >> 12);
725 out_be32(&priv->maint_atmu_regs->rowar,
726 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
727
728 priv->maint_win = ioremap(port->iores.start,
729 RIO_MAINT_WIN_SIZE);
730
731 rio_law_start = range_start;
732
733 fsl_rio_setup_rmu(port, rmu_np[i]);
734 fsl_rio_inbound_mem_init(priv);
735
736 dbell->mport[i] = port;
737 pw->mport[i] = port;
738
739 if (rio_register_mport(port)) {
740 release_resource(&port->iores);
741 kfree(priv);
742 kfree(port);
743 continue;
744 }
745 active_ports++;
746 }
747
748 if (!active_ports) {
749 rc = -ENOLINK;
750 goto err;
751 }
752
753 fsl_rio_doorbell_init(dbell);
754 fsl_rio_port_write_init(pw);
755
756 return 0;
757err:
758 kfree(pw);
759 pw = NULL;
760err_pw:
761 kfree(dbell);
762 dbell = NULL;
763err_dbell:
764 iounmap(rmu_regs_win);
765 rmu_regs_win = NULL;
766err_rmu:
767 kfree(ops);
768err_ops:
769 iounmap(rio_regs_win);
770 rio_regs_win = NULL;
771err_rio_regs:
772 return rc;
773}
774
775/* The probe function for RapidIO peer-to-peer network.
776 */
777static int fsl_of_rio_rpn_probe(struct platform_device *dev)
778{
779 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
780 dev->dev.of_node);
781
782 return fsl_rio_setup(dev);
783};
784
785static const struct of_device_id fsl_of_rio_rpn_ids[] = {
786 {
787 .compatible = "fsl,srio",
788 },
789 {},
790};
791
792static struct platform_driver fsl_of_rio_rpn_driver = {
793 .driver = {
794 .name = "fsl-of-rio",
795 .of_match_table = fsl_of_rio_rpn_ids,
796 },
797 .probe = fsl_of_rio_rpn_probe,
798};
799
800static __init int fsl_of_rio_rpn_init(void)
801{
802 return platform_driver_register(&fsl_of_rio_rpn_driver);
803}
804
805subsys_initcall(fsl_of_rio_rpn_init);
1/*
2 * Freescale MPC85xx/MPC86xx RapidIO support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 *
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/dma-mapping.h>
29#include <linux/interrupt.h>
30#include <linux/device.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_platform.h>
34#include <linux/delay.h>
35#include <linux/slab.h>
36
37#include <linux/io.h>
38#include <linux/uaccess.h>
39#include <asm/machdep.h>
40
41#include "fsl_rio.h"
42
43#undef DEBUG_PW /* Port-Write debugging */
44
45#define RIO_PORT1_EDCSR 0x0640
46#define RIO_PORT2_EDCSR 0x0680
47#define RIO_PORT1_IECSR 0x10130
48#define RIO_PORT2_IECSR 0x101B0
49
50#define RIO_GCCSR 0x13c
51#define RIO_ESCSR 0x158
52#define ESCSR_CLEAR 0x07120204
53#define RIO_PORT2_ESCSR 0x178
54#define RIO_CCSR 0x15c
55#define RIO_LTLEDCSR_IER 0x80000000
56#define RIO_LTLEDCSR_PRT 0x01000000
57#define IECSR_CLEAR 0x80000000
58#define RIO_ISR_AACR 0x10120
59#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
60
61#define __fsl_read_rio_config(x, addr, err, op) \
62 __asm__ __volatile__( \
63 "1: "op" %1,0(%2)\n" \
64 " eieio\n" \
65 "2:\n" \
66 ".section .fixup,\"ax\"\n" \
67 "3: li %1,-1\n" \
68 " li %0,%3\n" \
69 " b 2b\n" \
70 ".section __ex_table,\"a\"\n" \
71 PPC_LONG_ALIGN "\n" \
72 PPC_LONG "1b,3b\n" \
73 ".text" \
74 : "=r" (err), "=r" (x) \
75 : "b" (addr), "i" (-EFAULT), "0" (err))
76
77void __iomem *rio_regs_win;
78void __iomem *rmu_regs_win;
79resource_size_t rio_law_start;
80
81struct fsl_rio_dbell *dbell;
82struct fsl_rio_pw *pw;
83
84#ifdef CONFIG_E500
85int fsl_rio_mcheck_exception(struct pt_regs *regs)
86{
87 const struct exception_table_entry *entry;
88 unsigned long reason;
89
90 if (!rio_regs_win)
91 return 0;
92
93 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
94 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
95 /* Check if we are prepared to handle this fault */
96 entry = search_exception_tables(regs->nip);
97 if (entry) {
98 pr_debug("RIO: %s - MC Exception handled\n",
99 __func__);
100 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
101 0);
102 regs->msr |= MSR_RI;
103 regs->nip = entry->fixup;
104 return 1;
105 }
106 }
107
108 return 0;
109}
110EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
111#endif
112
113/**
114 * fsl_local_config_read - Generate a MPC85xx local config space read
115 * @mport: RapidIO master port info
116 * @index: ID of RapdiIO interface
117 * @offset: Offset into configuration space
118 * @len: Length (in bytes) of the maintenance transaction
119 * @data: Value to be read into
120 *
121 * Generates a MPC85xx local configuration space read. Returns %0 on
122 * success or %-EINVAL on failure.
123 */
124static int fsl_local_config_read(struct rio_mport *mport,
125 int index, u32 offset, int len, u32 *data)
126{
127 struct rio_priv *priv = mport->priv;
128 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
129 offset);
130 *data = in_be32(priv->regs_win + offset);
131
132 return 0;
133}
134
135/**
136 * fsl_local_config_write - Generate a MPC85xx local config space write
137 * @mport: RapidIO master port info
138 * @index: ID of RapdiIO interface
139 * @offset: Offset into configuration space
140 * @len: Length (in bytes) of the maintenance transaction
141 * @data: Value to be written
142 *
143 * Generates a MPC85xx local configuration space write. Returns %0 on
144 * success or %-EINVAL on failure.
145 */
146static int fsl_local_config_write(struct rio_mport *mport,
147 int index, u32 offset, int len, u32 data)
148{
149 struct rio_priv *priv = mport->priv;
150 pr_debug
151 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
152 index, offset, data);
153 out_be32(priv->regs_win + offset, data);
154
155 return 0;
156}
157
158/**
159 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
160 * @mport: RapidIO master port info
161 * @index: ID of RapdiIO interface
162 * @destid: Destination ID of transaction
163 * @hopcount: Number of hops to target device
164 * @offset: Offset into configuration space
165 * @len: Length (in bytes) of the maintenance transaction
166 * @val: Location to be read into
167 *
168 * Generates a MPC85xx read maintenance transaction. Returns %0 on
169 * success or %-EINVAL on failure.
170 */
171static int
172fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
173 u8 hopcount, u32 offset, int len, u32 *val)
174{
175 struct rio_priv *priv = mport->priv;
176 u8 *data;
177 u32 rval, err = 0;
178
179 pr_debug
180 ("fsl_rio_config_read:"
181 " index %d destid %d hopcount %d offset %8.8x len %d\n",
182 index, destid, hopcount, offset, len);
183
184 /* 16MB maintenance window possible */
185 /* allow only aligned access to maintenance registers */
186 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
187 return -EINVAL;
188
189 out_be32(&priv->maint_atmu_regs->rowtar,
190 (destid << 22) | (hopcount << 12) | (offset >> 12));
191 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
192
193 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
194 switch (len) {
195 case 1:
196 __fsl_read_rio_config(rval, data, err, "lbz");
197 break;
198 case 2:
199 __fsl_read_rio_config(rval, data, err, "lhz");
200 break;
201 case 4:
202 __fsl_read_rio_config(rval, data, err, "lwz");
203 break;
204 default:
205 return -EINVAL;
206 }
207
208 if (err) {
209 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
210 err, destid, hopcount, offset);
211 }
212
213 *val = rval;
214
215 return err;
216}
217
218/**
219 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
220 * @mport: RapidIO master port info
221 * @index: ID of RapdiIO interface
222 * @destid: Destination ID of transaction
223 * @hopcount: Number of hops to target device
224 * @offset: Offset into configuration space
225 * @len: Length (in bytes) of the maintenance transaction
226 * @val: Value to be written
227 *
228 * Generates an MPC85xx write maintenance transaction. Returns %0 on
229 * success or %-EINVAL on failure.
230 */
231static int
232fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
233 u8 hopcount, u32 offset, int len, u32 val)
234{
235 struct rio_priv *priv = mport->priv;
236 u8 *data;
237 pr_debug
238 ("fsl_rio_config_write:"
239 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
240 index, destid, hopcount, offset, len, val);
241
242 /* 16MB maintenance windows possible */
243 /* allow only aligned access to maintenance registers */
244 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
245 return -EINVAL;
246
247 out_be32(&priv->maint_atmu_regs->rowtar,
248 (destid << 22) | (hopcount << 12) | (offset >> 12));
249 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
250
251 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
252 switch (len) {
253 case 1:
254 out_8((u8 *) data, val);
255 break;
256 case 2:
257 out_be16((u16 *) data, val);
258 break;
259 case 4:
260 out_be32((u32 *) data, val);
261 break;
262 default:
263 return -EINVAL;
264 }
265
266 return 0;
267}
268
269void fsl_rio_port_error_handler(int offset)
270{
271 /*XXX: Error recovery is not implemented, we just clear errors */
272 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
273
274 if (offset == 0) {
275 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
276 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
277 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
278 } else {
279 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
280 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
281 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
282 }
283}
284static inline void fsl_rio_info(struct device *dev, u32 ccsr)
285{
286 const char *str;
287 if (ccsr & 1) {
288 /* Serial phy */
289 switch (ccsr >> 30) {
290 case 0:
291 str = "1";
292 break;
293 case 1:
294 str = "4";
295 break;
296 default:
297 str = "Unknown";
298 break;
299 }
300 dev_info(dev, "Hardware port width: %s\n", str);
301
302 switch ((ccsr >> 27) & 7) {
303 case 0:
304 str = "Single-lane 0";
305 break;
306 case 1:
307 str = "Single-lane 2";
308 break;
309 case 2:
310 str = "Four-lane";
311 break;
312 default:
313 str = "Unknown";
314 break;
315 }
316 dev_info(dev, "Training connection status: %s\n", str);
317 } else {
318 /* Parallel phy */
319 if (!(ccsr & 0x80000000))
320 dev_info(dev, "Output port operating in 8-bit mode\n");
321 if (!(ccsr & 0x08000000))
322 dev_info(dev, "Input port operating in 8-bit mode\n");
323 }
324}
325
326/**
327 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
328 * @dev: platform_device pointer
329 *
330 * Initializes MPC85xx RapidIO hardware interface, configures
331 * master port with system-specific info, and registers the
332 * master port with the RapidIO subsystem.
333 */
334int fsl_rio_setup(struct platform_device *dev)
335{
336 struct rio_ops *ops;
337 struct rio_mport *port;
338 struct rio_priv *priv;
339 int rc = 0;
340 const u32 *dt_range, *cell, *port_index;
341 u32 active_ports = 0;
342 struct resource regs, rmu_regs;
343 struct device_node *np, *rmu_node;
344 int rlen;
345 u32 ccsr;
346 u64 range_start, range_size;
347 int paw, aw, sw;
348 u32 i;
349 static int tmp;
350 struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
351
352 if (!dev->dev.of_node) {
353 dev_err(&dev->dev, "Device OF-Node is NULL");
354 return -ENODEV;
355 }
356
357 rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
358 if (rc) {
359 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
360 dev->dev.of_node->full_name);
361 return -EFAULT;
362 }
363 dev_info(&dev->dev, "Of-device full name %s\n",
364 dev->dev.of_node->full_name);
365 dev_info(&dev->dev, "Regs: %pR\n", ®s);
366
367 rio_regs_win = ioremap(regs.start, resource_size(®s));
368 if (!rio_regs_win) {
369 dev_err(&dev->dev, "Unable to map rio register window\n");
370 rc = -ENOMEM;
371 goto err_rio_regs;
372 }
373
374 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
375 if (!ops) {
376 rc = -ENOMEM;
377 goto err_ops;
378 }
379 ops->lcread = fsl_local_config_read;
380 ops->lcwrite = fsl_local_config_write;
381 ops->cread = fsl_rio_config_read;
382 ops->cwrite = fsl_rio_config_write;
383 ops->dsend = fsl_rio_doorbell_send;
384 ops->pwenable = fsl_rio_pw_enable;
385 ops->open_outb_mbox = fsl_open_outb_mbox;
386 ops->open_inb_mbox = fsl_open_inb_mbox;
387 ops->close_outb_mbox = fsl_close_outb_mbox;
388 ops->close_inb_mbox = fsl_close_inb_mbox;
389 ops->add_outb_message = fsl_add_outb_message;
390 ops->add_inb_buffer = fsl_add_inb_buffer;
391 ops->get_inb_message = fsl_get_inb_message;
392
393 rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
394 if (!rmu_node)
395 goto err_rmu;
396 rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
397 if (rc) {
398 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
399 rmu_node->full_name);
400 goto err_rmu;
401 }
402 rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
403 if (!rmu_regs_win) {
404 dev_err(&dev->dev, "Unable to map rmu register window\n");
405 rc = -ENOMEM;
406 goto err_rmu;
407 }
408 for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
409 rmu_np[tmp] = np;
410 tmp++;
411 }
412
413 /*set up doobell node*/
414 np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
415 if (!np) {
416 rc = -ENODEV;
417 goto err_dbell;
418 }
419 dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
420 if (!(dbell)) {
421 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
422 rc = -ENOMEM;
423 goto err_dbell;
424 }
425 dbell->dev = &dev->dev;
426 dbell->bellirq = irq_of_parse_and_map(np, 1);
427 dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
428
429 aw = of_n_addr_cells(np);
430 dt_range = of_get_property(np, "reg", &rlen);
431 if (!dt_range) {
432 pr_err("%s: unable to find 'reg' property\n",
433 np->full_name);
434 rc = -ENOMEM;
435 goto err_pw;
436 }
437 range_start = of_read_number(dt_range, aw);
438 dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
439 (u32)range_start);
440
441 /*set up port write node*/
442 np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
443 if (!np) {
444 rc = -ENODEV;
445 goto err_pw;
446 }
447 pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
448 if (!(pw)) {
449 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
450 rc = -ENOMEM;
451 goto err_pw;
452 }
453 pw->dev = &dev->dev;
454 pw->pwirq = irq_of_parse_and_map(np, 0);
455 dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
456 aw = of_n_addr_cells(np);
457 dt_range = of_get_property(np, "reg", &rlen);
458 if (!dt_range) {
459 pr_err("%s: unable to find 'reg' property\n",
460 np->full_name);
461 rc = -ENOMEM;
462 goto err;
463 }
464 range_start = of_read_number(dt_range, aw);
465 pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
466
467 /*set up ports node*/
468 for_each_child_of_node(dev->dev.of_node, np) {
469 port_index = of_get_property(np, "cell-index", NULL);
470 if (!port_index) {
471 dev_err(&dev->dev, "Can't get %s property 'cell-index'\n",
472 np->full_name);
473 continue;
474 }
475
476 dt_range = of_get_property(np, "ranges", &rlen);
477 if (!dt_range) {
478 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
479 np->full_name);
480 continue;
481 }
482
483 /* Get node address wide */
484 cell = of_get_property(np, "#address-cells", NULL);
485 if (cell)
486 aw = *cell;
487 else
488 aw = of_n_addr_cells(np);
489 /* Get node size wide */
490 cell = of_get_property(np, "#size-cells", NULL);
491 if (cell)
492 sw = *cell;
493 else
494 sw = of_n_size_cells(np);
495 /* Get parent address wide wide */
496 paw = of_n_addr_cells(np);
497 range_start = of_read_number(dt_range + aw, paw);
498 range_size = of_read_number(dt_range + aw + paw, sw);
499
500 dev_info(&dev->dev, "%s: LAW start 0x%016llx, size 0x%016llx.\n",
501 np->full_name, range_start, range_size);
502
503 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
504 if (!port)
505 continue;
506
507 i = *port_index - 1;
508 port->index = (unsigned char)i;
509
510 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
511 if (!priv) {
512 dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
513 kfree(port);
514 continue;
515 }
516
517 INIT_LIST_HEAD(&port->dbells);
518 port->iores.start = range_start;
519 port->iores.end = port->iores.start + range_size - 1;
520 port->iores.flags = IORESOURCE_MEM;
521 port->iores.name = "rio_io_win";
522
523 if (request_resource(&iomem_resource, &port->iores) < 0) {
524 dev_err(&dev->dev, "RIO: Error requesting master port region"
525 " 0x%016llx-0x%016llx\n",
526 (u64)port->iores.start, (u64)port->iores.end);
527 kfree(priv);
528 kfree(port);
529 continue;
530 }
531 sprintf(port->name, "RIO mport %d", i);
532
533 priv->dev = &dev->dev;
534 port->dev.parent = &dev->dev;
535 port->ops = ops;
536 port->priv = priv;
537 port->phys_efptr = 0x100;
538 priv->regs_win = rio_regs_win;
539
540 /* Probe the master port phy type */
541 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
542 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
543 if (port->phy_type == RIO_PHY_PARALLEL) {
544 dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported port type!\n");
545 release_resource(&port->iores);
546 kfree(priv);
547 kfree(port);
548 continue;
549 }
550 dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
551 /* Checking the port training status */
552 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
553 dev_err(&dev->dev, "Port %d is not ready. "
554 "Try to restart connection...\n", i);
555 /* Disable ports */
556 out_be32(priv->regs_win
557 + RIO_CCSR + i*0x20, 0);
558 /* Set 1x lane */
559 setbits32(priv->regs_win
560 + RIO_CCSR + i*0x20, 0x02000000);
561 /* Enable ports */
562 setbits32(priv->regs_win
563 + RIO_CCSR + i*0x20, 0x00600000);
564 msleep(100);
565 if (in_be32((priv->regs_win
566 + RIO_ESCSR + i*0x20)) & 1) {
567 dev_err(&dev->dev,
568 "Port %d restart failed.\n", i);
569 release_resource(&port->iores);
570 kfree(priv);
571 kfree(port);
572 continue;
573 }
574 dev_info(&dev->dev, "Port %d restart success!\n", i);
575 }
576 fsl_rio_info(&dev->dev, ccsr);
577
578 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
579 & RIO_PEF_CTLS) >> 4;
580 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
581 port->sys_size ? 65536 : 256);
582
583 if (rio_register_mport(port)) {
584 release_resource(&port->iores);
585 kfree(priv);
586 kfree(port);
587 continue;
588 }
589 if (port->host_deviceid >= 0)
590 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
591 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
592 else
593 out_be32(priv->regs_win + RIO_GCCSR,
594 RIO_PORT_GEN_MASTER);
595
596 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
597 + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
598 RIO_ATMU_REGS_PORT2_OFFSET));
599
600 priv->maint_atmu_regs = priv->atmu_regs + 1;
601
602 /* Set to receive any dist ID for serial RapidIO controller. */
603 if (port->phy_type == RIO_PHY_SERIAL)
604 out_be32((priv->regs_win
605 + RIO_ISR_AACR + i*0x80), RIO_ISR_AACR_AA);
606
607 /* Configure maintenance transaction window */
608 out_be32(&priv->maint_atmu_regs->rowbar,
609 port->iores.start >> 12);
610 out_be32(&priv->maint_atmu_regs->rowar,
611 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
612
613 priv->maint_win = ioremap(port->iores.start,
614 RIO_MAINT_WIN_SIZE);
615
616 rio_law_start = range_start;
617
618 fsl_rio_setup_rmu(port, rmu_np[i]);
619
620 dbell->mport[i] = port;
621
622 active_ports++;
623 }
624
625 if (!active_ports) {
626 rc = -ENOLINK;
627 goto err;
628 }
629
630 fsl_rio_doorbell_init(dbell);
631 fsl_rio_port_write_init(pw);
632
633 return 0;
634err:
635 kfree(pw);
636err_pw:
637 kfree(dbell);
638err_dbell:
639 iounmap(rmu_regs_win);
640err_rmu:
641 kfree(ops);
642err_ops:
643 iounmap(rio_regs_win);
644err_rio_regs:
645 return rc;
646}
647
648/* The probe function for RapidIO peer-to-peer network.
649 */
650static int fsl_of_rio_rpn_probe(struct platform_device *dev)
651{
652 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
653 dev->dev.of_node->full_name);
654
655 return fsl_rio_setup(dev);
656};
657
658static const struct of_device_id fsl_of_rio_rpn_ids[] = {
659 {
660 .compatible = "fsl,srio",
661 },
662 {},
663};
664
665static struct platform_driver fsl_of_rio_rpn_driver = {
666 .driver = {
667 .name = "fsl-of-rio",
668 .owner = THIS_MODULE,
669 .of_match_table = fsl_of_rio_rpn_ids,
670 },
671 .probe = fsl_of_rio_rpn_probe,
672};
673
674static __init int fsl_of_rio_rpn_init(void)
675{
676 return platform_driver_register(&fsl_of_rio_rpn_driver);
677}
678
679subsys_initcall(fsl_of_rio_rpn_init);