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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * linux/arch/m68k/mm/memory.c
4 *
5 * Copyright (C) 1995 Hamish Macdonald
6 */
7
8#include <linux/module.h>
9#include <linux/mm.h>
10#include <linux/kernel.h>
11#include <linux/string.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/pagemap.h>
15#include <linux/gfp.h>
16
17#include <asm/setup.h>
18#include <asm/page.h>
19#include <asm/traps.h>
20#include <asm/machdep.h>
21
22
23/* invalidate page in both caches */
24static inline void clear040(unsigned long paddr)
25{
26 asm volatile (
27 "nop\n\t"
28 ".chip 68040\n\t"
29 "cinvp %%bc,(%0)\n\t"
30 ".chip 68k"
31 : : "a" (paddr));
32}
33
34/* invalidate page in i-cache */
35static inline void cleari040(unsigned long paddr)
36{
37 asm volatile (
38 "nop\n\t"
39 ".chip 68040\n\t"
40 "cinvp %%ic,(%0)\n\t"
41 ".chip 68k"
42 : : "a" (paddr));
43}
44
45/* push page in both caches */
46/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
47static inline void push040(unsigned long paddr)
48{
49 asm volatile (
50 "nop\n\t"
51 ".chip 68040\n\t"
52 "cpushp %%bc,(%0)\n\t"
53 ".chip 68k"
54 : : "a" (paddr));
55}
56
57/* push and invalidate page in both caches, must disable ints
58 * to avoid invalidating valid data */
59static inline void pushcl040(unsigned long paddr)
60{
61 unsigned long flags;
62
63 local_irq_save(flags);
64 push040(paddr);
65 if (CPU_IS_060)
66 clear040(paddr);
67 local_irq_restore(flags);
68}
69
70/*
71 * 040: Hit every page containing an address in the range paddr..paddr+len-1.
72 * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
73 * Hit every page until there is a page or less to go. Hit the next page,
74 * and the one after that if the range hits it.
75 */
76/* ++roman: A little bit more care is required here: The CINVP instruction
77 * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
78 * and the end of the region must be treated differently if they are not
79 * exactly at the beginning or end of a page boundary. Else, maybe too much
80 * data becomes invalidated and thus lost forever. CPUSHP does what we need:
81 * it invalidates the page after pushing dirty data to memory. (Thanks to Jes
82 * for discovering the problem!)
83 */
84/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
85 * the DPI bit in the CACR; would it cause problems with temporarily changing
86 * this?). So we have to push first and then additionally to invalidate.
87 */
88
89
90/*
91 * cache_clear() semantics: Clear any cache entries for the area in question,
92 * without writing back dirty entries first. This is useful if the data will
93 * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
94 * _physical_ address.
95 */
96
97void cache_clear (unsigned long paddr, int len)
98{
99 if (CPU_IS_COLDFIRE) {
100 clear_cf_bcache(0, DCACHE_MAX_ADDR);
101 } else if (CPU_IS_040_OR_060) {
102 int tmp;
103
104 /*
105 * We need special treatment for the first page, in case it
106 * is not page-aligned. Page align the addresses to work
107 * around bug I17 in the 68060.
108 */
109 if ((tmp = -paddr & (PAGE_SIZE - 1))) {
110 pushcl040(paddr & PAGE_MASK);
111 if ((len -= tmp) <= 0)
112 return;
113 paddr += tmp;
114 }
115 tmp = PAGE_SIZE;
116 paddr &= PAGE_MASK;
117 while ((len -= tmp) >= 0) {
118 clear040(paddr);
119 paddr += tmp;
120 }
121 if ((len += tmp))
122 /* a page boundary gets crossed at the end */
123 pushcl040(paddr);
124 }
125 else /* 68030 or 68020 */
126 asm volatile ("movec %/cacr,%/d0\n\t"
127 "oriw %0,%/d0\n\t"
128 "movec %/d0,%/cacr"
129 : : "i" (FLUSH_I_AND_D)
130 : "d0");
131#ifdef CONFIG_M68K_L2_CACHE
132 if(mach_l2_flush)
133 mach_l2_flush(0);
134#endif
135}
136EXPORT_SYMBOL(cache_clear);
137
138
139/*
140 * cache_push() semantics: Write back any dirty cache data in the given area,
141 * and invalidate the range in the instruction cache. It needs not (but may)
142 * invalidate those entries also in the data cache. The range is defined by a
143 * _physical_ address.
144 */
145
146void cache_push (unsigned long paddr, int len)
147{
148 if (CPU_IS_COLDFIRE) {
149 flush_cf_bcache(0, DCACHE_MAX_ADDR);
150 } else if (CPU_IS_040_OR_060) {
151 int tmp = PAGE_SIZE;
152
153 /*
154 * on 68040 or 68060, push cache lines for pages in the range;
155 * on the '040 this also invalidates the pushed lines, but not on
156 * the '060!
157 */
158 len += paddr & (PAGE_SIZE - 1);
159
160 /*
161 * Work around bug I17 in the 68060 affecting some instruction
162 * lines not being invalidated properly.
163 */
164 paddr &= PAGE_MASK;
165
166 do {
167 push040(paddr);
168 paddr += tmp;
169 } while ((len -= tmp) > 0);
170 }
171 /*
172 * 68030/68020 have no writeback cache. On the other hand,
173 * cache_push is actually a superset of cache_clear (the lines
174 * get written back and invalidated), so we should make sure
175 * to perform the corresponding actions. After all, this is getting
176 * called in places where we've just loaded code, or whatever, so
177 * flushing the icache is appropriate; flushing the dcache shouldn't
178 * be required.
179 */
180 else /* 68030 or 68020 */
181 asm volatile ("movec %/cacr,%/d0\n\t"
182 "oriw %0,%/d0\n\t"
183 "movec %/d0,%/cacr"
184 : : "i" (FLUSH_I)
185 : "d0");
186#ifdef CONFIG_M68K_L2_CACHE
187 if(mach_l2_flush)
188 mach_l2_flush(1);
189#endif
190}
191EXPORT_SYMBOL(cache_push);
192
1/*
2 * linux/arch/m68k/mm/memory.c
3 *
4 * Copyright (C) 1995 Hamish Macdonald
5 */
6
7#include <linux/module.h>
8#include <linux/mm.h>
9#include <linux/kernel.h>
10#include <linux/string.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/pagemap.h>
14#include <linux/gfp.h>
15
16#include <asm/setup.h>
17#include <asm/segment.h>
18#include <asm/page.h>
19#include <asm/pgalloc.h>
20#include <asm/traps.h>
21#include <asm/machdep.h>
22
23
24/* ++andreas: {get,free}_pointer_table rewritten to use unused fields from
25 struct page instead of separately kmalloced struct. Stolen from
26 arch/sparc/mm/srmmu.c ... */
27
28typedef struct list_head ptable_desc;
29static LIST_HEAD(ptable_list);
30
31#define PD_PTABLE(page) ((ptable_desc *)&(virt_to_page(page)->lru))
32#define PD_PAGE(ptable) (list_entry(ptable, struct page, lru))
33#define PD_MARKBITS(dp) (*(unsigned char *)&PD_PAGE(dp)->index)
34
35#define PTABLE_SIZE (PTRS_PER_PMD * sizeof(pmd_t))
36
37void __init init_pointer_table(unsigned long ptable)
38{
39 ptable_desc *dp;
40 unsigned long page = ptable & PAGE_MASK;
41 unsigned char mask = 1 << ((ptable - page)/PTABLE_SIZE);
42
43 dp = PD_PTABLE(page);
44 if (!(PD_MARKBITS(dp) & mask)) {
45 PD_MARKBITS(dp) = 0xff;
46 list_add(dp, &ptable_list);
47 }
48
49 PD_MARKBITS(dp) &= ~mask;
50#ifdef DEBUG
51 printk("init_pointer_table: %lx, %x\n", ptable, PD_MARKBITS(dp));
52#endif
53
54 /* unreserve the page so it's possible to free that page */
55 PD_PAGE(dp)->flags &= ~(1 << PG_reserved);
56 init_page_count(PD_PAGE(dp));
57
58 return;
59}
60
61pmd_t *get_pointer_table (void)
62{
63 ptable_desc *dp = ptable_list.next;
64 unsigned char mask = PD_MARKBITS (dp);
65 unsigned char tmp;
66 unsigned int off;
67
68 /*
69 * For a pointer table for a user process address space, a
70 * table is taken from a page allocated for the purpose. Each
71 * page can hold 8 pointer tables. The page is remapped in
72 * virtual address space to be noncacheable.
73 */
74 if (mask == 0) {
75 void *page;
76 ptable_desc *new;
77
78 if (!(page = (void *)get_zeroed_page(GFP_KERNEL)))
79 return NULL;
80
81 flush_tlb_kernel_page(page);
82 nocache_page(page);
83
84 new = PD_PTABLE(page);
85 PD_MARKBITS(new) = 0xfe;
86 list_add_tail(new, dp);
87
88 return (pmd_t *)page;
89 }
90
91 for (tmp = 1, off = 0; (mask & tmp) == 0; tmp <<= 1, off += PTABLE_SIZE)
92 ;
93 PD_MARKBITS(dp) = mask & ~tmp;
94 if (!PD_MARKBITS(dp)) {
95 /* move to end of list */
96 list_move_tail(dp, &ptable_list);
97 }
98 return (pmd_t *) (page_address(PD_PAGE(dp)) + off);
99}
100
101int free_pointer_table (pmd_t *ptable)
102{
103 ptable_desc *dp;
104 unsigned long page = (unsigned long)ptable & PAGE_MASK;
105 unsigned char mask = 1 << (((unsigned long)ptable - page)/PTABLE_SIZE);
106
107 dp = PD_PTABLE(page);
108 if (PD_MARKBITS (dp) & mask)
109 panic ("table already free!");
110
111 PD_MARKBITS (dp) |= mask;
112
113 if (PD_MARKBITS(dp) == 0xff) {
114 /* all tables in page are free, free page */
115 list_del(dp);
116 cache_page((void *)page);
117 free_page (page);
118 return 1;
119 } else if (ptable_list.next != dp) {
120 /*
121 * move this descriptor to the front of the list, since
122 * it has one or more free tables.
123 */
124 list_move(dp, &ptable_list);
125 }
126 return 0;
127}
128
129/* invalidate page in both caches */
130static inline void clear040(unsigned long paddr)
131{
132 asm volatile (
133 "nop\n\t"
134 ".chip 68040\n\t"
135 "cinvp %%bc,(%0)\n\t"
136 ".chip 68k"
137 : : "a" (paddr));
138}
139
140/* invalidate page in i-cache */
141static inline void cleari040(unsigned long paddr)
142{
143 asm volatile (
144 "nop\n\t"
145 ".chip 68040\n\t"
146 "cinvp %%ic,(%0)\n\t"
147 ".chip 68k"
148 : : "a" (paddr));
149}
150
151/* push page in both caches */
152/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
153static inline void push040(unsigned long paddr)
154{
155 asm volatile (
156 "nop\n\t"
157 ".chip 68040\n\t"
158 "cpushp %%bc,(%0)\n\t"
159 ".chip 68k"
160 : : "a" (paddr));
161}
162
163/* push and invalidate page in both caches, must disable ints
164 * to avoid invalidating valid data */
165static inline void pushcl040(unsigned long paddr)
166{
167 unsigned long flags;
168
169 local_irq_save(flags);
170 push040(paddr);
171 if (CPU_IS_060)
172 clear040(paddr);
173 local_irq_restore(flags);
174}
175
176/*
177 * 040: Hit every page containing an address in the range paddr..paddr+len-1.
178 * (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
179 * Hit every page until there is a page or less to go. Hit the next page,
180 * and the one after that if the range hits it.
181 */
182/* ++roman: A little bit more care is required here: The CINVP instruction
183 * invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
184 * and the end of the region must be treated differently if they are not
185 * exactly at the beginning or end of a page boundary. Else, maybe too much
186 * data becomes invalidated and thus lost forever. CPUSHP does what we need:
187 * it invalidates the page after pushing dirty data to memory. (Thanks to Jes
188 * for discovering the problem!)
189 */
190/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
191 * the DPI bit in the CACR; would it cause problems with temporarily changing
192 * this?). So we have to push first and then additionally to invalidate.
193 */
194
195
196/*
197 * cache_clear() semantics: Clear any cache entries for the area in question,
198 * without writing back dirty entries first. This is useful if the data will
199 * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
200 * _physical_ address.
201 */
202
203void cache_clear (unsigned long paddr, int len)
204{
205 if (CPU_IS_COLDFIRE) {
206 clear_cf_bcache(0, DCACHE_MAX_ADDR);
207 } else if (CPU_IS_040_OR_060) {
208 int tmp;
209
210 /*
211 * We need special treatment for the first page, in case it
212 * is not page-aligned. Page align the addresses to work
213 * around bug I17 in the 68060.
214 */
215 if ((tmp = -paddr & (PAGE_SIZE - 1))) {
216 pushcl040(paddr & PAGE_MASK);
217 if ((len -= tmp) <= 0)
218 return;
219 paddr += tmp;
220 }
221 tmp = PAGE_SIZE;
222 paddr &= PAGE_MASK;
223 while ((len -= tmp) >= 0) {
224 clear040(paddr);
225 paddr += tmp;
226 }
227 if ((len += tmp))
228 /* a page boundary gets crossed at the end */
229 pushcl040(paddr);
230 }
231 else /* 68030 or 68020 */
232 asm volatile ("movec %/cacr,%/d0\n\t"
233 "oriw %0,%/d0\n\t"
234 "movec %/d0,%/cacr"
235 : : "i" (FLUSH_I_AND_D)
236 : "d0");
237#ifdef CONFIG_M68K_L2_CACHE
238 if(mach_l2_flush)
239 mach_l2_flush(0);
240#endif
241}
242EXPORT_SYMBOL(cache_clear);
243
244
245/*
246 * cache_push() semantics: Write back any dirty cache data in the given area,
247 * and invalidate the range in the instruction cache. It needs not (but may)
248 * invalidate those entries also in the data cache. The range is defined by a
249 * _physical_ address.
250 */
251
252void cache_push (unsigned long paddr, int len)
253{
254 if (CPU_IS_COLDFIRE) {
255 flush_cf_bcache(0, DCACHE_MAX_ADDR);
256 } else if (CPU_IS_040_OR_060) {
257 int tmp = PAGE_SIZE;
258
259 /*
260 * on 68040 or 68060, push cache lines for pages in the range;
261 * on the '040 this also invalidates the pushed lines, but not on
262 * the '060!
263 */
264 len += paddr & (PAGE_SIZE - 1);
265
266 /*
267 * Work around bug I17 in the 68060 affecting some instruction
268 * lines not being invalidated properly.
269 */
270 paddr &= PAGE_MASK;
271
272 do {
273 push040(paddr);
274 paddr += tmp;
275 } while ((len -= tmp) > 0);
276 }
277 /*
278 * 68030/68020 have no writeback cache. On the other hand,
279 * cache_push is actually a superset of cache_clear (the lines
280 * get written back and invalidated), so we should make sure
281 * to perform the corresponding actions. After all, this is getting
282 * called in places where we've just loaded code, or whatever, so
283 * flushing the icache is appropriate; flushing the dcache shouldn't
284 * be required.
285 */
286 else /* 68030 or 68020 */
287 asm volatile ("movec %/cacr,%/d0\n\t"
288 "oriw %0,%/d0\n\t"
289 "movec %/d0,%/cacr"
290 : : "i" (FLUSH_I)
291 : "d0");
292#ifdef CONFIG_M68K_L2_CACHE
293 if(mach_l2_flush)
294 mach_l2_flush(1);
295#endif
296}
297EXPORT_SYMBOL(cache_push);
298