1/* SPDX-License-Identifier: GPL-2.0 */
 2
 3#ifndef __ASM_CSKY_PGTABLE_BITS_H
 4#define __ASM_CSKY_PGTABLE_BITS_H
 5
 6/* implemented in software */
 7#define _PAGE_ACCESSED		(1<<7)
 8#define _PAGE_READ		(1<<8)
 9#define _PAGE_WRITE		(1<<9)
10#define _PAGE_PRESENT		(1<<10)
11#define _PAGE_MODIFIED		(1<<11)
12
13/* implemented in hardware */
14#define _PAGE_GLOBAL		(1<<0)
15#define _PAGE_VALID		(1<<1)
16#define _PAGE_DIRTY		(1<<2)
17
18#define _PAGE_SO		(1<<5)
19#define _PAGE_BUF		(1<<6)
20#define _PAGE_CACHE		(1<<3)
21#define _CACHE_MASK		_PAGE_CACHE
22
23#define _CACHE_CACHED		(_PAGE_CACHE | _PAGE_BUF)
24#define _CACHE_UNCACHED		(0)
25
26#define _PAGE_PROT_NONE		_PAGE_WRITE
27
28/*
29 * Encode and decode a swap entry
30 *
31 * Format of swap PTE:
32 *     bit          0:    _PAGE_GLOBAL (zero)
33 *     bit          1:    _PAGE_VALID (zero)
34 *     bit      2 - 6:    swap type
35 *     bit      7 - 8:    swap offset[0 - 1]
36 *     bit          9:    _PAGE_WRITE (zero)
37 *     bit         10:    _PAGE_PRESENT (zero)
38 *     bit    11 - 31:    swap offset[2 - 22]
39 */
40#define __swp_type(x)			(((x).val >> 2) & 0x1f)
41#define __swp_offset(x)			((((x).val >> 7) & 0x3) | \
42					(((x).val >> 9) & 0x7ffffc))
43#define __swp_entry(type, offset)	((swp_entry_t) { \
44					((type & 0x1f) << 2) | \
45					((offset & 0x3) << 7) | \
46					((offset & 0x7ffffc) << 9)})
47
48#endif /* __ASM_CSKY_PGTABLE_BITS_H */