1/* SPDX-License-Identifier: GPL-2.0 */
  2
  3#ifndef __ASM_CSKY_ENTRY_H
  4#define __ASM_CSKY_ENTRY_H
  5
  6#include <asm/setup.h>
  7#include <abi/regdef.h>
  8
  9#define LSAVE_PC	8
 10#define LSAVE_PSR	12
 11#define LSAVE_A0	24
 12#define LSAVE_A1	28
 13#define LSAVE_A2	32
 14#define LSAVE_A3	36
 15#define LSAVE_A4	40
 16#define LSAVE_A5	44
 17
 18#define KSPTOUSP
 19#define USPTOKSP
 20
 21#define usp cr<14, 1>
 22
 23.macro SAVE_ALL epc_inc
 24	subi    sp, 152
 25	stw	tls, (sp, 0)
 26	stw	lr, (sp, 4)
 27
 28	RD_MEH	lr
 29	WR_MEH	lr
 30
 31	mfcr	lr, epc
 32	movi	tls, \epc_inc
 33	add	lr, tls
 34	stw	lr, (sp, 8)
 35
 36	mfcr	lr, epsr
 37	stw	lr, (sp, 12)
 38	btsti   lr, 31
 39	bf      1f
 40	addi    lr, sp, 152
 41	br	2f
 421:
 43	mfcr	lr, usp
 442:
 45	stw	lr, (sp, 16)
 46
 47	stw     a0, (sp, 20)
 48	stw     a0, (sp, 24)
 49	stw     a1, (sp, 28)
 50	stw     a2, (sp, 32)
 51	stw     a3, (sp, 36)
 52
 53	addi	sp, 40
 54	stm	r4-r13, (sp)
 55
 56	addi    sp, 40
 57	stm     r16-r30, (sp)
 58#ifdef CONFIG_CPU_HAS_HILO
 59	mfhi	lr
 60	stw	lr, (sp, 60)
 61	mflo	lr
 62	stw	lr, (sp, 64)
 63	mfcr	lr, cr14
 64	stw	lr, (sp, 68)
 65#endif
 66	subi	sp, 80
 67.endm
 68
 69.macro	RESTORE_ALL
 70	ldw	tls, (sp, 0)
 71	ldw	lr, (sp, 4)
 72	ldw	a0, (sp, 8)
 73	mtcr	a0, epc
 74	ldw	a0, (sp, 12)
 75	mtcr	a0, epsr
 76	btsti   a0, 31
 77	ldw	a0, (sp, 16)
 78	mtcr	a0, usp
 79	mtcr	a0, ss0
 80
 81#ifdef CONFIG_CPU_HAS_HILO
 82	ldw	a0, (sp, 140)
 83	mthi	a0
 84	ldw	a0, (sp, 144)
 85	mtlo	a0
 86	ldw	a0, (sp, 148)
 87	mtcr	a0, cr14
 88#endif
 89
 90	ldw     a0, (sp, 24)
 91	ldw     a1, (sp, 28)
 92	ldw     a2, (sp, 32)
 93	ldw     a3, (sp, 36)
 94
 95	addi	sp, 40
 96	ldm	r4-r13, (sp)
 97	addi    sp, 40
 98	ldm     r16-r30, (sp)
 99	addi    sp, 72
100	bf	1f
101	mfcr	sp, ss0
1021:
103	rte
104.endm
105
106.macro SAVE_REGS_FTRACE
107	subi    sp, 152
108	stw	tls, (sp, 0)
109	stw	lr, (sp, 4)
110
111	mfcr	lr, psr
112	stw	lr, (sp, 12)
113
114	addi    lr, sp, 152
115	stw	lr, (sp, 16)
116
117	stw     a0, (sp, 20)
118	stw     a0, (sp, 24)
119	stw     a1, (sp, 28)
120	stw     a2, (sp, 32)
121	stw     a3, (sp, 36)
122
123	addi	sp, 40
124	stm	r4-r13, (sp)
125
126	addi    sp, 40
127	stm     r16-r30, (sp)
128#ifdef CONFIG_CPU_HAS_HILO
129	mfhi	lr
130	stw	lr, (sp, 60)
131	mflo	lr
132	stw	lr, (sp, 64)
133	mfcr	lr, cr14
134	stw	lr, (sp, 68)
135#endif
136	subi	sp, 80
137.endm
138
139.macro	RESTORE_REGS_FTRACE
140	ldw	tls, (sp, 0)
141
142#ifdef CONFIG_CPU_HAS_HILO
143	ldw	a0, (sp, 140)
144	mthi	a0
145	ldw	a0, (sp, 144)
146	mtlo	a0
147	ldw	a0, (sp, 148)
148	mtcr	a0, cr14
149#endif
150
151	ldw     a0, (sp, 24)
152	ldw     a1, (sp, 28)
153	ldw     a2, (sp, 32)
154	ldw     a3, (sp, 36)
155
156	addi	sp, 40
157	ldm	r4-r13, (sp)
158	addi    sp, 40
159	ldm     r16-r30, (sp)
160	addi    sp, 72
161.endm
162
163.macro SAVE_SWITCH_STACK
164	subi    sp, 64
165	stm	r4-r11, (sp)
166	stw	lr,  (sp, 32)
167	stw	r16, (sp, 36)
168	stw	r17, (sp, 40)
169	stw	r26, (sp, 44)
170	stw	r27, (sp, 48)
171	stw	r28, (sp, 52)
172	stw	r29, (sp, 56)
173	stw	r30, (sp, 60)
174#ifdef CONFIG_CPU_HAS_HILO
175	subi	sp, 16
176	mfhi	lr
177	stw	lr, (sp, 0)
178	mflo	lr
179	stw	lr, (sp, 4)
180	mfcr	lr, cr14
181	stw	lr, (sp, 8)
182#endif
183.endm
184
185.macro RESTORE_SWITCH_STACK
186#ifdef CONFIG_CPU_HAS_HILO
187	ldw	lr, (sp, 0)
188	mthi	lr
189	ldw	lr, (sp, 4)
190	mtlo	lr
191	ldw	lr, (sp, 8)
192	mtcr	lr, cr14
193	addi	sp, 16
194#endif
195	ldm	r4-r11, (sp)
196	ldw	lr,  (sp, 32)
197	ldw	r16, (sp, 36)
198	ldw	r17, (sp, 40)
199	ldw	r26, (sp, 44)
200	ldw	r27, (sp, 48)
201	ldw	r28, (sp, 52)
202	ldw	r29, (sp, 56)
203	ldw	r30, (sp, 60)
204	addi	sp, 64
205.endm
206
207/* MMU registers operators. */
208.macro RD_MIR rx
209	mfcr	\rx, cr<0, 15>
210.endm
211
212.macro RD_MEH rx
213	mfcr	\rx, cr<4, 15>
214.endm
215
216.macro RD_MCIR rx
217	mfcr	\rx, cr<8, 15>
218.endm
219
220.macro RD_PGDR rx
221	mfcr	\rx, cr<29, 15>
222.endm
223
224.macro RD_PGDR_K rx
225	mfcr	\rx, cr<28, 15>
226.endm
227
228.macro WR_MEH rx
229	mtcr	\rx, cr<4, 15>
230.endm
231
232.macro WR_MCIR rx
233	mtcr	\rx, cr<8, 15>
234.endm
235
236#ifdef CONFIG_PAGE_OFFSET_80000000
237#define MSA_SET cr<30, 15>
238#define MSA_CLR cr<31, 15>
239#endif
240
241#ifdef CONFIG_PAGE_OFFSET_A0000000
242#define MSA_SET cr<31, 15>
243#define MSA_CLR cr<30, 15>
244#endif
245
246.macro SETUP_MMU
247	/* Init psr and enable ee */
248	lrw	r6, DEFAULT_PSR_VALUE
249	mtcr    r6, psr
250	psrset  ee
251
252	/* Invalid I/Dcache BTB BHT */
253	movi	r6, 7
254	lsli	r6, 16
255	addi	r6, (1<<4) | 3
256	mtcr	r6, cr17
257
258	/* Invalid all TLB */
259	bgeni   r6, 26
260	mtcr	r6, cr<8, 15> /* Set MCIR */
261
262	/* Check MMU on/off */
263	mfcr	r6, cr18
264	btsti	r6, 0
265	bt	1f
266
267	/* MMU off: setup mapping tlb entry */
268	movi	r6, 0
269	mtcr	r6, cr<6, 15> /* Set MPR with 4K page size */
270
271	grs	r6, 1f /* Get current pa by PC */
272	bmaski  r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */
273	andn    r6, r7
274	mtcr	r6, cr<4, 15> /* Set MEH */
275
276	mov	r8, r6
277	movi    r7, 0x00000006
278	or      r8, r7
279	mtcr	r8, cr<2, 15> /* Set MEL0 */
280	movi    r7, 0x00001006
281	or      r8, r7
282	mtcr	r8, cr<3, 15> /* Set MEL1 */
283
284	bgeni   r8, 28
285	mtcr	r8, cr<8, 15> /* Set MCIR to write TLB */
286
287	br	2f
2881:
289	/*
290	 * MMU on: use origin MSA value from bootloader
291	 *
292	 * cr<30/31, 15> MSA register format:
293	 * 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
294	 *   BA     Reserved  SH  WA  B   SO SEC  C   D   V
295	 */
296	mfcr	r6, MSA_SET /* Get MSA */
2972:
298	lsri	r6, 29
299	lsli	r6, 29
300	addi	r6, 0x1ce
301	mtcr	r6, MSA_SET /* Set MSA */
302
303	movi    r6, 0
304	mtcr	r6, MSA_CLR /* Clr MSA */
305
306	/* enable MMU */
307	mfcr    r6, cr18
308	bseti	r6, 0
309	mtcr    r6, cr18
310
311	jmpi	3f /* jump to va */
3123:
313.endm
314#endif /* __ASM_CSKY_ENTRY_H */