1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Common Device Tree Source for IGEP COM MODULE
  4 *
  5 * Copyright (C) 2014 Javier Martinez Canillas <javier@dowhile0.org>
  6 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
  7 */
  8
  9#include "omap3-igep.dtsi"
 10
 11/ {
 12	leds: gpio_leds {
 13		compatible = "gpio-leds";
 14
 15		user0 {
 16			 label = "omap3:red:user0";
 17			 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>;	/* LEDA */
 18			 default-state = "off";
 19		};
 20
 21		user1 {
 22			 label = "omap3:green:user1";
 23			 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;	/* LEDB */
 24			 default-state = "off";
 25		};
 26
 27		user2 {
 28			 label = "omap3:red:user1";
 29			 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;		/* gpio_16 */
 30			 default-state = "off";
 31		};
 32	};
 33
 34	hsusb2_phy: hsusb2_phy {
 35		compatible = "usb-nop-xceiv";
 36		reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;		/* gpio_54 */
 37		#phy-cells = <0>;
 38	};
 39};
 40
 41&omap3_pmx_core {
 42	pinctrl-names = "default";
 43	pinctrl-0 = <&hsusb2_pins>;
 44
 45	hsusb2_pins: pinmux_hsusb2_pins {
 46		pinctrl-single,pins = <
 47			OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi1_cs3.hsusb2_data2 */
 48			OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_clk.hsusb2_data7 */
 49			OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_simo.hsusb2_data4 */
 50			OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_somi.hsusb2_data5 */
 51			OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs0.hsusb2_data6 */
 52			OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* mcspi2_cs1.hsusb2_data3 */
 53		>;
 54	};
 55
 56	uart2_pins: pinmux_uart2_pins {
 57		pinctrl-single,pins = <
 58			OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1)	/* mcbsp3_dx.uart2_cts */
 59			OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_dr.uart2_rts */
 60			OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1)	/* mcbsp3_clk.uart2_tx */
 61			OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1)	/* mcbsp3_fsx.uart2_rx */
 62		>;
 63	};
 64};
 65
 66&omap3_pmx_core2 {
 67	pinctrl-names = "default";
 68	pinctrl-0 = <&hsusb2_core2_pins>;
 69
 70	hsusb2_core2_pins: pinmux_hsusb2_core2_pins {
 71		pinctrl-single,pins = <
 72			OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3)		      /* etk_d10.hsusb2_clk */
 73			OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3)		      /* etk_d11.hsusb2_stp */
 74			OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d12.hsusb2_dir */
 75			OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d13.hsusb2_nxt */
 76			OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d14.hsusb2_data0 */
 77			OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3)	/* etk_d15.hsusb2_data1 */
 78		>;
 79	};
 80
 81	leds_core2_pins: pinmux_leds_core2_pins {
 82		pinctrl-single,pins = <
 83			OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4)	/* etk_d2.gpio_16 */
 84		>;
 85	};
 86};
 87
 88&usbhshost {
 89	port2-mode = "ehci-phy";
 90};
 91
 92&usbhsehci {
 93	phys = <0 &hsusb2_phy>;
 94};
 95
 96&uart2 {
 97	pinctrl-names = "default";
 98	pinctrl-0 = <&uart2_pins>;
 99};
100
101&gpmc {
102	ranges = <0 0 0x30000000 0x01000000>;   /* CS0: 16MB for NAND */
103};