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1// SPDX-License-Identifier: GPL-2.0
2/ {
3 mbus@f1000000 {
4 pciec: pcie@82000000 {
5 compatible = "marvell,kirkwood-pcie";
6 status = "disabled";
7 device_type = "pci";
8
9 #address-cells = <3>;
10 #size-cells = <2>;
11
12 bus-range = <0x00 0xff>;
13
14 ranges =
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
17 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
18 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
19 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
20 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
21 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
22
23 pcie0: pcie@1,0 {
24 device_type = "pci";
25 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
26 reg = <0x0800 0 0 0 0>;
27 #address-cells = <3>;
28 #size-cells = <2>;
29 #interrupt-cells = <1>;
30 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
31 0x81000000 0 0 0x81000000 0x1 0 1 0>;
32 bus-range = <0x00 0xff>;
33 interrupt-names = "intx", "error";
34 interrupts = <9>, <44>;
35 interrupt-map-mask = <0 0 0 7>;
36 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
37 <0 0 0 2 &pcie0_intc 1>,
38 <0 0 0 3 &pcie0_intc 2>,
39 <0 0 0 4 &pcie0_intc 3>;
40 marvell,pcie-port = <0>;
41 marvell,pcie-lane = <0>;
42 clocks = <&gate_clk 2>;
43 status = "disabled";
44
45 pcie0_intc: interrupt-controller {
46 interrupt-controller;
47 #interrupt-cells = <1>;
48 };
49 };
50
51 pcie1: pcie@2,0 {
52 device_type = "pci";
53 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
54 reg = <0x1000 0 0 0 0>;
55 #address-cells = <3>;
56 #size-cells = <2>;
57 #interrupt-cells = <1>;
58 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
59 0x81000000 0 0 0x81000000 0x2 0 1 0>;
60 bus-range = <0x00 0xff>;
61 interrupt-names = "intx", "error";
62 interrupts = <10>, <45>;
63 interrupt-map-mask = <0 0 0 7>;
64 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
65 <0 0 0 2 &pcie1_intc 1>,
66 <0 0 0 3 &pcie1_intc 2>,
67 <0 0 0 4 &pcie1_intc 3>;
68 marvell,pcie-port = <1>;
69 marvell,pcie-lane = <0>;
70 clocks = <&gate_clk 18>;
71 status = "disabled";
72
73 pcie1_intc: interrupt-controller {
74 interrupt-controller;
75 #interrupt-cells = <1>;
76 };
77 };
78 };
79 };
80 ocp@f1000000 {
81
82 pinctrl: pin-controller@10000 {
83 compatible = "marvell,88f6282-pinctrl";
84
85 pmx_sata0: pmx-sata0 {
86 marvell,pins = "mpp5", "mpp21", "mpp23";
87 marvell,function = "sata0";
88 };
89 pmx_sata1: pmx-sata1 {
90 marvell,pins = "mpp4", "mpp20", "mpp22";
91 marvell,function = "sata1";
92 };
93
94 /*
95 * Default I2C1 pinctrl setting on mpp36/mpp37,
96 * overwrite marvell,pins on board level if required.
97 */
98 pmx_twsi1: pmx-twsi1 {
99 marvell,pins = "mpp36", "mpp37";
100 marvell,function = "twsi1";
101 };
102
103 pmx_sdio: pmx-sdio {
104 marvell,pins = "mpp12", "mpp13", "mpp14",
105 "mpp15", "mpp16", "mpp17";
106 marvell,function = "sdio";
107 };
108 };
109
110 thermal: thermal@10078 {
111 compatible = "marvell,kirkwood-thermal";
112 reg = <0x10078 0x4>;
113 status = "okay";
114 };
115
116 rtc: rtc@10300 {
117 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
118 reg = <0x10300 0x20>;
119 interrupts = <53>;
120 clocks = <&gate_clk 7>;
121 };
122
123 i2c1: i2c@11100 {
124 compatible = "marvell,mv64xxx-i2c";
125 reg = <0x11100 0x20>;
126 #address-cells = <1>;
127 #size-cells = <0>;
128 interrupts = <32>;
129 clock-frequency = <100000>;
130 clocks = <&gate_clk 7>;
131 pinctrl-0 = <&pmx_twsi1>;
132 pinctrl-names = "default";
133 status = "disabled";
134 };
135
136 sata: sata@80000 {
137 compatible = "marvell,orion-sata";
138 reg = <0x80000 0x5000>;
139 interrupts = <21>;
140 clocks = <&gate_clk 14>, <&gate_clk 15>;
141 clock-names = "0", "1";
142 phys = <&sata_phy0>, <&sata_phy1>;
143 phy-names = "port0", "port1";
144 status = "disabled";
145 };
146
147 sdio: mvsdio@90000 {
148 compatible = "marvell,orion-sdio";
149 reg = <0x90000 0x200>;
150 interrupts = <28>;
151 clocks = <&gate_clk 4>;
152 pinctrl-0 = <&pmx_sdio>;
153 pinctrl-names = "default";
154 bus-width = <4>;
155 cap-sdio-irq;
156 cap-sd-highspeed;
157 cap-mmc-highspeed;
158 status = "disabled";
159 };
160 };
161};
1/ {
2 mbus {
3 pcie-controller {
4 compatible = "marvell,kirkwood-pcie";
5 status = "disabled";
6 device_type = "pci";
7
8 #address-cells = <3>;
9 #size-cells = <2>;
10
11 bus-range = <0x00 0xff>;
12
13 ranges =
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
16 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
17 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
18 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
19 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
20 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
21
22 pcie@1,0 {
23 device_type = "pci";
24 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
25 reg = <0x0800 0 0 0 0>;
26 #address-cells = <3>;
27 #size-cells = <2>;
28 #interrupt-cells = <1>;
29 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
30 0x81000000 0 0 0x81000000 0x1 0 1 0>;
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &intc 9>;
33 marvell,pcie-port = <0>;
34 marvell,pcie-lane = <0>;
35 clocks = <&gate_clk 2>;
36 status = "disabled";
37 };
38
39 pcie@2,0 {
40 device_type = "pci";
41 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
42 reg = <0x1000 0 0 0 0>;
43 #address-cells = <3>;
44 #size-cells = <2>;
45 #interrupt-cells = <1>;
46 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
47 0x81000000 0 0 0x81000000 0x2 0 1 0>;
48 interrupt-map-mask = <0 0 0 0>;
49 interrupt-map = <0 0 0 0 &intc 10>;
50 marvell,pcie-port = <1>;
51 marvell,pcie-lane = <0>;
52 clocks = <&gate_clk 18>;
53 status = "disabled";
54 };
55 };
56 };
57 ocp@f1000000 {
58
59 pinctrl: pinctrl@10000 {
60 compatible = "marvell,88f6282-pinctrl";
61 reg = <0x10000 0x20>;
62
63 pmx_nand: pmx-nand {
64 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
65 "mpp4", "mpp5", "mpp18", "mpp19";
66 marvell,function = "nand";
67 };
68
69 pmx_sata0: pmx-sata0 {
70 marvell,pins = "mpp5", "mpp21", "mpp23";
71 marvell,function = "sata0";
72 };
73 pmx_sata1: pmx-sata1 {
74 marvell,pins = "mpp4", "mpp20", "mpp22";
75 marvell,function = "sata1";
76 };
77 pmx_spi: pmx-spi {
78 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
79 marvell,function = "spi";
80 };
81 pmx_twsi0: pmx-twsi0 {
82 marvell,pins = "mpp8", "mpp9";
83 marvell,function = "twsi0";
84 };
85
86 pmx_twsi1: pmx-twsi1 {
87 marvell,pins = "mpp36", "mpp37";
88 marvell,function = "twsi1";
89 };
90
91 pmx_uart0: pmx-uart0 {
92 marvell,pins = "mpp10", "mpp11";
93 marvell,function = "uart0";
94 };
95
96 pmx_uart1: pmx-uart1 {
97 marvell,pins = "mpp13", "mpp14";
98 marvell,function = "uart1";
99 };
100 pmx_sdio: pmx-sdio {
101 marvell,pins = "mpp12", "mpp13", "mpp14",
102 "mpp15", "mpp16", "mpp17";
103 marvell,function = "sdio";
104 };
105 };
106
107 thermal@10078 {
108 compatible = "marvell,kirkwood-thermal";
109 reg = <0x10078 0x4>;
110 status = "okay";
111 };
112
113 rtc@10300 {
114 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
115 reg = <0x10300 0x20>;
116 interrupts = <53>;
117 clocks = <&gate_clk 7>;
118 };
119
120 i2c@11100 {
121 compatible = "marvell,mv64xxx-i2c";
122 reg = <0x11100 0x20>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 interrupts = <32>;
126 clock-frequency = <100000>;
127 clocks = <&gate_clk 7>;
128 status = "disabled";
129 };
130
131 sata@80000 {
132 compatible = "marvell,orion-sata";
133 reg = <0x80000 0x5000>;
134 interrupts = <21>;
135 clocks = <&gate_clk 14>, <&gate_clk 15>;
136 clock-names = "0", "1";
137 phys = <&sata_phy0>, <&sata_phy1>;
138 phy-names = "port0", "port1";
139 status = "disabled";
140 };
141
142 mvsdio@90000 {
143 compatible = "marvell,orion-sdio";
144 reg = <0x90000 0x200>;
145 interrupts = <28>;
146 clocks = <&gate_clk 4>;
147 pinctrl-0 = <&pmx_sdio>;
148 pinctrl-names = "default";
149 bus-width = <4>;
150 cap-sdio-irq;
151 cap-sd-highspeed;
152 cap-mmc-highspeed;
153 status = "disabled";
154 };
155 };
156};