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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada XP family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk>
11 *
12 * Contains definitions specific to the Armada XP SoC that are not
13 * common to all Armada SoCs.
14 */
15
16#include "armada-370-xp.dtsi"
17
18/ {
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 aliases {
26 serial2 = &uart2;
27 serial3 = &uart3;
28 };
29
30 soc {
31 compatible = "marvell,armadaxp-mbus", "simple-bus";
32
33 bootrom {
34 compatible = "marvell,bootrom";
35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
36 };
37
38 internal-regs {
39 sdramc: sdramc@1400 {
40 compatible = "marvell,armada-xp-sdram-controller";
41 reg = <0x1400 0x500>;
42 };
43
44 L2: l2-cache@8000 {
45 compatible = "marvell,aurora-system-cache";
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
48 cache-level = <2>;
49 cache-unified;
50 wt-override;
51 };
52
53 uart2: serial@12200 {
54 compatible = "snps,dw-apb-uart";
55 pinctrl-0 = <&uart2_pins>;
56 pinctrl-names = "default";
57 reg = <0x12200 0x100>;
58 reg-shift = <2>;
59 interrupts = <43>;
60 reg-io-width = <1>;
61 clocks = <&coreclk 0>;
62 status = "disabled";
63 };
64
65 uart3: serial@12300 {
66 compatible = "snps,dw-apb-uart";
67 pinctrl-0 = <&uart3_pins>;
68 pinctrl-names = "default";
69 reg = <0x12300 0x100>;
70 reg-shift = <2>;
71 interrupts = <44>;
72 reg-io-width = <1>;
73 clocks = <&coreclk 0>;
74 status = "disabled";
75 };
76
77 systemc: system-controller@18200 {
78 compatible = "marvell,armada-370-xp-system-controller";
79 reg = <0x18200 0x500>;
80 };
81
82 gateclk: clock-gating-control@18220 {
83 compatible = "marvell,armada-xp-gating-clock";
84 reg = <0x18220 0x4>;
85 clocks = <&coreclk 0>;
86 #clock-cells = <1>;
87 };
88
89 coreclk: mvebu-sar@18230 {
90 compatible = "marvell,armada-xp-core-clock";
91 reg = <0x18230 0x08>;
92 #clock-cells = <1>;
93 };
94
95 thermal: thermal@182b0 {
96 compatible = "marvell,armadaxp-thermal";
97 reg = <0x182b0 0x4
98 0x184d0 0x4>;
99 status = "okay";
100 };
101
102 cpuclk: clock-complex@18700 {
103 #clock-cells = <1>;
104 compatible = "marvell,armada-xp-cpu-clock";
105 reg = <0x18700 0x24>, <0x1c054 0x10>;
106 clocks = <&coreclk 1>;
107 };
108
109 cpu-config@21000 {
110 compatible = "marvell,armada-xp-cpu-config";
111 reg = <0x21000 0x8>;
112 };
113
114 eth2: ethernet@30000 {
115 compatible = "marvell,armada-xp-neta";
116 reg = <0x30000 0x4000>;
117 interrupts = <12>;
118 clocks = <&gateclk 2>;
119 status = "disabled";
120 };
121
122 usb2: usb@52000 {
123 compatible = "marvell,orion-ehci";
124 reg = <0x52000 0x500>;
125 interrupts = <47>;
126 clocks = <&gateclk 20>;
127 status = "disabled";
128 };
129
130 xor1: xor@60900 {
131 compatible = "marvell,orion-xor";
132 reg = <0x60900 0x100
133 0x60b00 0x100>;
134 clocks = <&gateclk 22>;
135 status = "okay";
136
137 xor10 {
138 interrupts = <51>;
139 dmacap,memcpy;
140 dmacap,xor;
141 };
142 xor11 {
143 interrupts = <52>;
144 dmacap,memcpy;
145 dmacap,xor;
146 dmacap,memset;
147 };
148 };
149
150 ethernet@70000 {
151 compatible = "marvell,armada-xp-neta";
152 };
153
154 ethernet@74000 {
155 compatible = "marvell,armada-xp-neta";
156 };
157
158 cesa: crypto@90000 {
159 compatible = "marvell,armada-xp-crypto";
160 reg = <0x90000 0x10000>;
161 reg-names = "regs";
162 interrupts = <48>, <49>;
163 clocks = <&gateclk 23>, <&gateclk 23>;
164 clock-names = "cesa0", "cesa1";
165 marvell,crypto-srams = <&crypto_sram0>,
166 <&crypto_sram1>;
167 marvell,crypto-sram-size = <0x800>;
168 };
169
170 bm: bm@c0000 {
171 compatible = "marvell,armada-380-neta-bm";
172 reg = <0xc0000 0xac>;
173 clocks = <&gateclk 13>;
174 internal-mem = <&bm_bppi>;
175 status = "disabled";
176 };
177
178 xor0: xor@f0900 {
179 compatible = "marvell,orion-xor";
180 reg = <0xF0900 0x100
181 0xF0B00 0x100>;
182 clocks = <&gateclk 28>;
183 status = "okay";
184
185 xor00 {
186 interrupts = <94>;
187 dmacap,memcpy;
188 dmacap,xor;
189 };
190 xor01 {
191 interrupts = <95>;
192 dmacap,memcpy;
193 dmacap,xor;
194 dmacap,memset;
195 };
196 };
197 };
198
199 crypto_sram0: sa-sram0 {
200 compatible = "mmio-sram";
201 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
202 clocks = <&gateclk 23>;
203 #address-cells = <1>;
204 #size-cells = <1>;
205 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
206 };
207
208 crypto_sram1: sa-sram1 {
209 compatible = "mmio-sram";
210 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
211 clocks = <&gateclk 23>;
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
215 };
216
217 bm_bppi: bm-bppi {
218 compatible = "mmio-sram";
219 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
220 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
221 #address-cells = <1>;
222 #size-cells = <1>;
223 clocks = <&gateclk 13>;
224 no-memory-wc;
225 status = "disabled";
226 };
227 };
228
229 clocks {
230 /* 25 MHz reference crystal */
231 refclk: oscillator {
232 compatible = "fixed-clock";
233 #clock-cells = <0>;
234 clock-frequency = <25000000>;
235 };
236 };
237};
238
239&i2c0 {
240 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
241 reg = <0x11000 0x100>;
242};
243
244&i2c1 {
245 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
246 reg = <0x11100 0x100>;
247};
248
249&mpic {
250 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
251};
252
253&timer {
254 compatible = "marvell,armada-xp-timer";
255 clocks = <&coreclk 2>, <&refclk>;
256 clock-names = "nbclk", "fixed";
257};
258
259&watchdog {
260 compatible = "marvell,armada-xp-wdt";
261 clocks = <&coreclk 2>, <&refclk>;
262 clock-names = "nbclk", "fixed";
263 interrupts = <93>, <38>;
264};
265
266&cpurst {
267 reg = <0x20800 0x20>;
268};
269
270&usb0 {
271 clocks = <&gateclk 18>;
272};
273
274&usb1 {
275 clocks = <&gateclk 19>;
276};
277
278&pinctrl {
279 ge0_gmii_pins: ge0-gmii-pins {
280 marvell,pins =
281 "mpp0", "mpp1", "mpp2", "mpp3",
282 "mpp4", "mpp5", "mpp6", "mpp7",
283 "mpp8", "mpp9", "mpp10", "mpp11",
284 "mpp12", "mpp13", "mpp14", "mpp15",
285 "mpp16", "mpp17", "mpp18", "mpp19",
286 "mpp20", "mpp21", "mpp22", "mpp23";
287 marvell,function = "ge0";
288 };
289
290 ge0_rgmii_pins: ge0-rgmii-pins {
291 marvell,pins =
292 "mpp0", "mpp1", "mpp2", "mpp3",
293 "mpp4", "mpp5", "mpp6", "mpp7",
294 "mpp8", "mpp9", "mpp10", "mpp11";
295 marvell,function = "ge0";
296 };
297
298 ge1_rgmii_pins: ge1-rgmii-pins {
299 marvell,pins =
300 "mpp12", "mpp13", "mpp14", "mpp15",
301 "mpp16", "mpp17", "mpp18", "mpp19",
302 "mpp20", "mpp21", "mpp22", "mpp23";
303 marvell,function = "ge1";
304 };
305
306 sdio_pins: sdio-pins {
307 marvell,pins = "mpp30", "mpp31", "mpp32",
308 "mpp33", "mpp34", "mpp35";
309 marvell,function = "sd0";
310 };
311
312 spi0_pins: spi0-pins {
313 marvell,pins = "mpp36", "mpp37",
314 "mpp38", "mpp39";
315 marvell,function = "spi0";
316 };
317
318 spi1_pins: spi1-pins {
319 marvell,pins = "mpp13", "mpp14",
320 "mpp16", "mpp17";
321 marvell,function = "spi1";
322 };
323
324 uart2_pins: uart2-pins {
325 marvell,pins = "mpp42", "mpp43";
326 marvell,function = "uart2";
327 };
328
329 uart3_pins: uart3-pins {
330 marvell,pins = "mpp44", "mpp45";
331 marvell,function = "uart3";
332 };
333};
334
335&spi0 {
336 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
337 pinctrl-0 = <&spi0_pins>;
338 pinctrl-names = "default";
339};
340
341&spi1 {
342 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
343 pinctrl-0 = <&spi1_pins>;
344 pinctrl-names = "default";
345};
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
17 */
18
19#include "armada-370-xp.dtsi"
20
21/ {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 aliases {
26 eth2 = ð2;
27 };
28
29 soc {
30 compatible = "marvell,armadaxp-mbus", "simple-bus";
31
32 bootrom {
33 compatible = "marvell,bootrom";
34 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
35 };
36
37 internal-regs {
38 L2: l2-cache {
39 compatible = "marvell,aurora-system-cache";
40 reg = <0x08000 0x1000>;
41 cache-id-part = <0x100>;
42 wt-override;
43 };
44
45 i2c0: i2c@11000 {
46 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
47 reg = <0x11000 0x100>;
48 };
49
50 i2c1: i2c@11100 {
51 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
52 reg = <0x11100 0x100>;
53 };
54
55 serial@12200 {
56 compatible = "snps,dw-apb-uart";
57 reg = <0x12200 0x100>;
58 reg-shift = <2>;
59 interrupts = <43>;
60 reg-io-width = <1>;
61 status = "disabled";
62 };
63 serial@12300 {
64 compatible = "snps,dw-apb-uart";
65 reg = <0x12300 0x100>;
66 reg-shift = <2>;
67 interrupts = <44>;
68 reg-io-width = <1>;
69 status = "disabled";
70 };
71
72 system-controller@18200 {
73 compatible = "marvell,armada-370-xp-system-controller";
74 reg = <0x18200 0x500>;
75 };
76
77 gateclk: clock-gating-control@18220 {
78 compatible = "marvell,armada-xp-gating-clock";
79 reg = <0x18220 0x4>;
80 clocks = <&coreclk 0>;
81 #clock-cells = <1>;
82 };
83
84 coreclk: mvebu-sar@18230 {
85 compatible = "marvell,armada-xp-core-clock";
86 reg = <0x18230 0x08>;
87 #clock-cells = <1>;
88 };
89
90 thermal@182b0 {
91 compatible = "marvell,armadaxp-thermal";
92 reg = <0x182b0 0x4
93 0x184d0 0x4>;
94 status = "okay";
95 };
96
97 cpuclk: clock-complex@18700 {
98 #clock-cells = <1>;
99 compatible = "marvell,armada-xp-cpu-clock";
100 reg = <0x18700 0xA0>;
101 clocks = <&coreclk 1>;
102 };
103
104 interrupt-controller@20000 {
105 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
106 };
107
108 timer@20300 {
109 compatible = "marvell,armada-xp-timer";
110 clocks = <&coreclk 2>, <&refclk>;
111 clock-names = "nbclk", "fixed";
112 };
113
114 watchdog@20300 {
115 compatible = "marvell,armada-xp-wdt";
116 clocks = <&coreclk 2>, <&refclk>;
117 clock-names = "nbclk", "fixed";
118 };
119
120 armada-370-xp-pmsu@22000 {
121 compatible = "marvell,armada-370-xp-pmsu";
122 reg = <0x22100 0x400>, <0x20800 0x20>;
123 };
124
125 eth2: ethernet@30000 {
126 compatible = "marvell,armada-370-neta";
127 reg = <0x30000 0x4000>;
128 interrupts = <12>;
129 clocks = <&gateclk 2>;
130 status = "disabled";
131 };
132
133 usb@50000 {
134 clocks = <&gateclk 18>;
135 };
136
137 usb@51000 {
138 clocks = <&gateclk 19>;
139 };
140
141 usb@52000 {
142 compatible = "marvell,orion-ehci";
143 reg = <0x52000 0x500>;
144 interrupts = <47>;
145 clocks = <&gateclk 20>;
146 status = "disabled";
147 };
148
149 xor@60900 {
150 compatible = "marvell,orion-xor";
151 reg = <0x60900 0x100
152 0x60b00 0x100>;
153 clocks = <&gateclk 22>;
154 status = "okay";
155
156 xor10 {
157 interrupts = <51>;
158 dmacap,memcpy;
159 dmacap,xor;
160 };
161 xor11 {
162 interrupts = <52>;
163 dmacap,memcpy;
164 dmacap,xor;
165 dmacap,memset;
166 };
167 };
168
169 xor@f0900 {
170 compatible = "marvell,orion-xor";
171 reg = <0xF0900 0x100
172 0xF0B00 0x100>;
173 clocks = <&gateclk 28>;
174 status = "okay";
175
176 xor00 {
177 interrupts = <94>;
178 dmacap,memcpy;
179 dmacap,xor;
180 };
181 xor01 {
182 interrupts = <95>;
183 dmacap,memcpy;
184 dmacap,xor;
185 dmacap,memset;
186 };
187 };
188 };
189 };
190
191 clocks {
192 /* 25 MHz reference crystal */
193 refclk: oscillator {
194 compatible = "fixed-clock";
195 #clock-cells = <0>;
196 clock-frequency = <25000000>;
197 };
198 };
199};