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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada XP family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * Contains definitions specific to the Armada XP MV78260 SoC that are not
10 * common to all Armada XP SoCs.
11 */
12
13#include "armada-xp.dtsi"
14
15/ {
16 model = "Marvell Armada XP MV78260 SoC";
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
18
19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 gpio2 = &gpio2;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
29
30 cpu@0 {
31 device_type = "cpu";
32 compatible = "marvell,sheeva-v7";
33 reg = <0>;
34 clocks = <&cpuclk 0>;
35 clock-latency = <1000000>;
36 };
37
38 cpu@1 {
39 device_type = "cpu";
40 compatible = "marvell,sheeva-v7";
41 reg = <1>;
42 clocks = <&cpuclk 1>;
43 clock-latency = <1000000>;
44 };
45 };
46
47 soc {
48 /*
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is
51 * x4 only.
52 */
53 pciec: pcie@82000000 {
54 compatible = "marvell,armada-xp-pcie";
55 status = "disabled";
56 device_type = "pci";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60
61 msi-parent = <&mpic>;
62 bus-range = <0x00 0xff>;
63
64 ranges =
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
77 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
78 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
82
83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
85 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
86 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
87 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
88 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
89 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
90 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
91
92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
94
95 pcie1: pcie@1,0 {
96 device_type = "pci";
97 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
98 reg = <0x0800 0 0 0 0>;
99 #address-cells = <3>;
100 #size-cells = <2>;
101 interrupt-names = "intx";
102 interrupts-extended = <&mpic 58>;
103 #interrupt-cells = <1>;
104 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
105 0x81000000 0 0 0x81000000 0x1 0 1 0>;
106 bus-range = <0x00 0xff>;
107 interrupt-map-mask = <0 0 0 7>;
108 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
109 <0 0 0 2 &pcie1_intc 1>,
110 <0 0 0 3 &pcie1_intc 2>,
111 <0 0 0 4 &pcie1_intc 3>;
112 marvell,pcie-port = <0>;
113 marvell,pcie-lane = <0>;
114 clocks = <&gateclk 5>;
115 status = "disabled";
116
117 pcie1_intc: interrupt-controller {
118 interrupt-controller;
119 #interrupt-cells = <1>;
120 };
121 };
122
123 pcie2: pcie@2,0 {
124 device_type = "pci";
125 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
126 reg = <0x1000 0 0 0 0>;
127 #address-cells = <3>;
128 #size-cells = <2>;
129 interrupt-names = "intx";
130 interrupts-extended = <&mpic 59>;
131 #interrupt-cells = <1>;
132 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
133 0x81000000 0 0 0x81000000 0x2 0 1 0>;
134 bus-range = <0x00 0xff>;
135 interrupt-map-mask = <0 0 0 7>;
136 interrupt-map = <0 0 0 1 &pcie2_intc 0>,
137 <0 0 0 2 &pcie2_intc 1>,
138 <0 0 0 3 &pcie2_intc 2>,
139 <0 0 0 4 &pcie2_intc 3>;
140 marvell,pcie-port = <0>;
141 marvell,pcie-lane = <1>;
142 clocks = <&gateclk 6>;
143 status = "disabled";
144
145 pcie2_intc: interrupt-controller {
146 interrupt-controller;
147 #interrupt-cells = <1>;
148 };
149 };
150
151 pcie3: pcie@3,0 {
152 device_type = "pci";
153 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
154 reg = <0x1800 0 0 0 0>;
155 #address-cells = <3>;
156 #size-cells = <2>;
157 interrupt-names = "intx";
158 interrupts-extended = <&mpic 60>;
159 #interrupt-cells = <1>;
160 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
161 0x81000000 0 0 0x81000000 0x3 0 1 0>;
162 bus-range = <0x00 0xff>;
163 interrupt-map-mask = <0 0 0 7>;
164 interrupt-map = <0 0 0 1 &pcie3_intc 0>,
165 <0 0 0 2 &pcie3_intc 1>,
166 <0 0 0 3 &pcie3_intc 2>,
167 <0 0 0 4 &pcie3_intc 3>;
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
170 clocks = <&gateclk 7>;
171 status = "disabled";
172
173 pcie3_intc: interrupt-controller {
174 interrupt-controller;
175 #interrupt-cells = <1>;
176 };
177 };
178
179 pcie4: pcie@4,0 {
180 device_type = "pci";
181 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
182 reg = <0x2000 0 0 0 0>;
183 #address-cells = <3>;
184 #size-cells = <2>;
185 interrupt-names = "intx";
186 interrupts-extended = <&mpic 61>;
187 #interrupt-cells = <1>;
188 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
189 0x81000000 0 0 0x81000000 0x4 0 1 0>;
190 bus-range = <0x00 0xff>;
191 interrupt-map-mask = <0 0 0 7>;
192 interrupt-map = <0 0 0 1 &pcie4_intc 0>,
193 <0 0 0 2 &pcie4_intc 1>,
194 <0 0 0 3 &pcie4_intc 2>,
195 <0 0 0 4 &pcie4_intc 3>;
196 marvell,pcie-port = <0>;
197 marvell,pcie-lane = <3>;
198 clocks = <&gateclk 8>;
199 status = "disabled";
200
201 pcie4_intc: interrupt-controller {
202 interrupt-controller;
203 #interrupt-cells = <1>;
204 };
205 };
206
207 pcie5: pcie@5,0 {
208 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x2800 0 0 0 0>;
211 #address-cells = <3>;
212 #size-cells = <2>;
213 interrupt-names = "intx";
214 interrupts-extended = <&mpic 62>;
215 #interrupt-cells = <1>;
216 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
217 0x81000000 0 0 0x81000000 0x5 0 1 0>;
218 bus-range = <0x00 0xff>;
219 interrupt-map-mask = <0 0 0 7>;
220 interrupt-map = <0 0 0 1 &pcie5_intc 0>,
221 <0 0 0 2 &pcie5_intc 1>,
222 <0 0 0 3 &pcie5_intc 2>,
223 <0 0 0 4 &pcie5_intc 3>;
224 marvell,pcie-port = <1>;
225 marvell,pcie-lane = <0>;
226 clocks = <&gateclk 9>;
227 status = "disabled";
228
229 pcie5_intc: interrupt-controller {
230 interrupt-controller;
231 #interrupt-cells = <1>;
232 };
233 };
234
235 pcie6: pcie@6,0 {
236 device_type = "pci";
237 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
238 reg = <0x3000 0 0 0 0>;
239 #address-cells = <3>;
240 #size-cells = <2>;
241 interrupt-names = "intx";
242 interrupts-extended = <&mpic 63>;
243 #interrupt-cells = <1>;
244 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
245 0x81000000 0 0 0x81000000 0x6 0 1 0>;
246 bus-range = <0x00 0xff>;
247 interrupt-map-mask = <0 0 0 7>;
248 interrupt-map = <0 0 0 1 &pcie6_intc 0>,
249 <0 0 0 2 &pcie6_intc 1>,
250 <0 0 0 3 &pcie6_intc 2>,
251 <0 0 0 4 &pcie6_intc 3>;
252 marvell,pcie-port = <1>;
253 marvell,pcie-lane = <1>;
254 clocks = <&gateclk 10>;
255 status = "disabled";
256
257 pcie6_intc: interrupt-controller {
258 interrupt-controller;
259 #interrupt-cells = <1>;
260 };
261 };
262
263 pcie7: pcie@7,0 {
264 device_type = "pci";
265 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
266 reg = <0x3800 0 0 0 0>;
267 #address-cells = <3>;
268 #size-cells = <2>;
269 interrupt-names = "intx";
270 interrupts-extended = <&mpic 64>;
271 #interrupt-cells = <1>;
272 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
273 0x81000000 0 0 0x81000000 0x7 0 1 0>;
274 bus-range = <0x00 0xff>;
275 interrupt-map-mask = <0 0 0 7>;
276 interrupt-map = <0 0 0 1 &pcie7_intc 0>,
277 <0 0 0 2 &pcie7_intc 1>,
278 <0 0 0 3 &pcie7_intc 2>,
279 <0 0 0 4 &pcie7_intc 3>;
280 marvell,pcie-port = <1>;
281 marvell,pcie-lane = <2>;
282 clocks = <&gateclk 11>;
283 status = "disabled";
284
285 pcie7_intc: interrupt-controller {
286 interrupt-controller;
287 #interrupt-cells = <1>;
288 };
289 };
290
291 pcie8: pcie@8,0 {
292 device_type = "pci";
293 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
294 reg = <0x4000 0 0 0 0>;
295 #address-cells = <3>;
296 #size-cells = <2>;
297 interrupt-names = "intx";
298 interrupts-extended = <&mpic 65>;
299 #interrupt-cells = <1>;
300 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
301 0x81000000 0 0 0x81000000 0x8 0 1 0>;
302 bus-range = <0x00 0xff>;
303 interrupt-map-mask = <0 0 0 7>;
304 interrupt-map = <0 0 0 1 &pcie8_intc 0>,
305 <0 0 0 2 &pcie8_intc 1>,
306 <0 0 0 3 &pcie8_intc 2>,
307 <0 0 0 4 &pcie8_intc 3>;
308 marvell,pcie-port = <1>;
309 marvell,pcie-lane = <3>;
310 clocks = <&gateclk 12>;
311 status = "disabled";
312
313 pcie8_intc: interrupt-controller {
314 interrupt-controller;
315 #interrupt-cells = <1>;
316 };
317 };
318
319 pcie9: pcie@9,0 {
320 device_type = "pci";
321 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
322 reg = <0x4800 0 0 0 0>;
323 #address-cells = <3>;
324 #size-cells = <2>;
325 interrupt-names = "intx";
326 interrupts-extended = <&mpic 99>;
327 #interrupt-cells = <1>;
328 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
329 0x81000000 0 0 0x81000000 0x9 0 1 0>;
330 bus-range = <0x00 0xff>;
331 interrupt-map-mask = <0 0 0 7>;
332 interrupt-map = <0 0 0 1 &pcie9_intc 0>,
333 <0 0 0 2 &pcie9_intc 1>,
334 <0 0 0 3 &pcie9_intc 2>,
335 <0 0 0 4 &pcie9_intc 3>;
336 marvell,pcie-port = <2>;
337 marvell,pcie-lane = <0>;
338 clocks = <&gateclk 26>;
339 status = "disabled";
340
341 pcie9_intc: interrupt-controller {
342 interrupt-controller;
343 #interrupt-cells = <1>;
344 };
345 };
346 };
347
348 internal-regs {
349 gpio0: gpio@18100 {
350 compatible = "marvell,armada-370-gpio",
351 "marvell,orion-gpio";
352 reg = <0x18100 0x40>, <0x181c0 0x08>;
353 reg-names = "gpio", "pwm";
354 ngpios = <32>;
355 gpio-controller;
356 #gpio-cells = <2>;
357 #pwm-cells = <2>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 interrupts = <82>, <83>, <84>, <85>;
361 clocks = <&coreclk 0>;
362 };
363
364 gpio1: gpio@18140 {
365 compatible = "marvell,armada-370-gpio",
366 "marvell,orion-gpio";
367 reg = <0x18140 0x40>, <0x181c8 0x08>;
368 reg-names = "gpio", "pwm";
369 ngpios = <32>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 #pwm-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 interrupts = <87>, <88>, <89>, <90>;
376 clocks = <&coreclk 0>;
377 };
378
379 gpio2: gpio@18180 {
380 compatible = "marvell,armada-370-gpio",
381 "marvell,orion-gpio";
382 reg = <0x18180 0x40>;
383 ngpios = <3>;
384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
387 #interrupt-cells = <2>;
388 interrupts = <91>;
389 };
390
391 eth3: ethernet@34000 {
392 compatible = "marvell,armada-xp-neta";
393 reg = <0x34000 0x4000>;
394 interrupts = <14>;
395 clocks = <&gateclk 1>;
396 status = "disabled";
397 };
398 };
399 };
400};
401
402&pinctrl {
403 compatible = "marvell,mv78260-pinctrl";
404};
1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 *
12 * Contains definitions specific to the Armada XP MV78260 SoC that are not
13 * common to all Armada XP SoCs.
14 */
15
16#include "armada-xp.dtsi"
17
18/ {
19 model = "Marvell Armada XP MV78260 SoC";
20 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
21
22 aliases {
23 gpio0 = &gpio0;
24 gpio1 = &gpio1;
25 gpio2 = &gpio2;
26 eth3 = ð3;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 device_type = "cpu";
35 compatible = "marvell,sheeva-v7";
36 reg = <0>;
37 clocks = <&cpuclk 0>;
38 };
39
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "marvell,sheeva-v7";
43 reg = <1>;
44 clocks = <&cpuclk 1>;
45 };
46 };
47
48 soc {
49 /*
50 * MV78260 has 3 PCIe units Gen2.0: Two units can be
51 * configured as x4 or quad x1 lanes. One unit is
52 * x4 only.
53 */
54 pcie-controller {
55 compatible = "marvell,armada-xp-pcie";
56 status = "disabled";
57 device_type = "pci";
58
59 #address-cells = <3>;
60 #size-cells = <2>;
61
62 msi-parent = <&mpic>;
63 bus-range = <0x00 0xff>;
64
65 ranges =
66 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
67 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
68 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
69 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
70 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
71 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
72 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
73 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
74 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
75 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
76 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
77 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
78 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
79 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
80 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
81 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
82 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
83
84 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
85 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
86 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
87 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
88 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
89 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
90 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
91 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
92
93 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
94 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
95
96 pcie@1,0 {
97 device_type = "pci";
98 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
99 reg = <0x0800 0 0 0 0>;
100 #address-cells = <3>;
101 #size-cells = <2>;
102 #interrupt-cells = <1>;
103 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
104 0x81000000 0 0 0x81000000 0x1 0 1 0>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 58>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <0>;
109 clocks = <&gateclk 5>;
110 status = "disabled";
111 };
112
113 pcie@2,0 {
114 device_type = "pci";
115 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
116 reg = <0x1000 0 0 0 0>;
117 #address-cells = <3>;
118 #size-cells = <2>;
119 #interrupt-cells = <1>;
120 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
121 0x81000000 0 0 0x81000000 0x2 0 1 0>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &mpic 59>;
124 marvell,pcie-port = <0>;
125 marvell,pcie-lane = <1>;
126 clocks = <&gateclk 6>;
127 status = "disabled";
128 };
129
130 pcie@3,0 {
131 device_type = "pci";
132 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
133 reg = <0x1800 0 0 0 0>;
134 #address-cells = <3>;
135 #size-cells = <2>;
136 #interrupt-cells = <1>;
137 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
138 0x81000000 0 0 0x81000000 0x3 0 1 0>;
139 interrupt-map-mask = <0 0 0 0>;
140 interrupt-map = <0 0 0 0 &mpic 60>;
141 marvell,pcie-port = <0>;
142 marvell,pcie-lane = <2>;
143 clocks = <&gateclk 7>;
144 status = "disabled";
145 };
146
147 pcie@4,0 {
148 device_type = "pci";
149 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
150 reg = <0x2000 0 0 0 0>;
151 #address-cells = <3>;
152 #size-cells = <2>;
153 #interrupt-cells = <1>;
154 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
155 0x81000000 0 0 0x81000000 0x4 0 1 0>;
156 interrupt-map-mask = <0 0 0 0>;
157 interrupt-map = <0 0 0 0 &mpic 61>;
158 marvell,pcie-port = <0>;
159 marvell,pcie-lane = <3>;
160 clocks = <&gateclk 8>;
161 status = "disabled";
162 };
163
164 pcie@5,0 {
165 device_type = "pci";
166 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
167 reg = <0x2800 0 0 0 0>;
168 #address-cells = <3>;
169 #size-cells = <2>;
170 #interrupt-cells = <1>;
171 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
172 0x81000000 0 0 0x81000000 0x5 0 1 0>;
173 interrupt-map-mask = <0 0 0 0>;
174 interrupt-map = <0 0 0 0 &mpic 62>;
175 marvell,pcie-port = <1>;
176 marvell,pcie-lane = <0>;
177 clocks = <&gateclk 9>;
178 status = "disabled";
179 };
180
181 pcie@6,0 {
182 device_type = "pci";
183 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
184 reg = <0x3000 0 0 0 0>;
185 #address-cells = <3>;
186 #size-cells = <2>;
187 #interrupt-cells = <1>;
188 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
189 0x81000000 0 0 0x81000000 0x6 0 1 0>;
190 interrupt-map-mask = <0 0 0 0>;
191 interrupt-map = <0 0 0 0 &mpic 63>;
192 marvell,pcie-port = <1>;
193 marvell,pcie-lane = <1>;
194 clocks = <&gateclk 10>;
195 status = "disabled";
196 };
197
198 pcie@7,0 {
199 device_type = "pci";
200 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
201 reg = <0x3800 0 0 0 0>;
202 #address-cells = <3>;
203 #size-cells = <2>;
204 #interrupt-cells = <1>;
205 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
206 0x81000000 0 0 0x81000000 0x7 0 1 0>;
207 interrupt-map-mask = <0 0 0 0>;
208 interrupt-map = <0 0 0 0 &mpic 64>;
209 marvell,pcie-port = <1>;
210 marvell,pcie-lane = <2>;
211 clocks = <&gateclk 11>;
212 status = "disabled";
213 };
214
215 pcie@8,0 {
216 device_type = "pci";
217 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
218 reg = <0x4000 0 0 0 0>;
219 #address-cells = <3>;
220 #size-cells = <2>;
221 #interrupt-cells = <1>;
222 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
223 0x81000000 0 0 0x81000000 0x8 0 1 0>;
224 interrupt-map-mask = <0 0 0 0>;
225 interrupt-map = <0 0 0 0 &mpic 65>;
226 marvell,pcie-port = <1>;
227 marvell,pcie-lane = <3>;
228 clocks = <&gateclk 12>;
229 status = "disabled";
230 };
231
232 pcie@9,0 {
233 device_type = "pci";
234 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
235 reg = <0x4800 0 0 0 0>;
236 #address-cells = <3>;
237 #size-cells = <2>;
238 #interrupt-cells = <1>;
239 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
240 0x81000000 0 0 0x81000000 0x9 0 1 0>;
241 interrupt-map-mask = <0 0 0 0>;
242 interrupt-map = <0 0 0 0 &mpic 99>;
243 marvell,pcie-port = <2>;
244 marvell,pcie-lane = <0>;
245 clocks = <&gateclk 26>;
246 status = "disabled";
247 };
248 };
249
250 internal-regs {
251 pinctrl {
252 compatible = "marvell,mv78260-pinctrl";
253 reg = <0x18000 0x38>;
254
255 sdio_pins: sdio-pins {
256 marvell,pins = "mpp30", "mpp31", "mpp32",
257 "mpp33", "mpp34", "mpp35";
258 marvell,function = "sd0";
259 };
260 };
261
262 gpio0: gpio@18100 {
263 compatible = "marvell,orion-gpio";
264 reg = <0x18100 0x40>;
265 ngpios = <32>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
270 interrupts = <82>, <83>, <84>, <85>;
271 };
272
273 gpio1: gpio@18140 {
274 compatible = "marvell,orion-gpio";
275 reg = <0x18140 0x40>;
276 ngpios = <32>;
277 gpio-controller;
278 #gpio-cells = <2>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 interrupts = <87>, <88>, <89>, <90>;
282 };
283
284 gpio2: gpio@18180 {
285 compatible = "marvell,orion-gpio";
286 reg = <0x18180 0x40>;
287 ngpios = <3>;
288 gpio-controller;
289 #gpio-cells = <2>;
290 interrupt-controller;
291 #interrupt-cells = <2>;
292 interrupts = <91>;
293 };
294
295 eth3: ethernet@34000 {
296 compatible = "marvell,armada-370-neta";
297 reg = <0x34000 0x4000>;
298 interrupts = <14>;
299 clocks = <&gateclk 1>;
300 status = "disabled";
301 };
302 };
303 };
304};