Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for AM33XX SoC
4 *
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/pinctrl/am33xx.h>
11#include <dt-bindings/clock/am3.h>
12
13/ {
14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18 chosen { };
19
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
30 d-can0 = &dcan0;
31 d-can1 = &dcan1;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
36 ethernet0 = &cpsw_port1;
37 ethernet1 = &cpsw_port2;
38 spi0 = &spi0;
39 spi1 = &spi1;
40 mmc0 = &mmc1;
41 mmc1 = &mmc2;
42 mmc2 = &mmc3;
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48 cpu@0 {
49 compatible = "arm,cortex-a8";
50 enable-method = "ti,am3352";
51 device_type = "cpu";
52 reg = <0>;
53
54 operating-points-v2 = <&cpu0_opp_table>;
55
56 clocks = <&dpll_mpu_ck>;
57 clock-names = "cpu";
58
59 clock-latency = <300000>; /* From omap-cpufreq driver */
60 cpu-idle-states = <&mpu_gate>;
61 };
62
63 idle-states {
64 mpu_gate: mpu_gate {
65 compatible = "arm,idle-state";
66 entry-latency-us = <40>;
67 exit-latency-us = <90>;
68 min-residency-us = <300>;
69 ti,idle-wkup-m3;
70 };
71 };
72 };
73
74 cpu0_opp_table: opp-table {
75 compatible = "operating-points-v2-ti-cpu";
76 syscon = <&scm_conf>;
77
78 /*
79 * The three following nodes are marked with opp-suspend
80 * because the can not be enabled simultaneously on a
81 * single SoC.
82 */
83 opp50-300000000 {
84 opp-hz = /bits/ 64 <300000000>;
85 opp-microvolt = <950000 931000 969000>;
86 opp-supported-hw = <0x06 0x0010>;
87 opp-suspend;
88 };
89
90 opp100-275000000 {
91 opp-hz = /bits/ 64 <275000000>;
92 opp-microvolt = <1100000 1078000 1122000>;
93 opp-supported-hw = <0x01 0x00FF>;
94 opp-suspend;
95 };
96
97 opp100-300000000 {
98 opp-hz = /bits/ 64 <300000000>;
99 opp-microvolt = <1100000 1078000 1122000>;
100 opp-supported-hw = <0x06 0x0020>;
101 opp-suspend;
102 };
103
104 opp100-500000000 {
105 opp-hz = /bits/ 64 <500000000>;
106 opp-microvolt = <1100000 1078000 1122000>;
107 opp-supported-hw = <0x01 0xFFFF>;
108 };
109
110 opp100-600000000 {
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <1100000 1078000 1122000>;
113 opp-supported-hw = <0x06 0x0040>;
114 };
115
116 opp120-600000000 {
117 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <1200000 1176000 1224000>;
119 opp-supported-hw = <0x01 0xFFFF>;
120 };
121
122 opp120-720000000 {
123 opp-hz = /bits/ 64 <720000000>;
124 opp-microvolt = <1200000 1176000 1224000>;
125 opp-supported-hw = <0x06 0x0080>;
126 };
127
128 oppturbo-720000000 {
129 opp-hz = /bits/ 64 <720000000>;
130 opp-microvolt = <1260000 1234800 1285200>;
131 opp-supported-hw = <0x01 0xFFFF>;
132 };
133
134 oppturbo-800000000 {
135 opp-hz = /bits/ 64 <800000000>;
136 opp-microvolt = <1260000 1234800 1285200>;
137 opp-supported-hw = <0x06 0x0100>;
138 };
139
140 oppnitro-1000000000 {
141 opp-hz = /bits/ 64 <1000000000>;
142 opp-microvolt = <1325000 1298500 1351500>;
143 opp-supported-hw = <0x04 0x0200>;
144 };
145 };
146
147 target-module@4b000000 {
148 compatible = "ti,sysc-omap4-simple", "ti,sysc";
149 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
150 clock-names = "fck";
151 ti,no-idle;
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0x0 0x4b000000 0x1000000>;
155
156 target-module@140000 {
157 compatible = "ti,sysc-omap4-simple", "ti,sysc";
158 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
159 clock-names = "fck";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 ranges = <0x0 0x140000 0xec0000>;
163
164 pmu@0 {
165 compatible = "arm,cortex-a8-pmu";
166 interrupts = <3>;
167 };
168 };
169 };
170
171 /*
172 * The soc node represents the soc top level view. It is used for IPs
173 * that are not memory mapped in the MPU view or for the MPU itself.
174 */
175 soc {
176 compatible = "ti,omap-infra";
177 };
178
179 /*
180 * XXX: Use a flat representation of the AM33XX interconnect.
181 * The real AM33XX interconnect network is quite complex. Since
182 * it will not bring real advantage to represent that in DT
183 * for the moment, just use a fake OCP bus entry to represent
184 * the whole bus hierarchy.
185 */
186 ocp: ocp {
187 compatible = "simple-pm-bus";
188 power-domains = <&prm_per>;
189 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
190 clock-names = "fck";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges;
194
195 l4_wkup: interconnect@44c00000 {
196 };
197 l4_per: interconnect@48000000 {
198 };
199 l4_fw: interconnect@47c00000 {
200 };
201 l4_fast: interconnect@4a000000 {
202 };
203 l4_mpuss: interconnect@4b140000 {
204 };
205
206 intc: interrupt-controller@48200000 {
207 compatible = "ti,am33xx-intc";
208 interrupt-controller;
209 #interrupt-cells = <1>;
210 reg = <0x48200000 0x1000>;
211 };
212
213 target-module@49000000 {
214 compatible = "ti,sysc-omap4", "ti,sysc";
215 reg = <0x49000000 0x4>;
216 reg-names = "rev";
217 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
218 clock-names = "fck";
219 #address-cells = <1>;
220 #size-cells = <1>;
221 ranges = <0x0 0x49000000 0x10000>;
222
223 edma: dma@0 {
224 compatible = "ti,edma3-tpcc";
225 reg = <0 0x10000>;
226 reg-names = "edma3_cc";
227 interrupts = <12 13 14>;
228 interrupt-names = "edma3_ccint", "edma3_mperr",
229 "edma3_ccerrint";
230 dma-requests = <64>;
231 #dma-cells = <2>;
232
233 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
234 <&edma_tptc2 0>;
235
236 ti,edma-memcpy-channels = <20 21>;
237 };
238 };
239
240 target-module@49800000 {
241 compatible = "ti,sysc-omap4", "ti,sysc";
242 reg = <0x49800000 0x4>,
243 <0x49800010 0x4>;
244 reg-names = "rev", "sysc";
245 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
246 ti,sysc-midle = <SYSC_IDLE_FORCE>;
247 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
248 <SYSC_IDLE_SMART>;
249 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
250 clock-names = "fck";
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges = <0x0 0x49800000 0x100000>;
254
255 edma_tptc0: dma@0 {
256 compatible = "ti,edma3-tptc";
257 reg = <0 0x100000>;
258 interrupts = <112>;
259 interrupt-names = "edma3_tcerrint";
260 };
261 };
262
263 target-module@49900000 {
264 compatible = "ti,sysc-omap4", "ti,sysc";
265 reg = <0x49900000 0x4>,
266 <0x49900010 0x4>;
267 reg-names = "rev", "sysc";
268 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
269 ti,sysc-midle = <SYSC_IDLE_FORCE>;
270 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
271 <SYSC_IDLE_SMART>;
272 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
273 clock-names = "fck";
274 #address-cells = <1>;
275 #size-cells = <1>;
276 ranges = <0x0 0x49900000 0x100000>;
277
278 edma_tptc1: dma@0 {
279 compatible = "ti,edma3-tptc";
280 reg = <0 0x100000>;
281 interrupts = <113>;
282 interrupt-names = "edma3_tcerrint";
283 };
284 };
285
286 target-module@49a00000 {
287 compatible = "ti,sysc-omap4", "ti,sysc";
288 reg = <0x49a00000 0x4>,
289 <0x49a00010 0x4>;
290 reg-names = "rev", "sysc";
291 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
292 ti,sysc-midle = <SYSC_IDLE_FORCE>;
293 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
294 <SYSC_IDLE_SMART>;
295 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
296 clock-names = "fck";
297 #address-cells = <1>;
298 #size-cells = <1>;
299 ranges = <0x0 0x49a00000 0x100000>;
300
301 edma_tptc2: dma@0 {
302 compatible = "ti,edma3-tptc";
303 reg = <0 0x100000>;
304 interrupts = <114>;
305 interrupt-names = "edma3_tcerrint";
306 };
307 };
308
309 target-module@47810000 {
310 compatible = "ti,sysc-omap2", "ti,sysc";
311 reg = <0x478102fc 0x4>,
312 <0x47810110 0x4>,
313 <0x47810114 0x4>;
314 reg-names = "rev", "sysc", "syss";
315 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
316 SYSC_OMAP2_ENAWAKEUP |
317 SYSC_OMAP2_SOFTRESET |
318 SYSC_OMAP2_AUTOIDLE)>;
319 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
320 <SYSC_IDLE_NO>,
321 <SYSC_IDLE_SMART>;
322 ti,syss-mask = <1>;
323 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
324 clock-names = "fck";
325 #address-cells = <1>;
326 #size-cells = <1>;
327 ranges = <0x0 0x47810000 0x1000>;
328
329 mmc3: mmc@0 {
330 compatible = "ti,am335-sdhci";
331 ti,needs-special-reset;
332 interrupts = <29>;
333 reg = <0x0 0x1000>;
334 status = "disabled";
335 };
336 };
337
338 usb: target-module@47400000 {
339 compatible = "ti,sysc-omap4", "ti,sysc";
340 reg = <0x47400000 0x4>,
341 <0x47400010 0x4>;
342 reg-names = "rev", "sysc";
343 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
344 SYSC_OMAP4_SOFTRESET)>;
345 ti,sysc-midle = <SYSC_IDLE_FORCE>,
346 <SYSC_IDLE_NO>,
347 <SYSC_IDLE_SMART>;
348 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
349 <SYSC_IDLE_NO>,
350 <SYSC_IDLE_SMART>,
351 <SYSC_IDLE_SMART_WKUP>;
352 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
353 clock-names = "fck";
354 #address-cells = <1>;
355 #size-cells = <1>;
356 ranges = <0x0 0x47400000 0x8000>;
357
358 usb0_phy: usb-phy@1300 {
359 compatible = "ti,am335x-usb-phy";
360 reg = <0x1300 0x100>;
361 reg-names = "phy";
362 ti,ctrl_mod = <&usb_ctrl_mod>;
363 #phy-cells = <0>;
364 };
365
366 usb0: usb@1400 {
367 compatible = "ti,musb-am33xx";
368 reg = <0x1400 0x400>,
369 <0x1000 0x200>;
370 reg-names = "mc", "control";
371
372 interrupts = <18>;
373 interrupt-names = "mc";
374 dr_mode = "otg";
375 mentor,multipoint = <1>;
376 mentor,num-eps = <16>;
377 mentor,ram-bits = <12>;
378 mentor,power = <500>;
379 phys = <&usb0_phy>;
380
381 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
382 &cppi41dma 2 0 &cppi41dma 3 0
383 &cppi41dma 4 0 &cppi41dma 5 0
384 &cppi41dma 6 0 &cppi41dma 7 0
385 &cppi41dma 8 0 &cppi41dma 9 0
386 &cppi41dma 10 0 &cppi41dma 11 0
387 &cppi41dma 12 0 &cppi41dma 13 0
388 &cppi41dma 14 0 &cppi41dma 0 1
389 &cppi41dma 1 1 &cppi41dma 2 1
390 &cppi41dma 3 1 &cppi41dma 4 1
391 &cppi41dma 5 1 &cppi41dma 6 1
392 &cppi41dma 7 1 &cppi41dma 8 1
393 &cppi41dma 9 1 &cppi41dma 10 1
394 &cppi41dma 11 1 &cppi41dma 12 1
395 &cppi41dma 13 1 &cppi41dma 14 1>;
396 dma-names =
397 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
398 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
399 "rx14", "rx15",
400 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
401 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
402 "tx14", "tx15";
403 };
404
405 usb1_phy: usb-phy@1b00 {
406 compatible = "ti,am335x-usb-phy";
407 reg = <0x1b00 0x100>;
408 reg-names = "phy";
409 ti,ctrl_mod = <&usb_ctrl_mod>;
410 #phy-cells = <0>;
411 };
412
413 usb1: usb@1800 {
414 compatible = "ti,musb-am33xx";
415 reg = <0x1c00 0x400>,
416 <0x1800 0x200>;
417 reg-names = "mc", "control";
418 interrupts = <19>;
419 interrupt-names = "mc";
420 dr_mode = "otg";
421 mentor,multipoint = <1>;
422 mentor,num-eps = <16>;
423 mentor,ram-bits = <12>;
424 mentor,power = <500>;
425 phys = <&usb1_phy>;
426
427 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
428 &cppi41dma 17 0 &cppi41dma 18 0
429 &cppi41dma 19 0 &cppi41dma 20 0
430 &cppi41dma 21 0 &cppi41dma 22 0
431 &cppi41dma 23 0 &cppi41dma 24 0
432 &cppi41dma 25 0 &cppi41dma 26 0
433 &cppi41dma 27 0 &cppi41dma 28 0
434 &cppi41dma 29 0 &cppi41dma 15 1
435 &cppi41dma 16 1 &cppi41dma 17 1
436 &cppi41dma 18 1 &cppi41dma 19 1
437 &cppi41dma 20 1 &cppi41dma 21 1
438 &cppi41dma 22 1 &cppi41dma 23 1
439 &cppi41dma 24 1 &cppi41dma 25 1
440 &cppi41dma 26 1 &cppi41dma 27 1
441 &cppi41dma 28 1 &cppi41dma 29 1>;
442 dma-names =
443 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
444 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
445 "rx14", "rx15",
446 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
447 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
448 "tx14", "tx15";
449 };
450
451 cppi41dma: dma-controller@2000 {
452 compatible = "ti,am3359-cppi41";
453 reg = <0x0000 0x1000>,
454 <0x2000 0x1000>,
455 <0x3000 0x1000>,
456 <0x4000 0x4000>;
457 reg-names = "glue", "controller", "scheduler", "queuemgr";
458 interrupts = <17>;
459 interrupt-names = "glue";
460 #dma-cells = <2>;
461 /* For backwards compatibility: */
462 #dma-channels = <30>;
463 dma-channels = <30>;
464 #dma-requests = <256>;
465 dma-requests = <256>;
466 };
467 };
468
469 target-module@40300000 {
470 compatible = "ti,sysc-omap4-simple", "ti,sysc";
471 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
472 clock-names = "fck";
473 ti,no-idle;
474 #address-cells = <1>;
475 #size-cells = <1>;
476 ranges = <0 0x40300000 0x10000>;
477
478 ocmcram: sram@0 {
479 compatible = "mmio-sram";
480 reg = <0 0x10000>; /* 64k */
481 ranges = <0 0 0x10000>;
482 #address-cells = <1>;
483 #size-cells = <1>;
484
485 pm_sram_code: pm-code-sram@0 {
486 compatible = "ti,sram";
487 reg = <0x0 0x1000>;
488 protect-exec;
489 };
490
491 pm_sram_data: pm-data-sram@1000 {
492 compatible = "ti,sram";
493 reg = <0x1000 0x1000>;
494 pool;
495 };
496 };
497 };
498
499 target-module@4c000000 {
500 compatible = "ti,sysc-omap4-simple", "ti,sysc";
501 reg = <0x4c000000 0x4>;
502 reg-names = "rev";
503 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
504 clock-names = "fck";
505 ti,no-idle;
506 #address-cells = <1>;
507 #size-cells = <1>;
508 ranges = <0x0 0x4c000000 0x1000000>;
509
510 emif: emif@0 {
511 compatible = "ti,emif-am3352";
512 reg = <0 0x1000000>;
513 interrupts = <101>;
514 sram = <&pm_sram_code
515 &pm_sram_data>;
516 };
517 };
518
519 target-module@50000000 {
520 compatible = "ti,sysc-omap2", "ti,sysc";
521 reg = <0x50000000 4>,
522 <0x50000010 4>,
523 <0x50000014 4>;
524 reg-names = "rev", "sysc", "syss";
525 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
526 <SYSC_IDLE_NO>,
527 <SYSC_IDLE_SMART>;
528 ti,syss-mask = <1>;
529 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
530 clock-names = "fck";
531 #address-cells = <1>;
532 #size-cells = <1>;
533 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
534 <0x00000000 0x00000000 0x40000000>; /* data */
535
536 gpmc: gpmc@50000000 {
537 compatible = "ti,am3352-gpmc";
538 reg = <0x50000000 0x2000>;
539 interrupts = <100>;
540 dmas = <&edma 52 0>;
541 dma-names = "rxtx";
542 gpmc,num-cs = <7>;
543 gpmc,num-waitpins = <2>;
544 #address-cells = <2>;
545 #size-cells = <1>;
546 interrupt-controller;
547 #interrupt-cells = <2>;
548 gpio-controller;
549 #gpio-cells = <2>;
550 status = "disabled";
551 };
552 };
553
554 sham_target: target-module@53100000 {
555 compatible = "ti,sysc-omap3-sham", "ti,sysc";
556 reg = <0x53100100 0x4>,
557 <0x53100110 0x4>,
558 <0x53100114 0x4>;
559 reg-names = "rev", "sysc", "syss";
560 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
561 SYSC_OMAP2_AUTOIDLE)>;
562 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
563 <SYSC_IDLE_NO>,
564 <SYSC_IDLE_SMART>;
565 ti,syss-mask = <1>;
566 /* Domains (P, C): per_pwrdm, l3_clkdm */
567 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
568 clock-names = "fck";
569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges = <0x0 0x53100000 0x1000>;
572
573 sham: sham@0 {
574 compatible = "ti,omap4-sham";
575 reg = <0 0x200>;
576 interrupts = <109>;
577 dmas = <&edma 36 0>;
578 dma-names = "rx";
579 };
580 };
581
582 aes_target: target-module@53500000 {
583 compatible = "ti,sysc-omap2", "ti,sysc";
584 reg = <0x53500080 0x4>,
585 <0x53500084 0x4>,
586 <0x53500088 0x4>;
587 reg-names = "rev", "sysc", "syss";
588 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
589 SYSC_OMAP2_AUTOIDLE)>;
590 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
591 <SYSC_IDLE_NO>,
592 <SYSC_IDLE_SMART>,
593 <SYSC_IDLE_SMART_WKUP>;
594 ti,syss-mask = <1>;
595 /* Domains (P, C): per_pwrdm, l3_clkdm */
596 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
597 clock-names = "fck";
598 #address-cells = <1>;
599 #size-cells = <1>;
600 ranges = <0x0 0x53500000 0x1000>;
601
602 aes: aes@0 {
603 compatible = "ti,omap4-aes";
604 reg = <0 0xa0>;
605 interrupts = <103>;
606 dmas = <&edma 6 0>,
607 <&edma 5 0>;
608 dma-names = "tx", "rx";
609 };
610 };
611
612 target-module@56000000 {
613 compatible = "ti,sysc-omap4", "ti,sysc";
614 reg = <0x5600fe00 0x4>,
615 <0x5600fe10 0x4>;
616 reg-names = "rev", "sysc";
617 ti,sysc-midle = <SYSC_IDLE_FORCE>,
618 <SYSC_IDLE_NO>,
619 <SYSC_IDLE_SMART>;
620 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
621 <SYSC_IDLE_NO>,
622 <SYSC_IDLE_SMART>;
623 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
624 clock-names = "fck";
625 power-domains = <&prm_gfx>;
626 resets = <&prm_gfx 0>;
627 reset-names = "rstctrl";
628 #address-cells = <1>;
629 #size-cells = <1>;
630 ranges = <0 0x56000000 0x1000000>;
631
632 /*
633 * Closed source PowerVR driver, no child device
634 * binding or driver in mainline
635 */
636 };
637 };
638};
639
640#include "am33xx-l4.dtsi"
641#include "am33xx-clocks.dtsi"
642
643&prcm {
644 prm_per: prm@c00 {
645 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
646 reg = <0xc00 0x100>;
647 #reset-cells = <1>;
648 #power-domain-cells = <0>;
649 };
650
651 prm_wkup: prm@d00 {
652 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
653 reg = <0xd00 0x100>;
654 #reset-cells = <1>;
655 #power-domain-cells = <0>;
656 };
657
658 prm_mpu: prm@e00 {
659 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
660 reg = <0xe00 0x100>;
661 #power-domain-cells = <0>;
662 };
663
664 prm_device: prm@f00 {
665 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
666 reg = <0xf00 0x100>;
667 #reset-cells = <1>;
668 };
669
670 prm_rtc: prm@1000 {
671 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
672 reg = <0x1000 0x100>;
673 #power-domain-cells = <0>;
674 };
675
676 prm_gfx: prm@1100 {
677 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
678 reg = <0x1100 0x100>;
679 #power-domain-cells = <0>;
680 #reset-cells = <1>;
681 };
682
683 prm_cefuse: prm@1200 {
684 compatible = "ti,am3-prm-inst", "ti,omap-prm-inst";
685 reg = <0x1200 0x100>;
686 #power-domain-cells = <0>;
687 };
688};
689
690/* Preferred always-on timer for clocksource */
691&timer1_target {
692 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
693 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
694 clock-names = "fck", "ick";
695 ti,no-reset-on-init;
696 ti,no-idle;
697 timer@0 {
698 assigned-clocks = <&timer1_fck>;
699 assigned-clock-parents = <&sys_clkin_ck>;
700 };
701};
702
703/* Preferred timer for clockevent */
704&timer2_target {
705 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
706 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
707 clock-names = "fck", "ick";
708 ti,no-reset-on-init;
709 ti,no-idle;
710 timer@0 {
711 assigned-clocks = <&timer2_fck>;
712 assigned-clock-parents = <&sys_clkin_ck>;
713 };
714};
1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/am33xx.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 compatible = "ti,am33xx";
18 interrupt-parent = <&intc>;
19
20 aliases {
21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 cpu@0 {
44 compatible = "arm,cortex-a8";
45 device_type = "cpu";
46 reg = <0>;
47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
65 clock-latency = <300000>; /* From omap-cpufreq driver */
66 };
67 };
68
69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
74 /*
75 * The soc node represents the soc top level view. It is used for IPs
76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
86 am33xx_pinmux: pinmux@44e10800 {
87 compatible = "pinctrl-single";
88 reg = <0x44e10800 0x0238>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-single,register-width = <32>;
92 pinctrl-single,function-mask = <0x7f>;
93 };
94
95 /*
96 * XXX: Use a flat representation of the AM33XX interconnect.
97 * The real AM33XX interconnect network is quite complex. Since
98 * it will not bring real advantage to represent that in DT
99 * for the moment, just use a fake OCP bus entry to represent
100 * the whole bus hierarchy.
101 */
102 ocp {
103 compatible = "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 ranges;
107 ti,hwmods = "l3_main";
108
109 prcm: prcm@44e00000 {
110 compatible = "ti,am3-prcm";
111 reg = <0x44e00000 0x4000>;
112
113 prcm_clocks: clocks {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 };
117
118 prcm_clockdomains: clockdomains {
119 };
120 };
121
122 scrm: scrm@44e10000 {
123 compatible = "ti,am3-scrm";
124 reg = <0x44e10000 0x2000>;
125
126 scrm_clocks: clocks {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 };
130
131 scrm_clockdomains: clockdomains {
132 };
133 };
134
135 intc: interrupt-controller@48200000 {
136 compatible = "ti,omap2-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 ti,intc-size = <128>;
140 reg = <0x48200000 0x1000>;
141 };
142
143 edma: edma@49000000 {
144 compatible = "ti,edma3";
145 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
146 reg = <0x49000000 0x10000>,
147 <0x44e10f90 0x40>;
148 interrupts = <12 13 14>;
149 #dma-cells = <1>;
150 dma-channels = <64>;
151 ti,edma-regions = <4>;
152 ti,edma-slots = <256>;
153 };
154
155 gpio0: gpio@44e07000 {
156 compatible = "ti,omap4-gpio";
157 ti,hwmods = "gpio1";
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
161 #interrupt-cells = <2>;
162 reg = <0x44e07000 0x1000>;
163 interrupts = <96>;
164 };
165
166 gpio1: gpio@4804c000 {
167 compatible = "ti,omap4-gpio";
168 ti,hwmods = "gpio2";
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
173 reg = <0x4804c000 0x1000>;
174 interrupts = <98>;
175 };
176
177 gpio2: gpio@481ac000 {
178 compatible = "ti,omap4-gpio";
179 ti,hwmods = "gpio3";
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 reg = <0x481ac000 0x1000>;
185 interrupts = <32>;
186 };
187
188 gpio3: gpio@481ae000 {
189 compatible = "ti,omap4-gpio";
190 ti,hwmods = "gpio4";
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 reg = <0x481ae000 0x1000>;
196 interrupts = <62>;
197 };
198
199 uart0: serial@44e09000 {
200 compatible = "ti,omap3-uart";
201 ti,hwmods = "uart1";
202 clock-frequency = <48000000>;
203 reg = <0x44e09000 0x2000>;
204 interrupts = <72>;
205 status = "disabled";
206 };
207
208 uart1: serial@48022000 {
209 compatible = "ti,omap3-uart";
210 ti,hwmods = "uart2";
211 clock-frequency = <48000000>;
212 reg = <0x48022000 0x2000>;
213 interrupts = <73>;
214 status = "disabled";
215 };
216
217 uart2: serial@48024000 {
218 compatible = "ti,omap3-uart";
219 ti,hwmods = "uart3";
220 clock-frequency = <48000000>;
221 reg = <0x48024000 0x2000>;
222 interrupts = <74>;
223 status = "disabled";
224 };
225
226 uart3: serial@481a6000 {
227 compatible = "ti,omap3-uart";
228 ti,hwmods = "uart4";
229 clock-frequency = <48000000>;
230 reg = <0x481a6000 0x2000>;
231 interrupts = <44>;
232 status = "disabled";
233 };
234
235 uart4: serial@481a8000 {
236 compatible = "ti,omap3-uart";
237 ti,hwmods = "uart5";
238 clock-frequency = <48000000>;
239 reg = <0x481a8000 0x2000>;
240 interrupts = <45>;
241 status = "disabled";
242 };
243
244 uart5: serial@481aa000 {
245 compatible = "ti,omap3-uart";
246 ti,hwmods = "uart6";
247 clock-frequency = <48000000>;
248 reg = <0x481aa000 0x2000>;
249 interrupts = <46>;
250 status = "disabled";
251 };
252
253 i2c0: i2c@44e0b000 {
254 compatible = "ti,omap4-i2c";
255 #address-cells = <1>;
256 #size-cells = <0>;
257 ti,hwmods = "i2c1";
258 reg = <0x44e0b000 0x1000>;
259 interrupts = <70>;
260 status = "disabled";
261 };
262
263 i2c1: i2c@4802a000 {
264 compatible = "ti,omap4-i2c";
265 #address-cells = <1>;
266 #size-cells = <0>;
267 ti,hwmods = "i2c2";
268 reg = <0x4802a000 0x1000>;
269 interrupts = <71>;
270 status = "disabled";
271 };
272
273 i2c2: i2c@4819c000 {
274 compatible = "ti,omap4-i2c";
275 #address-cells = <1>;
276 #size-cells = <0>;
277 ti,hwmods = "i2c3";
278 reg = <0x4819c000 0x1000>;
279 interrupts = <30>;
280 status = "disabled";
281 };
282
283 mmc1: mmc@48060000 {
284 compatible = "ti,omap4-hsmmc";
285 ti,hwmods = "mmc1";
286 ti,dual-volt;
287 ti,needs-special-reset;
288 ti,needs-special-hs-handling;
289 dmas = <&edma 24
290 &edma 25>;
291 dma-names = "tx", "rx";
292 interrupts = <64>;
293 interrupt-parent = <&intc>;
294 reg = <0x48060000 0x1000>;
295 status = "disabled";
296 };
297
298 mmc2: mmc@481d8000 {
299 compatible = "ti,omap4-hsmmc";
300 ti,hwmods = "mmc2";
301 ti,needs-special-reset;
302 dmas = <&edma 2
303 &edma 3>;
304 dma-names = "tx", "rx";
305 interrupts = <28>;
306 interrupt-parent = <&intc>;
307 reg = <0x481d8000 0x1000>;
308 status = "disabled";
309 };
310
311 mmc3: mmc@47810000 {
312 compatible = "ti,omap4-hsmmc";
313 ti,hwmods = "mmc3";
314 ti,needs-special-reset;
315 interrupts = <29>;
316 interrupt-parent = <&intc>;
317 reg = <0x47810000 0x1000>;
318 status = "disabled";
319 };
320
321 hwspinlock: spinlock@480ca000 {
322 compatible = "ti,omap4-hwspinlock";
323 reg = <0x480ca000 0x1000>;
324 ti,hwmods = "spinlock";
325 #hwlock-cells = <1>;
326 };
327
328 wdt2: wdt@44e35000 {
329 compatible = "ti,omap3-wdt";
330 ti,hwmods = "wd_timer2";
331 reg = <0x44e35000 0x1000>;
332 interrupts = <91>;
333 };
334
335 dcan0: d_can@481cc000 {
336 compatible = "bosch,d_can";
337 ti,hwmods = "d_can0";
338 reg = <0x481cc000 0x2000
339 0x44e10644 0x4>;
340 interrupts = <52>;
341 status = "disabled";
342 };
343
344 dcan1: d_can@481d0000 {
345 compatible = "bosch,d_can";
346 ti,hwmods = "d_can1";
347 reg = <0x481d0000 0x2000
348 0x44e10644 0x4>;
349 interrupts = <55>;
350 status = "disabled";
351 };
352
353 timer1: timer@44e31000 {
354 compatible = "ti,am335x-timer-1ms";
355 reg = <0x44e31000 0x400>;
356 interrupts = <67>;
357 ti,hwmods = "timer1";
358 ti,timer-alwon;
359 };
360
361 timer2: timer@48040000 {
362 compatible = "ti,am335x-timer";
363 reg = <0x48040000 0x400>;
364 interrupts = <68>;
365 ti,hwmods = "timer2";
366 };
367
368 timer3: timer@48042000 {
369 compatible = "ti,am335x-timer";
370 reg = <0x48042000 0x400>;
371 interrupts = <69>;
372 ti,hwmods = "timer3";
373 };
374
375 timer4: timer@48044000 {
376 compatible = "ti,am335x-timer";
377 reg = <0x48044000 0x400>;
378 interrupts = <92>;
379 ti,hwmods = "timer4";
380 ti,timer-pwm;
381 };
382
383 timer5: timer@48046000 {
384 compatible = "ti,am335x-timer";
385 reg = <0x48046000 0x400>;
386 interrupts = <93>;
387 ti,hwmods = "timer5";
388 ti,timer-pwm;
389 };
390
391 timer6: timer@48048000 {
392 compatible = "ti,am335x-timer";
393 reg = <0x48048000 0x400>;
394 interrupts = <94>;
395 ti,hwmods = "timer6";
396 ti,timer-pwm;
397 };
398
399 timer7: timer@4804a000 {
400 compatible = "ti,am335x-timer";
401 reg = <0x4804a000 0x400>;
402 interrupts = <95>;
403 ti,hwmods = "timer7";
404 ti,timer-pwm;
405 };
406
407 rtc: rtc@44e3e000 {
408 compatible = "ti,da830-rtc";
409 reg = <0x44e3e000 0x1000>;
410 interrupts = <75
411 76>;
412 ti,hwmods = "rtc";
413 };
414
415 spi0: spi@48030000 {
416 compatible = "ti,omap4-mcspi";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 reg = <0x48030000 0x400>;
420 interrupts = <65>;
421 ti,spi-num-cs = <2>;
422 ti,hwmods = "spi0";
423 dmas = <&edma 16
424 &edma 17
425 &edma 18
426 &edma 19>;
427 dma-names = "tx0", "rx0", "tx1", "rx1";
428 status = "disabled";
429 };
430
431 spi1: spi@481a0000 {
432 compatible = "ti,omap4-mcspi";
433 #address-cells = <1>;
434 #size-cells = <0>;
435 reg = <0x481a0000 0x400>;
436 interrupts = <125>;
437 ti,spi-num-cs = <2>;
438 ti,hwmods = "spi1";
439 dmas = <&edma 42
440 &edma 43
441 &edma 44
442 &edma 45>;
443 dma-names = "tx0", "rx0", "tx1", "rx1";
444 status = "disabled";
445 };
446
447 usb: usb@47400000 {
448 compatible = "ti,am33xx-usb";
449 reg = <0x47400000 0x1000>;
450 ranges;
451 #address-cells = <1>;
452 #size-cells = <1>;
453 ti,hwmods = "usb_otg_hs";
454 status = "disabled";
455
456 usb_ctrl_mod: control@44e10620 {
457 compatible = "ti,am335x-usb-ctrl-module";
458 reg = <0x44e10620 0x10
459 0x44e10648 0x4>;
460 reg-names = "phy_ctrl", "wakeup";
461 status = "disabled";
462 };
463
464 usb0_phy: usb-phy@47401300 {
465 compatible = "ti,am335x-usb-phy";
466 reg = <0x47401300 0x100>;
467 reg-names = "phy";
468 status = "disabled";
469 ti,ctrl_mod = <&usb_ctrl_mod>;
470 };
471
472 usb0: usb@47401000 {
473 compatible = "ti,musb-am33xx";
474 status = "disabled";
475 reg = <0x47401400 0x400
476 0x47401000 0x200>;
477 reg-names = "mc", "control";
478
479 interrupts = <18>;
480 interrupt-names = "mc";
481 dr_mode = "otg";
482 mentor,multipoint = <1>;
483 mentor,num-eps = <16>;
484 mentor,ram-bits = <12>;
485 mentor,power = <500>;
486 phys = <&usb0_phy>;
487
488 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
489 &cppi41dma 2 0 &cppi41dma 3 0
490 &cppi41dma 4 0 &cppi41dma 5 0
491 &cppi41dma 6 0 &cppi41dma 7 0
492 &cppi41dma 8 0 &cppi41dma 9 0
493 &cppi41dma 10 0 &cppi41dma 11 0
494 &cppi41dma 12 0 &cppi41dma 13 0
495 &cppi41dma 14 0 &cppi41dma 0 1
496 &cppi41dma 1 1 &cppi41dma 2 1
497 &cppi41dma 3 1 &cppi41dma 4 1
498 &cppi41dma 5 1 &cppi41dma 6 1
499 &cppi41dma 7 1 &cppi41dma 8 1
500 &cppi41dma 9 1 &cppi41dma 10 1
501 &cppi41dma 11 1 &cppi41dma 12 1
502 &cppi41dma 13 1 &cppi41dma 14 1>;
503 dma-names =
504 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
505 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
506 "rx14", "rx15",
507 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
508 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
509 "tx14", "tx15";
510 };
511
512 usb1_phy: usb-phy@47401b00 {
513 compatible = "ti,am335x-usb-phy";
514 reg = <0x47401b00 0x100>;
515 reg-names = "phy";
516 status = "disabled";
517 ti,ctrl_mod = <&usb_ctrl_mod>;
518 };
519
520 usb1: usb@47401800 {
521 compatible = "ti,musb-am33xx";
522 status = "disabled";
523 reg = <0x47401c00 0x400
524 0x47401800 0x200>;
525 reg-names = "mc", "control";
526 interrupts = <19>;
527 interrupt-names = "mc";
528 dr_mode = "otg";
529 mentor,multipoint = <1>;
530 mentor,num-eps = <16>;
531 mentor,ram-bits = <12>;
532 mentor,power = <500>;
533 phys = <&usb1_phy>;
534
535 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
536 &cppi41dma 17 0 &cppi41dma 18 0
537 &cppi41dma 19 0 &cppi41dma 20 0
538 &cppi41dma 21 0 &cppi41dma 22 0
539 &cppi41dma 23 0 &cppi41dma 24 0
540 &cppi41dma 25 0 &cppi41dma 26 0
541 &cppi41dma 27 0 &cppi41dma 28 0
542 &cppi41dma 29 0 &cppi41dma 15 1
543 &cppi41dma 16 1 &cppi41dma 17 1
544 &cppi41dma 18 1 &cppi41dma 19 1
545 &cppi41dma 20 1 &cppi41dma 21 1
546 &cppi41dma 22 1 &cppi41dma 23 1
547 &cppi41dma 24 1 &cppi41dma 25 1
548 &cppi41dma 26 1 &cppi41dma 27 1
549 &cppi41dma 28 1 &cppi41dma 29 1>;
550 dma-names =
551 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
552 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
553 "rx14", "rx15",
554 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
555 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
556 "tx14", "tx15";
557 };
558
559 cppi41dma: dma-controller@47402000 {
560 compatible = "ti,am3359-cppi41";
561 reg = <0x47400000 0x1000
562 0x47402000 0x1000
563 0x47403000 0x1000
564 0x47404000 0x4000>;
565 reg-names = "glue", "controller", "scheduler", "queuemgr";
566 interrupts = <17>;
567 interrupt-names = "glue";
568 #dma-cells = <2>;
569 #dma-channels = <30>;
570 #dma-requests = <256>;
571 status = "disabled";
572 };
573 };
574
575 epwmss0: epwmss@48300000 {
576 compatible = "ti,am33xx-pwmss";
577 reg = <0x48300000 0x10>;
578 ti,hwmods = "epwmss0";
579 #address-cells = <1>;
580 #size-cells = <1>;
581 status = "disabled";
582 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
583 0x48300180 0x48300180 0x80 /* EQEP */
584 0x48300200 0x48300200 0x80>; /* EHRPWM */
585
586 ecap0: ecap@48300100 {
587 compatible = "ti,am33xx-ecap";
588 #pwm-cells = <3>;
589 reg = <0x48300100 0x80>;
590 interrupts = <31>;
591 interrupt-names = "ecap0";
592 ti,hwmods = "ecap0";
593 status = "disabled";
594 };
595
596 ehrpwm0: ehrpwm@48300200 {
597 compatible = "ti,am33xx-ehrpwm";
598 #pwm-cells = <3>;
599 reg = <0x48300200 0x80>;
600 ti,hwmods = "ehrpwm0";
601 status = "disabled";
602 };
603 };
604
605 epwmss1: epwmss@48302000 {
606 compatible = "ti,am33xx-pwmss";
607 reg = <0x48302000 0x10>;
608 ti,hwmods = "epwmss1";
609 #address-cells = <1>;
610 #size-cells = <1>;
611 status = "disabled";
612 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
613 0x48302180 0x48302180 0x80 /* EQEP */
614 0x48302200 0x48302200 0x80>; /* EHRPWM */
615
616 ecap1: ecap@48302100 {
617 compatible = "ti,am33xx-ecap";
618 #pwm-cells = <3>;
619 reg = <0x48302100 0x80>;
620 interrupts = <47>;
621 interrupt-names = "ecap1";
622 ti,hwmods = "ecap1";
623 status = "disabled";
624 };
625
626 ehrpwm1: ehrpwm@48302200 {
627 compatible = "ti,am33xx-ehrpwm";
628 #pwm-cells = <3>;
629 reg = <0x48302200 0x80>;
630 ti,hwmods = "ehrpwm1";
631 status = "disabled";
632 };
633 };
634
635 epwmss2: epwmss@48304000 {
636 compatible = "ti,am33xx-pwmss";
637 reg = <0x48304000 0x10>;
638 ti,hwmods = "epwmss2";
639 #address-cells = <1>;
640 #size-cells = <1>;
641 status = "disabled";
642 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
643 0x48304180 0x48304180 0x80 /* EQEP */
644 0x48304200 0x48304200 0x80>; /* EHRPWM */
645
646 ecap2: ecap@48304100 {
647 compatible = "ti,am33xx-ecap";
648 #pwm-cells = <3>;
649 reg = <0x48304100 0x80>;
650 interrupts = <61>;
651 interrupt-names = "ecap2";
652 ti,hwmods = "ecap2";
653 status = "disabled";
654 };
655
656 ehrpwm2: ehrpwm@48304200 {
657 compatible = "ti,am33xx-ehrpwm";
658 #pwm-cells = <3>;
659 reg = <0x48304200 0x80>;
660 ti,hwmods = "ehrpwm2";
661 status = "disabled";
662 };
663 };
664
665 mac: ethernet@4a100000 {
666 compatible = "ti,cpsw";
667 ti,hwmods = "cpgmac0";
668 cpdma_channels = <8>;
669 ale_entries = <1024>;
670 bd_ram_size = <0x2000>;
671 no_bd_ram = <0>;
672 rx_descs = <64>;
673 mac_control = <0x20>;
674 slaves = <2>;
675 active_slave = <0>;
676 cpts_clock_mult = <0x80000000>;
677 cpts_clock_shift = <29>;
678 reg = <0x4a100000 0x800
679 0x4a101200 0x100>;
680 #address-cells = <1>;
681 #size-cells = <1>;
682 interrupt-parent = <&intc>;
683 /*
684 * c0_rx_thresh_pend
685 * c0_rx_pend
686 * c0_tx_pend
687 * c0_misc_pend
688 */
689 interrupts = <40 41 42 43>;
690 ranges;
691
692 davinci_mdio: mdio@4a101000 {
693 compatible = "ti,davinci_mdio";
694 #address-cells = <1>;
695 #size-cells = <0>;
696 ti,hwmods = "davinci_mdio";
697 bus_freq = <1000000>;
698 reg = <0x4a101000 0x100>;
699 };
700
701 cpsw_emac0: slave@4a100200 {
702 /* Filled in by U-Boot */
703 mac-address = [ 00 00 00 00 00 00 ];
704 };
705
706 cpsw_emac1: slave@4a100300 {
707 /* Filled in by U-Boot */
708 mac-address = [ 00 00 00 00 00 00 ];
709 };
710
711 phy_sel: cpsw-phy-sel@44e10650 {
712 compatible = "ti,am3352-cpsw-phy-sel";
713 reg= <0x44e10650 0x4>;
714 reg-names = "gmii-sel";
715 };
716 };
717
718 ocmcram: ocmcram@40300000 {
719 compatible = "ti,am3352-ocmcram";
720 reg = <0x40300000 0x10000>;
721 ti,hwmods = "ocmcram";
722 };
723
724 wkup_m3: wkup_m3@44d00000 {
725 compatible = "ti,am3353-wkup-m3";
726 reg = <0x44d00000 0x4000 /* M3 UMEM */
727 0x44d80000 0x2000>; /* M3 DMEM */
728 ti,hwmods = "wkup_m3";
729 ti,no-reset-on-init;
730 };
731
732 elm: elm@48080000 {
733 compatible = "ti,am3352-elm";
734 reg = <0x48080000 0x2000>;
735 interrupts = <4>;
736 ti,hwmods = "elm";
737 status = "disabled";
738 };
739
740 lcdc: lcdc@4830e000 {
741 compatible = "ti,am33xx-tilcdc";
742 reg = <0x4830e000 0x1000>;
743 interrupt-parent = <&intc>;
744 interrupts = <36>;
745 ti,hwmods = "lcdc";
746 status = "disabled";
747 };
748
749 tscadc: tscadc@44e0d000 {
750 compatible = "ti,am3359-tscadc";
751 reg = <0x44e0d000 0x1000>;
752 interrupt-parent = <&intc>;
753 interrupts = <16>;
754 ti,hwmods = "adc_tsc";
755 status = "disabled";
756
757 tsc {
758 compatible = "ti,am3359-tsc";
759 };
760 am335x_adc: adc {
761 #io-channel-cells = <1>;
762 compatible = "ti,am3359-adc";
763 };
764 };
765
766 gpmc: gpmc@50000000 {
767 compatible = "ti,am3352-gpmc";
768 ti,hwmods = "gpmc";
769 ti,no-idle-on-init;
770 reg = <0x50000000 0x2000>;
771 interrupts = <100>;
772 gpmc,num-cs = <7>;
773 gpmc,num-waitpins = <2>;
774 #address-cells = <2>;
775 #size-cells = <1>;
776 status = "disabled";
777 };
778
779 sham: sham@53100000 {
780 compatible = "ti,omap4-sham";
781 ti,hwmods = "sham";
782 reg = <0x53100000 0x200>;
783 interrupts = <109>;
784 dmas = <&edma 36>;
785 dma-names = "rx";
786 };
787
788 aes: aes@53500000 {
789 compatible = "ti,omap4-aes";
790 ti,hwmods = "aes";
791 reg = <0x53500000 0xa0>;
792 interrupts = <103>;
793 dmas = <&edma 6>,
794 <&edma 5>;
795 dma-names = "tx", "rx";
796 };
797
798 mcasp0: mcasp@48038000 {
799 compatible = "ti,am33xx-mcasp-audio";
800 ti,hwmods = "mcasp0";
801 reg = <0x48038000 0x2000>,
802 <0x46000000 0x400000>;
803 reg-names = "mpu", "dat";
804 interrupts = <80>, <81>;
805 interrupt-names = "tx", "rx";
806 status = "disabled";
807 dmas = <&edma 8>,
808 <&edma 9>;
809 dma-names = "tx", "rx";
810 };
811
812 mcasp1: mcasp@4803C000 {
813 compatible = "ti,am33xx-mcasp-audio";
814 ti,hwmods = "mcasp1";
815 reg = <0x4803C000 0x2000>,
816 <0x46400000 0x400000>;
817 reg-names = "mpu", "dat";
818 interrupts = <82>, <83>;
819 interrupt-names = "tx", "rx";
820 status = "disabled";
821 dmas = <&edma 10>,
822 <&edma 11>;
823 dma-names = "tx", "rx";
824 };
825
826 rng: rng@48310000 {
827 compatible = "ti,omap4-rng";
828 ti,hwmods = "rng";
829 reg = <0x48310000 0x2000>;
830 interrupts = <111>;
831 };
832 };
833};
834
835/include/ "am33xx-clocks.dtsi"