1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
 
 
 
 
 4 */
 5/dts-v1/;
 6
 7/include/ "skeleton.dtsi"
 8
 9/ {
10	model = "snps,nsimosci";
11	compatible = "snps,nsimosci";
 
12	#address-cells = <1>;
13	#size-cells = <1>;
14	interrupt-parent = <&core_intc>;
15
16	chosen {
17		/* this is for console on PGU */
18		/* bootargs = "console=tty0 consoleblank=0"; */
19		/* this is for console on serial */
20		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24 print-fatal-signals=1";
21	};
22
23	aliases {
24		serial0 = &uart0;
25	};
26
 
 
 
 
 
27	fpga {
28		compatible = "simple-bus";
29		#address-cells = <1>;
30		#size-cells = <1>;
31
32		/* child and parent address space 1:1 mapped */
33		ranges;
34
35		core_clk: core_clk {
36			#clock-cells = <0>;
37			compatible = "fixed-clock";
38			clock-frequency = <20000000>;
39		};
40
41		core_intc: interrupt-controller {
42			compatible = "snps,arc700-intc";
43			interrupt-controller;
44			#interrupt-cells = <1>;
45		};
46
47		uart0: serial@f0000000 {
48			compatible = "ns8250";
49			reg = <0xf0000000 0x2000>;
50			interrupts = <11>;
51			clock-frequency = <3686400>;
52			baud = <115200>;
53			reg-shift = <2>;
54			reg-io-width = <4>;
55			no-loopback-test = <1>;
56		};
57
58		pguclk: pguclk {
59			#clock-cells = <0>;
60			compatible = "fixed-clock";
61			clock-frequency = <25175000>;
62		};
63
64		pgu@f9000000 {
65			compatible = "snps,arcpgu";
66			reg = <0xf9000000 0x400>;
67			clocks = <&pguclk>;
68			clock-names = "pxlclk";
69		};
70
71		ps2: ps2@f9001000 {
72			compatible = "snps,arc_ps2";
73			reg = <0xf9000400 0x14>;
74			interrupts = <13>;
75			interrupt-names = "arc_ps2_irq";
76		};
77
78		eth0: ethernet@f0003000 {
79			compatible = "ezchip,nps-mgt-enet";
80			reg = <0xf0003000 0x44>;
81			interrupts = <7>;
82		};
83
84		arcpct0: pct {
85			compatible = "snps,arc700-pct";
86		};
87	};
88};

 
 1/*
 2 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8/dts-v1/;
 9
10/include/ "skeleton.dtsi"
11
12/ {
 
13	compatible = "snps,nsimosci";
14	clock-frequency = <20000000>;	/* 20 MHZ */
15	#address-cells = <1>;
16	#size-cells = <1>;
17	interrupt-parent = <&intc>;
18
19	chosen {
20		/* this is for console on PGU */
21		/* bootargs = "console=tty0 consoleblank=0"; */
22		/* this is for console on serial */
23		bootargs = "earlycon=uart8250,mmio32,0xc0000000,115200n8 console=ttyS0,115200n8 consoleblank=0 debug";
24	};
25
26	aliases {
27		serial0 = &uart0;
28	};
29
30	memory {
31		device_type = "memory";
32		reg = <0x80000000 0x10000000>;	/* 256M */
33	};
34
35	fpga {
36		compatible = "simple-bus";
37		#address-cells = <1>;
38		#size-cells = <1>;
39
40		/* child and parent address space 1:1 mapped */
41		ranges;
42
43		intc: interrupt-controller {
 
 
 
 
 
 
44			compatible = "snps,arc700-intc";
45			interrupt-controller;
46			#interrupt-cells = <1>;
47		};
48
49		uart0: serial@c0000000 {
50			compatible = "ns8250";
51			reg = <0xc0000000 0x2000>;
52			interrupts = <11>;
53			clock-frequency = <3686400>;
54			baud = <115200>;
55			reg-shift = <2>;
56			reg-io-width = <4>;
57			no-loopback-test = <1>;
58		};
59
60		pgu0: pgu@c9000000 {
61			compatible = "snps,arcpgufb";
62			reg = <0xc9000000 0x400>;
 
63		};
64
65		ps2: ps2@c9001000 {
 
 
 
 
 
 
 
66			compatible = "snps,arc_ps2";
67			reg = <0xc9000400 0x14>;
68			interrupts = <13>;
69			interrupt-names = "arc_ps2_irq";
70		};
71
72		eth0: ethernet@c0003000 {
73			compatible = "snps,oscilan";
74			reg = <0xc0003000 0x44>;
75			interrupts = <7>, <8>;
76			interrupt-names = "rx", "tx";
 
 
 
77		};
78	};
79};