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1// SPDX-License-Identifier: GPL-2.0
2/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
6 *
7 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
8 * Maxim Krasnyanskiy <maxk@qualcomm.com>
9 *
10 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
11 * rates to be programmed into the UART. Also eliminated a lot of
12 * duplicated code in the console setup.
13 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
14 *
15 * Ported to new 2.5.x UART layer.
16 * David S. Miller <davem@davemloft.net>
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/major.h>
25#include <linux/string.h>
26#include <linux/ptrace.h>
27#include <linux/ioport.h>
28#include <linux/circ_buf.h>
29#include <linux/serial.h>
30#include <linux/sysrq.h>
31#include <linux/console.h>
32#include <linux/spinlock.h>
33#include <linux/slab.h>
34#include <linux/delay.h>
35#include <linux/init.h>
36#include <linux/of_device.h>
37
38#include <linux/io.h>
39#include <asm/irq.h>
40#include <asm/prom.h>
41#include <asm/setup.h>
42
43#include <linux/serial_core.h>
44#include <linux/sunserialcore.h>
45
46#include "sunsab.h"
47
48struct uart_sunsab_port {
49 struct uart_port port; /* Generic UART port */
50 union sab82532_async_regs __iomem *regs; /* Chip registers */
51 unsigned long irqflags; /* IRQ state flags */
52 int dsr; /* Current DSR state */
53 unsigned int cec_timeout; /* Chip poll timeout... */
54 unsigned int tec_timeout; /* likewise */
55 unsigned char interrupt_mask0;/* ISR0 masking */
56 unsigned char interrupt_mask1;/* ISR1 masking */
57 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
58 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
59 unsigned int gis_shift;
60 int type; /* SAB82532 version */
61
62 /* Setting configuration bits while the transmitter is active
63 * can cause garbage characters to get emitted by the chip.
64 * Therefore, we cache such writes here and do the real register
65 * write the next time the transmitter becomes idle.
66 */
67 unsigned int cached_ebrg;
68 unsigned char cached_mode;
69 unsigned char cached_pvr;
70 unsigned char cached_dafo;
71};
72
73/*
74 * This assumes you have a 29.4912 MHz clock for your UART.
75 */
76#define SAB_BASE_BAUD ( 29491200 / 16 )
77
78static char *sab82532_version[16] = {
79 "V1.0", "V2.0", "V3.2", "V(0x03)",
80 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
81 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
82 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
83};
84
85#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
86#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
87
88#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
89#define SAB82532_XMIT_FIFO_SIZE 32
90
91static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
92{
93 int timeout = up->tec_timeout;
94
95 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
96 udelay(1);
97}
98
99static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
100{
101 int timeout = up->cec_timeout;
102
103 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
104 udelay(1);
105}
106
107static struct tty_port *
108receive_chars(struct uart_sunsab_port *up,
109 union sab82532_irq_status *stat)
110{
111 struct tty_port *port = NULL;
112 unsigned char buf[32];
113 int saw_console_brk = 0;
114 int free_fifo = 0;
115 int count = 0;
116 int i;
117
118 if (up->port.state != NULL) /* Unopened serial console */
119 port = &up->port.state->port;
120
121 /* Read number of BYTES (Character + Status) available. */
122 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
123 count = SAB82532_RECV_FIFO_SIZE;
124 free_fifo++;
125 }
126
127 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
128 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
129 free_fifo++;
130 }
131
132 /* Issue a FIFO read command in case we where idle. */
133 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
134 sunsab_cec_wait(up);
135 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
136 return port;
137 }
138
139 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
140 free_fifo++;
141
142 /* Read the FIFO. */
143 for (i = 0; i < count; i++)
144 buf[i] = readb(&up->regs->r.rfifo[i]);
145
146 /* Issue Receive Message Complete command. */
147 if (free_fifo) {
148 sunsab_cec_wait(up);
149 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
150 }
151
152 /* Count may be zero for BRK, so we check for it here */
153 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
154 (up->port.line == up->port.cons->index))
155 saw_console_brk = 1;
156
157 if (count == 0) {
158 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
159 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
160 SAB82532_ISR0_FERR);
161 up->port.icount.brk++;
162 uart_handle_break(&up->port);
163 }
164 }
165
166 for (i = 0; i < count; i++) {
167 unsigned char ch = buf[i], flag;
168
169 flag = TTY_NORMAL;
170 up->port.icount.rx++;
171
172 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
173 SAB82532_ISR0_FERR |
174 SAB82532_ISR0_RFO)) ||
175 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
176 /*
177 * For statistics only
178 */
179 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
180 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
181 SAB82532_ISR0_FERR);
182 up->port.icount.brk++;
183 /*
184 * We do the SysRQ and SAK checking
185 * here because otherwise the break
186 * may get masked by ignore_status_mask
187 * or read_status_mask.
188 */
189 if (uart_handle_break(&up->port))
190 continue;
191 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
192 up->port.icount.parity++;
193 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
194 up->port.icount.frame++;
195 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
196 up->port.icount.overrun++;
197
198 /*
199 * Mask off conditions which should be ingored.
200 */
201 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
202 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
203
204 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
205 flag = TTY_BREAK;
206 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
207 flag = TTY_PARITY;
208 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
209 flag = TTY_FRAME;
210 }
211
212 if (uart_handle_sysrq_char(&up->port, ch) || !port)
213 continue;
214
215 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
216 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
217 tty_insert_flip_char(port, ch, flag);
218 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
219 tty_insert_flip_char(port, 0, TTY_OVERRUN);
220 }
221
222 if (saw_console_brk)
223 sun_do_break();
224
225 return port;
226}
227
228static void sunsab_stop_tx(struct uart_port *);
229static void sunsab_tx_idle(struct uart_sunsab_port *);
230
231static void transmit_chars(struct uart_sunsab_port *up,
232 union sab82532_irq_status *stat)
233{
234 struct circ_buf *xmit = &up->port.state->xmit;
235 int i;
236
237 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
238 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
239 writeb(up->interrupt_mask1, &up->regs->w.imr1);
240 set_bit(SAB82532_ALLS, &up->irqflags);
241 }
242
243#if 0 /* bde@nwlink.com says this check causes problems */
244 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
245 return;
246#endif
247
248 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
249 return;
250
251 set_bit(SAB82532_XPR, &up->irqflags);
252 sunsab_tx_idle(up);
253
254 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
255 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
256 writeb(up->interrupt_mask1, &up->regs->w.imr1);
257 return;
258 }
259
260 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
261 writeb(up->interrupt_mask1, &up->regs->w.imr1);
262 clear_bit(SAB82532_ALLS, &up->irqflags);
263
264 /* Stuff 32 bytes into Transmit FIFO. */
265 clear_bit(SAB82532_XPR, &up->irqflags);
266 for (i = 0; i < up->port.fifosize; i++) {
267 writeb(xmit->buf[xmit->tail],
268 &up->regs->w.xfifo[i]);
269 uart_xmit_advance(&up->port, 1);
270 if (uart_circ_empty(xmit))
271 break;
272 }
273
274 /* Issue a Transmit Frame command. */
275 sunsab_cec_wait(up);
276 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
277
278 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
279 uart_write_wakeup(&up->port);
280
281 if (uart_circ_empty(xmit))
282 sunsab_stop_tx(&up->port);
283}
284
285static void check_status(struct uart_sunsab_port *up,
286 union sab82532_irq_status *stat)
287{
288 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
289 uart_handle_dcd_change(&up->port,
290 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
291
292 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
293 uart_handle_cts_change(&up->port,
294 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
295
296 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
297 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
298 up->port.icount.dsr++;
299 }
300
301 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
302}
303
304static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
305{
306 struct uart_sunsab_port *up = dev_id;
307 struct tty_port *port = NULL;
308 union sab82532_irq_status status;
309 unsigned long flags;
310 unsigned char gis;
311
312 spin_lock_irqsave(&up->port.lock, flags);
313
314 status.stat = 0;
315 gis = readb(&up->regs->r.gis) >> up->gis_shift;
316 if (gis & 1)
317 status.sreg.isr0 = readb(&up->regs->r.isr0);
318 if (gis & 2)
319 status.sreg.isr1 = readb(&up->regs->r.isr1);
320
321 if (status.stat) {
322 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
323 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
324 (status.sreg.isr1 & SAB82532_ISR1_BRK))
325 port = receive_chars(up, &status);
326 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
327 (status.sreg.isr1 & SAB82532_ISR1_CSC))
328 check_status(up, &status);
329 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
330 transmit_chars(up, &status);
331 }
332
333 spin_unlock_irqrestore(&up->port.lock, flags);
334
335 if (port)
336 tty_flip_buffer_push(port);
337
338 return IRQ_HANDLED;
339}
340
341/* port->lock is not held. */
342static unsigned int sunsab_tx_empty(struct uart_port *port)
343{
344 struct uart_sunsab_port *up =
345 container_of(port, struct uart_sunsab_port, port);
346 int ret;
347
348 /* Do not need a lock for a state test like this. */
349 if (test_bit(SAB82532_ALLS, &up->irqflags))
350 ret = TIOCSER_TEMT;
351 else
352 ret = 0;
353
354 return ret;
355}
356
357/* port->lock held by caller. */
358static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
359{
360 struct uart_sunsab_port *up =
361 container_of(port, struct uart_sunsab_port, port);
362
363 if (mctrl & TIOCM_RTS) {
364 up->cached_mode &= ~SAB82532_MODE_FRTS;
365 up->cached_mode |= SAB82532_MODE_RTS;
366 } else {
367 up->cached_mode |= (SAB82532_MODE_FRTS |
368 SAB82532_MODE_RTS);
369 }
370 if (mctrl & TIOCM_DTR) {
371 up->cached_pvr &= ~(up->pvr_dtr_bit);
372 } else {
373 up->cached_pvr |= up->pvr_dtr_bit;
374 }
375
376 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
377 if (test_bit(SAB82532_XPR, &up->irqflags))
378 sunsab_tx_idle(up);
379}
380
381/* port->lock is held by caller and interrupts are disabled. */
382static unsigned int sunsab_get_mctrl(struct uart_port *port)
383{
384 struct uart_sunsab_port *up =
385 container_of(port, struct uart_sunsab_port, port);
386 unsigned char val;
387 unsigned int result;
388
389 result = 0;
390
391 val = readb(&up->regs->r.pvr);
392 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
393
394 val = readb(&up->regs->r.vstr);
395 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
396
397 val = readb(&up->regs->r.star);
398 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
399
400 return result;
401}
402
403/* port->lock held by caller. */
404static void sunsab_stop_tx(struct uart_port *port)
405{
406 struct uart_sunsab_port *up =
407 container_of(port, struct uart_sunsab_port, port);
408
409 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
410 writeb(up->interrupt_mask1, &up->regs->w.imr1);
411}
412
413/* port->lock held by caller. */
414static void sunsab_tx_idle(struct uart_sunsab_port *up)
415{
416 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
417 u8 tmp;
418
419 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
420 writeb(up->cached_mode, &up->regs->rw.mode);
421 writeb(up->cached_pvr, &up->regs->rw.pvr);
422 writeb(up->cached_dafo, &up->regs->w.dafo);
423
424 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
425 tmp = readb(&up->regs->rw.ccr2);
426 tmp &= ~0xc0;
427 tmp |= (up->cached_ebrg >> 2) & 0xc0;
428 writeb(tmp, &up->regs->rw.ccr2);
429 }
430}
431
432/* port->lock held by caller. */
433static void sunsab_start_tx(struct uart_port *port)
434{
435 struct uart_sunsab_port *up =
436 container_of(port, struct uart_sunsab_port, port);
437 struct circ_buf *xmit = &up->port.state->xmit;
438 int i;
439
440 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
441 return;
442
443 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
444 writeb(up->interrupt_mask1, &up->regs->w.imr1);
445
446 if (!test_bit(SAB82532_XPR, &up->irqflags))
447 return;
448
449 clear_bit(SAB82532_ALLS, &up->irqflags);
450 clear_bit(SAB82532_XPR, &up->irqflags);
451
452 for (i = 0; i < up->port.fifosize; i++) {
453 writeb(xmit->buf[xmit->tail],
454 &up->regs->w.xfifo[i]);
455 uart_xmit_advance(&up->port, 1);
456 if (uart_circ_empty(xmit))
457 break;
458 }
459
460 /* Issue a Transmit Frame command. */
461 sunsab_cec_wait(up);
462 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
463}
464
465/* port->lock is not held. */
466static void sunsab_send_xchar(struct uart_port *port, char ch)
467{
468 struct uart_sunsab_port *up =
469 container_of(port, struct uart_sunsab_port, port);
470 unsigned long flags;
471
472 if (ch == __DISABLED_CHAR)
473 return;
474
475 spin_lock_irqsave(&up->port.lock, flags);
476
477 sunsab_tec_wait(up);
478 writeb(ch, &up->regs->w.tic);
479
480 spin_unlock_irqrestore(&up->port.lock, flags);
481}
482
483/* port->lock held by caller. */
484static void sunsab_stop_rx(struct uart_port *port)
485{
486 struct uart_sunsab_port *up =
487 container_of(port, struct uart_sunsab_port, port);
488
489 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
490 writeb(up->interrupt_mask1, &up->regs->w.imr0);
491}
492
493/* port->lock is not held. */
494static void sunsab_break_ctl(struct uart_port *port, int break_state)
495{
496 struct uart_sunsab_port *up =
497 container_of(port, struct uart_sunsab_port, port);
498 unsigned long flags;
499 unsigned char val;
500
501 spin_lock_irqsave(&up->port.lock, flags);
502
503 val = up->cached_dafo;
504 if (break_state)
505 val |= SAB82532_DAFO_XBRK;
506 else
507 val &= ~SAB82532_DAFO_XBRK;
508 up->cached_dafo = val;
509
510 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
511 if (test_bit(SAB82532_XPR, &up->irqflags))
512 sunsab_tx_idle(up);
513
514 spin_unlock_irqrestore(&up->port.lock, flags);
515}
516
517/* port->lock is not held. */
518static int sunsab_startup(struct uart_port *port)
519{
520 struct uart_sunsab_port *up =
521 container_of(port, struct uart_sunsab_port, port);
522 unsigned long flags;
523 unsigned char tmp;
524 int err = request_irq(up->port.irq, sunsab_interrupt,
525 IRQF_SHARED, "sab", up);
526 if (err)
527 return err;
528
529 spin_lock_irqsave(&up->port.lock, flags);
530
531 /*
532 * Wait for any commands or immediate characters
533 */
534 sunsab_cec_wait(up);
535 sunsab_tec_wait(up);
536
537 /*
538 * Clear the FIFO buffers.
539 */
540 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
541 sunsab_cec_wait(up);
542 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
543
544 /*
545 * Clear the interrupt registers.
546 */
547 (void) readb(&up->regs->r.isr0);
548 (void) readb(&up->regs->r.isr1);
549
550 /*
551 * Now, initialize the UART
552 */
553 writeb(0, &up->regs->w.ccr0); /* power-down */
554 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
555 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
556 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
557 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
558 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
559 writeb(0, &up->regs->w.ccr3);
560 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
561 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
562 SAB82532_MODE_RAC);
563 writeb(up->cached_mode, &up->regs->w.mode);
564 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
565
566 tmp = readb(&up->regs->rw.ccr0);
567 tmp |= SAB82532_CCR0_PU; /* power-up */
568 writeb(tmp, &up->regs->rw.ccr0);
569
570 /*
571 * Finally, enable interrupts
572 */
573 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
574 SAB82532_IMR0_PLLA);
575 writeb(up->interrupt_mask0, &up->regs->w.imr0);
576 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
577 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
578 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
579 SAB82532_IMR1_XPR);
580 writeb(up->interrupt_mask1, &up->regs->w.imr1);
581 set_bit(SAB82532_ALLS, &up->irqflags);
582 set_bit(SAB82532_XPR, &up->irqflags);
583
584 spin_unlock_irqrestore(&up->port.lock, flags);
585
586 return 0;
587}
588
589/* port->lock is not held. */
590static void sunsab_shutdown(struct uart_port *port)
591{
592 struct uart_sunsab_port *up =
593 container_of(port, struct uart_sunsab_port, port);
594 unsigned long flags;
595
596 spin_lock_irqsave(&up->port.lock, flags);
597
598 /* Disable Interrupts */
599 up->interrupt_mask0 = 0xff;
600 writeb(up->interrupt_mask0, &up->regs->w.imr0);
601 up->interrupt_mask1 = 0xff;
602 writeb(up->interrupt_mask1, &up->regs->w.imr1);
603
604 /* Disable break condition */
605 up->cached_dafo = readb(&up->regs->rw.dafo);
606 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
607 writeb(up->cached_dafo, &up->regs->rw.dafo);
608
609 /* Disable Receiver */
610 up->cached_mode &= ~SAB82532_MODE_RAC;
611 writeb(up->cached_mode, &up->regs->rw.mode);
612
613 /*
614 * XXX FIXME
615 *
616 * If the chip is powered down here the system hangs/crashes during
617 * reboot or shutdown. This needs to be investigated further,
618 * similar behaviour occurs in 2.4 when the driver is configured
619 * as a module only. One hint may be that data is sometimes
620 * transmitted at 9600 baud during shutdown (regardless of the
621 * speed the chip was configured for when the port was open).
622 */
623#if 0
624 /* Power Down */
625 tmp = readb(&up->regs->rw.ccr0);
626 tmp &= ~SAB82532_CCR0_PU;
627 writeb(tmp, &up->regs->rw.ccr0);
628#endif
629
630 spin_unlock_irqrestore(&up->port.lock, flags);
631 free_irq(up->port.irq, up);
632}
633
634/*
635 * This is used to figure out the divisor speeds.
636 *
637 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
638 *
639 * with 0 <= N < 64 and 0 <= M < 16
640 */
641
642static void calc_ebrg(int baud, int *n_ret, int *m_ret)
643{
644 int n, m;
645
646 if (baud == 0) {
647 *n_ret = 0;
648 *m_ret = 0;
649 return;
650 }
651
652 /*
653 * We scale numbers by 10 so that we get better accuracy
654 * without having to use floating point. Here we increment m
655 * until n is within the valid range.
656 */
657 n = (SAB_BASE_BAUD * 10) / baud;
658 m = 0;
659 while (n >= 640) {
660 n = n / 2;
661 m++;
662 }
663 n = (n+5) / 10;
664 /*
665 * We try very hard to avoid speeds with M == 0 since they may
666 * not work correctly for XTAL frequences above 10 MHz.
667 */
668 if ((m == 0) && ((n & 1) == 0)) {
669 n = n / 2;
670 m++;
671 }
672 *n_ret = n - 1;
673 *m_ret = m;
674}
675
676/* Internal routine, port->lock is held and local interrupts are disabled. */
677static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
678 unsigned int iflag, unsigned int baud,
679 unsigned int quot)
680{
681 unsigned char dafo;
682 int n, m;
683
684 /* Byte size and parity */
685 switch (cflag & CSIZE) {
686 case CS5: dafo = SAB82532_DAFO_CHL5; break;
687 case CS6: dafo = SAB82532_DAFO_CHL6; break;
688 case CS7: dafo = SAB82532_DAFO_CHL7; break;
689 case CS8: dafo = SAB82532_DAFO_CHL8; break;
690 /* Never happens, but GCC is too dumb to figure it out */
691 default: dafo = SAB82532_DAFO_CHL5; break;
692 }
693
694 if (cflag & CSTOPB)
695 dafo |= SAB82532_DAFO_STOP;
696
697 if (cflag & PARENB)
698 dafo |= SAB82532_DAFO_PARE;
699
700 if (cflag & PARODD) {
701 dafo |= SAB82532_DAFO_PAR_ODD;
702 } else {
703 dafo |= SAB82532_DAFO_PAR_EVEN;
704 }
705 up->cached_dafo = dafo;
706
707 calc_ebrg(baud, &n, &m);
708
709 up->cached_ebrg = n | (m << 6);
710
711 up->tec_timeout = (10 * 1000000) / baud;
712 up->cec_timeout = up->tec_timeout >> 2;
713
714 /* CTS flow control flags */
715 /* We encode read_status_mask and ignore_status_mask like so:
716 *
717 * ---------------------
718 * | ... | ISR1 | ISR0 |
719 * ---------------------
720 * .. 15 8 7 0
721 */
722
723 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
724 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
725 SAB82532_ISR0_CDSC);
726 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
727 SAB82532_ISR1_ALLS |
728 SAB82532_ISR1_XPR) << 8;
729 if (iflag & INPCK)
730 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
731 SAB82532_ISR0_FERR);
732 if (iflag & (IGNBRK | BRKINT | PARMRK))
733 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
734
735 /*
736 * Characteres to ignore
737 */
738 up->port.ignore_status_mask = 0;
739 if (iflag & IGNPAR)
740 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
741 SAB82532_ISR0_FERR);
742 if (iflag & IGNBRK) {
743 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
744 /*
745 * If we're ignoring parity and break indicators,
746 * ignore overruns too (for real raw support).
747 */
748 if (iflag & IGNPAR)
749 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
750 }
751
752 /*
753 * ignore all characters if CREAD is not set
754 */
755 if ((cflag & CREAD) == 0)
756 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
757 SAB82532_ISR0_TCD);
758
759 uart_update_timeout(&up->port, cflag,
760 (up->port.uartclk / (16 * quot)));
761
762 /* Now schedule a register update when the chip's
763 * transmitter is idle.
764 */
765 up->cached_mode |= SAB82532_MODE_RAC;
766 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
767 if (test_bit(SAB82532_XPR, &up->irqflags))
768 sunsab_tx_idle(up);
769}
770
771/* port->lock is not held. */
772static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
773 const struct ktermios *old)
774{
775 struct uart_sunsab_port *up =
776 container_of(port, struct uart_sunsab_port, port);
777 unsigned long flags;
778 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
779 unsigned int quot = uart_get_divisor(port, baud);
780
781 spin_lock_irqsave(&up->port.lock, flags);
782 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
783 spin_unlock_irqrestore(&up->port.lock, flags);
784}
785
786static const char *sunsab_type(struct uart_port *port)
787{
788 struct uart_sunsab_port *up = (void *)port;
789 static char buf[36];
790
791 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
792 return buf;
793}
794
795static void sunsab_release_port(struct uart_port *port)
796{
797}
798
799static int sunsab_request_port(struct uart_port *port)
800{
801 return 0;
802}
803
804static void sunsab_config_port(struct uart_port *port, int flags)
805{
806}
807
808static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
809{
810 return -EINVAL;
811}
812
813static const struct uart_ops sunsab_pops = {
814 .tx_empty = sunsab_tx_empty,
815 .set_mctrl = sunsab_set_mctrl,
816 .get_mctrl = sunsab_get_mctrl,
817 .stop_tx = sunsab_stop_tx,
818 .start_tx = sunsab_start_tx,
819 .send_xchar = sunsab_send_xchar,
820 .stop_rx = sunsab_stop_rx,
821 .break_ctl = sunsab_break_ctl,
822 .startup = sunsab_startup,
823 .shutdown = sunsab_shutdown,
824 .set_termios = sunsab_set_termios,
825 .type = sunsab_type,
826 .release_port = sunsab_release_port,
827 .request_port = sunsab_request_port,
828 .config_port = sunsab_config_port,
829 .verify_port = sunsab_verify_port,
830};
831
832static struct uart_driver sunsab_reg = {
833 .owner = THIS_MODULE,
834 .driver_name = "sunsab",
835 .dev_name = "ttyS",
836 .major = TTY_MAJOR,
837};
838
839static struct uart_sunsab_port *sunsab_ports;
840
841#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
842
843static void sunsab_console_putchar(struct uart_port *port, unsigned char c)
844{
845 struct uart_sunsab_port *up =
846 container_of(port, struct uart_sunsab_port, port);
847
848 sunsab_tec_wait(up);
849 writeb(c, &up->regs->w.tic);
850}
851
852static void sunsab_console_write(struct console *con, const char *s, unsigned n)
853{
854 struct uart_sunsab_port *up = &sunsab_ports[con->index];
855 unsigned long flags;
856 int locked = 1;
857
858 if (up->port.sysrq || oops_in_progress)
859 locked = spin_trylock_irqsave(&up->port.lock, flags);
860 else
861 spin_lock_irqsave(&up->port.lock, flags);
862
863 uart_console_write(&up->port, s, n, sunsab_console_putchar);
864 sunsab_tec_wait(up);
865
866 if (locked)
867 spin_unlock_irqrestore(&up->port.lock, flags);
868}
869
870static int sunsab_console_setup(struct console *con, char *options)
871{
872 struct uart_sunsab_port *up = &sunsab_ports[con->index];
873 unsigned long flags;
874 unsigned int baud, quot;
875
876 /*
877 * The console framework calls us for each and every port
878 * registered. Defer the console setup until the requested
879 * port has been properly discovered. A bit of a hack,
880 * though...
881 */
882 if (up->port.type != PORT_SUNSAB)
883 return -EINVAL;
884
885 printk("Console: ttyS%d (SAB82532)\n",
886 (sunsab_reg.minor - 64) + con->index);
887
888 sunserial_console_termios(con, up->port.dev->of_node);
889
890 switch (con->cflag & CBAUD) {
891 case B150: baud = 150; break;
892 case B300: baud = 300; break;
893 case B600: baud = 600; break;
894 case B1200: baud = 1200; break;
895 case B2400: baud = 2400; break;
896 case B4800: baud = 4800; break;
897 default: case B9600: baud = 9600; break;
898 case B19200: baud = 19200; break;
899 case B38400: baud = 38400; break;
900 case B57600: baud = 57600; break;
901 case B115200: baud = 115200; break;
902 case B230400: baud = 230400; break;
903 case B460800: baud = 460800; break;
904 }
905
906 /*
907 * Temporary fix.
908 */
909 spin_lock_init(&up->port.lock);
910
911 /*
912 * Initialize the hardware
913 */
914 sunsab_startup(&up->port);
915
916 spin_lock_irqsave(&up->port.lock, flags);
917
918 /*
919 * Finally, enable interrupts
920 */
921 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
922 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
923 writeb(up->interrupt_mask0, &up->regs->w.imr0);
924 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
925 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
926 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
927 SAB82532_IMR1_XPR;
928 writeb(up->interrupt_mask1, &up->regs->w.imr1);
929
930 quot = uart_get_divisor(&up->port, baud);
931 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
932 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
933
934 spin_unlock_irqrestore(&up->port.lock, flags);
935
936 return 0;
937}
938
939static struct console sunsab_console = {
940 .name = "ttyS",
941 .write = sunsab_console_write,
942 .device = uart_console_device,
943 .setup = sunsab_console_setup,
944 .flags = CON_PRINTBUFFER,
945 .index = -1,
946 .data = &sunsab_reg,
947};
948
949static inline struct console *SUNSAB_CONSOLE(void)
950{
951 return &sunsab_console;
952}
953#else
954#define SUNSAB_CONSOLE() (NULL)
955#define sunsab_console_init() do { } while (0)
956#endif
957
958static int sunsab_init_one(struct uart_sunsab_port *up,
959 struct platform_device *op,
960 unsigned long offset,
961 int line)
962{
963 up->port.line = line;
964 up->port.dev = &op->dev;
965
966 up->port.mapbase = op->resource[0].start + offset;
967 up->port.membase = of_ioremap(&op->resource[0], offset,
968 sizeof(union sab82532_async_regs),
969 "sab");
970 if (!up->port.membase)
971 return -ENOMEM;
972 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
973
974 up->port.irq = op->archdata.irqs[0];
975
976 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
977 up->port.iotype = UPIO_MEM;
978 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE);
979
980 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
981
982 up->port.ops = &sunsab_pops;
983 up->port.type = PORT_SUNSAB;
984 up->port.uartclk = SAB_BASE_BAUD;
985
986 up->type = readb(&up->regs->r.vstr) & 0x0f;
987 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
988 writeb(0xff, &up->regs->w.pim);
989 if ((up->port.line & 0x1) == 0) {
990 up->pvr_dsr_bit = (1 << 0);
991 up->pvr_dtr_bit = (1 << 1);
992 up->gis_shift = 2;
993 } else {
994 up->pvr_dsr_bit = (1 << 3);
995 up->pvr_dtr_bit = (1 << 2);
996 up->gis_shift = 0;
997 }
998 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
999 writeb(up->cached_pvr, &up->regs->w.pvr);
1000 up->cached_mode = readb(&up->regs->rw.mode);
1001 up->cached_mode |= SAB82532_MODE_FRTS;
1002 writeb(up->cached_mode, &up->regs->rw.mode);
1003 up->cached_mode |= SAB82532_MODE_RTS;
1004 writeb(up->cached_mode, &up->regs->rw.mode);
1005
1006 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1007 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1008
1009 return 0;
1010}
1011
1012static int sab_probe(struct platform_device *op)
1013{
1014 static int inst;
1015 struct uart_sunsab_port *up;
1016 int err;
1017
1018 up = &sunsab_ports[inst * 2];
1019
1020 err = sunsab_init_one(&up[0], op,
1021 0,
1022 (inst * 2) + 0);
1023 if (err)
1024 goto out;
1025
1026 err = sunsab_init_one(&up[1], op,
1027 sizeof(union sab82532_async_regs),
1028 (inst * 2) + 1);
1029 if (err)
1030 goto out1;
1031
1032 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1033 &sunsab_reg, up[0].port.line,
1034 false);
1035
1036 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1037 &sunsab_reg, up[1].port.line,
1038 false);
1039
1040 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1041 if (err)
1042 goto out2;
1043
1044 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1045 if (err)
1046 goto out3;
1047
1048 platform_set_drvdata(op, &up[0]);
1049
1050 inst++;
1051
1052 return 0;
1053
1054out3:
1055 uart_remove_one_port(&sunsab_reg, &up[0].port);
1056out2:
1057 of_iounmap(&op->resource[0],
1058 up[1].port.membase,
1059 sizeof(union sab82532_async_regs));
1060out1:
1061 of_iounmap(&op->resource[0],
1062 up[0].port.membase,
1063 sizeof(union sab82532_async_regs));
1064out:
1065 return err;
1066}
1067
1068static int sab_remove(struct platform_device *op)
1069{
1070 struct uart_sunsab_port *up = platform_get_drvdata(op);
1071
1072 uart_remove_one_port(&sunsab_reg, &up[1].port);
1073 uart_remove_one_port(&sunsab_reg, &up[0].port);
1074 of_iounmap(&op->resource[0],
1075 up[1].port.membase,
1076 sizeof(union sab82532_async_regs));
1077 of_iounmap(&op->resource[0],
1078 up[0].port.membase,
1079 sizeof(union sab82532_async_regs));
1080
1081 return 0;
1082}
1083
1084static const struct of_device_id sab_match[] = {
1085 {
1086 .name = "se",
1087 },
1088 {
1089 .name = "serial",
1090 .compatible = "sab82532",
1091 },
1092 {},
1093};
1094MODULE_DEVICE_TABLE(of, sab_match);
1095
1096static struct platform_driver sab_driver = {
1097 .driver = {
1098 .name = "sab",
1099 .of_match_table = sab_match,
1100 },
1101 .probe = sab_probe,
1102 .remove = sab_remove,
1103};
1104
1105static int __init sunsab_init(void)
1106{
1107 struct device_node *dp;
1108 int err;
1109 int num_channels = 0;
1110
1111 for_each_node_by_name(dp, "se")
1112 num_channels += 2;
1113 for_each_node_by_name(dp, "serial") {
1114 if (of_device_is_compatible(dp, "sab82532"))
1115 num_channels += 2;
1116 }
1117
1118 if (num_channels) {
1119 sunsab_ports = kcalloc(num_channels,
1120 sizeof(struct uart_sunsab_port),
1121 GFP_KERNEL);
1122 if (!sunsab_ports)
1123 return -ENOMEM;
1124
1125 err = sunserial_register_minors(&sunsab_reg, num_channels);
1126 if (err) {
1127 kfree(sunsab_ports);
1128 sunsab_ports = NULL;
1129
1130 return err;
1131 }
1132 }
1133
1134 err = platform_driver_register(&sab_driver);
1135 if (err) {
1136 kfree(sunsab_ports);
1137 sunsab_ports = NULL;
1138 }
1139
1140 return err;
1141}
1142
1143static void __exit sunsab_exit(void)
1144{
1145 platform_driver_unregister(&sab_driver);
1146 if (sunsab_reg.nr) {
1147 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1148 }
1149
1150 kfree(sunsab_ports);
1151 sunsab_ports = NULL;
1152}
1153
1154module_init(sunsab_init);
1155module_exit(sunsab_exit);
1156
1157MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1158MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1159MODULE_LICENSE("GPL");
1/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@davemloft.net>
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/major.h>
24#include <linux/string.h>
25#include <linux/ptrace.h>
26#include <linux/ioport.h>
27#include <linux/circ_buf.h>
28#include <linux/serial.h>
29#include <linux/sysrq.h>
30#include <linux/console.h>
31#include <linux/spinlock.h>
32#include <linux/slab.h>
33#include <linux/delay.h>
34#include <linux/init.h>
35#include <linux/of_device.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/prom.h>
40#include <asm/setup.h>
41
42#if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43#define SUPPORT_SYSRQ
44#endif
45
46#include <linux/serial_core.h>
47#include <linux/sunserialcore.h>
48
49#include "sunsab.h"
50
51struct uart_sunsab_port {
52 struct uart_port port; /* Generic UART port */
53 union sab82532_async_regs __iomem *regs; /* Chip registers */
54 unsigned long irqflags; /* IRQ state flags */
55 int dsr; /* Current DSR state */
56 unsigned int cec_timeout; /* Chip poll timeout... */
57 unsigned int tec_timeout; /* likewise */
58 unsigned char interrupt_mask0;/* ISR0 masking */
59 unsigned char interrupt_mask1;/* ISR1 masking */
60 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
61 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
62 unsigned int gis_shift;
63 int type; /* SAB82532 version */
64
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
69 */
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
74};
75
76/*
77 * This assumes you have a 29.4912 MHz clock for your UART.
78 */
79#define SAB_BASE_BAUD ( 29491200 / 16 )
80
81static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
86};
87
88#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
90
91#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92#define SAB82532_XMIT_FIFO_SIZE 32
93
94static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
95{
96 int timeout = up->tec_timeout;
97
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
99 udelay(1);
100}
101
102static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
103{
104 int timeout = up->cec_timeout;
105
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
107 udelay(1);
108}
109
110static struct tty_port *
111receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat)
113{
114 struct tty_port *port = NULL;
115 unsigned char buf[32];
116 int saw_console_brk = 0;
117 int free_fifo = 0;
118 int count = 0;
119 int i;
120
121 if (up->port.state != NULL) /* Unopened serial console */
122 port = &up->port.state->port;
123
124 /* Read number of BYTES (Character + Status) available. */
125 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
126 count = SAB82532_RECV_FIFO_SIZE;
127 free_fifo++;
128 }
129
130 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
131 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
132 free_fifo++;
133 }
134
135 /* Issue a FIFO read command in case we where idle. */
136 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
137 sunsab_cec_wait(up);
138 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
139 return port;
140 }
141
142 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
143 free_fifo++;
144
145 /* Read the FIFO. */
146 for (i = 0; i < count; i++)
147 buf[i] = readb(&up->regs->r.rfifo[i]);
148
149 /* Issue Receive Message Complete command. */
150 if (free_fifo) {
151 sunsab_cec_wait(up);
152 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
153 }
154
155 /* Count may be zero for BRK, so we check for it here */
156 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
157 (up->port.line == up->port.cons->index))
158 saw_console_brk = 1;
159
160 for (i = 0; i < count; i++) {
161 unsigned char ch = buf[i], flag;
162
163 flag = TTY_NORMAL;
164 up->port.icount.rx++;
165
166 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
167 SAB82532_ISR0_FERR |
168 SAB82532_ISR0_RFO)) ||
169 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
170 /*
171 * For statistics only
172 */
173 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
174 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
175 SAB82532_ISR0_FERR);
176 up->port.icount.brk++;
177 /*
178 * We do the SysRQ and SAK checking
179 * here because otherwise the break
180 * may get masked by ignore_status_mask
181 * or read_status_mask.
182 */
183 if (uart_handle_break(&up->port))
184 continue;
185 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
186 up->port.icount.parity++;
187 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
188 up->port.icount.frame++;
189 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
190 up->port.icount.overrun++;
191
192 /*
193 * Mask off conditions which should be ingored.
194 */
195 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
196 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
197
198 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
199 flag = TTY_BREAK;
200 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
201 flag = TTY_PARITY;
202 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
203 flag = TTY_FRAME;
204 }
205
206 if (uart_handle_sysrq_char(&up->port, ch) || !port)
207 continue;
208
209 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
210 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
211 tty_insert_flip_char(port, ch, flag);
212 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
213 tty_insert_flip_char(port, 0, TTY_OVERRUN);
214 }
215
216 if (saw_console_brk)
217 sun_do_break();
218
219 return port;
220}
221
222static void sunsab_stop_tx(struct uart_port *);
223static void sunsab_tx_idle(struct uart_sunsab_port *);
224
225static void transmit_chars(struct uart_sunsab_port *up,
226 union sab82532_irq_status *stat)
227{
228 struct circ_buf *xmit = &up->port.state->xmit;
229 int i;
230
231 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
232 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
233 writeb(up->interrupt_mask1, &up->regs->w.imr1);
234 set_bit(SAB82532_ALLS, &up->irqflags);
235 }
236
237#if 0 /* bde@nwlink.com says this check causes problems */
238 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
239 return;
240#endif
241
242 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
243 return;
244
245 set_bit(SAB82532_XPR, &up->irqflags);
246 sunsab_tx_idle(up);
247
248 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
249 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
250 writeb(up->interrupt_mask1, &up->regs->w.imr1);
251 return;
252 }
253
254 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
255 writeb(up->interrupt_mask1, &up->regs->w.imr1);
256 clear_bit(SAB82532_ALLS, &up->irqflags);
257
258 /* Stuff 32 bytes into Transmit FIFO. */
259 clear_bit(SAB82532_XPR, &up->irqflags);
260 for (i = 0; i < up->port.fifosize; i++) {
261 writeb(xmit->buf[xmit->tail],
262 &up->regs->w.xfifo[i]);
263 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
264 up->port.icount.tx++;
265 if (uart_circ_empty(xmit))
266 break;
267 }
268
269 /* Issue a Transmit Frame command. */
270 sunsab_cec_wait(up);
271 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
272
273 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
274 uart_write_wakeup(&up->port);
275
276 if (uart_circ_empty(xmit))
277 sunsab_stop_tx(&up->port);
278}
279
280static void check_status(struct uart_sunsab_port *up,
281 union sab82532_irq_status *stat)
282{
283 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
284 uart_handle_dcd_change(&up->port,
285 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
286
287 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
288 uart_handle_cts_change(&up->port,
289 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
290
291 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
292 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
293 up->port.icount.dsr++;
294 }
295
296 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
297}
298
299static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
300{
301 struct uart_sunsab_port *up = dev_id;
302 struct tty_port *port = NULL;
303 union sab82532_irq_status status;
304 unsigned long flags;
305 unsigned char gis;
306
307 spin_lock_irqsave(&up->port.lock, flags);
308
309 status.stat = 0;
310 gis = readb(&up->regs->r.gis) >> up->gis_shift;
311 if (gis & 1)
312 status.sreg.isr0 = readb(&up->regs->r.isr0);
313 if (gis & 2)
314 status.sreg.isr1 = readb(&up->regs->r.isr1);
315
316 if (status.stat) {
317 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
318 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
319 (status.sreg.isr1 & SAB82532_ISR1_BRK))
320 port = receive_chars(up, &status);
321 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
322 (status.sreg.isr1 & SAB82532_ISR1_CSC))
323 check_status(up, &status);
324 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
325 transmit_chars(up, &status);
326 }
327
328 spin_unlock_irqrestore(&up->port.lock, flags);
329
330 if (port)
331 tty_flip_buffer_push(port);
332
333 return IRQ_HANDLED;
334}
335
336/* port->lock is not held. */
337static unsigned int sunsab_tx_empty(struct uart_port *port)
338{
339 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
340 int ret;
341
342 /* Do not need a lock for a state test like this. */
343 if (test_bit(SAB82532_ALLS, &up->irqflags))
344 ret = TIOCSER_TEMT;
345 else
346 ret = 0;
347
348 return ret;
349}
350
351/* port->lock held by caller. */
352static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
353{
354 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
355
356 if (mctrl & TIOCM_RTS) {
357 up->cached_mode &= ~SAB82532_MODE_FRTS;
358 up->cached_mode |= SAB82532_MODE_RTS;
359 } else {
360 up->cached_mode |= (SAB82532_MODE_FRTS |
361 SAB82532_MODE_RTS);
362 }
363 if (mctrl & TIOCM_DTR) {
364 up->cached_pvr &= ~(up->pvr_dtr_bit);
365 } else {
366 up->cached_pvr |= up->pvr_dtr_bit;
367 }
368
369 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
370 if (test_bit(SAB82532_XPR, &up->irqflags))
371 sunsab_tx_idle(up);
372}
373
374/* port->lock is held by caller and interrupts are disabled. */
375static unsigned int sunsab_get_mctrl(struct uart_port *port)
376{
377 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
378 unsigned char val;
379 unsigned int result;
380
381 result = 0;
382
383 val = readb(&up->regs->r.pvr);
384 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
385
386 val = readb(&up->regs->r.vstr);
387 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
388
389 val = readb(&up->regs->r.star);
390 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
391
392 return result;
393}
394
395/* port->lock held by caller. */
396static void sunsab_stop_tx(struct uart_port *port)
397{
398 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
399
400 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
401 writeb(up->interrupt_mask1, &up->regs->w.imr1);
402}
403
404/* port->lock held by caller. */
405static void sunsab_tx_idle(struct uart_sunsab_port *up)
406{
407 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
408 u8 tmp;
409
410 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
411 writeb(up->cached_mode, &up->regs->rw.mode);
412 writeb(up->cached_pvr, &up->regs->rw.pvr);
413 writeb(up->cached_dafo, &up->regs->w.dafo);
414
415 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
416 tmp = readb(&up->regs->rw.ccr2);
417 tmp &= ~0xc0;
418 tmp |= (up->cached_ebrg >> 2) & 0xc0;
419 writeb(tmp, &up->regs->rw.ccr2);
420 }
421}
422
423/* port->lock held by caller. */
424static void sunsab_start_tx(struct uart_port *port)
425{
426 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
427 struct circ_buf *xmit = &up->port.state->xmit;
428 int i;
429
430 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
431 writeb(up->interrupt_mask1, &up->regs->w.imr1);
432
433 if (!test_bit(SAB82532_XPR, &up->irqflags))
434 return;
435
436 clear_bit(SAB82532_ALLS, &up->irqflags);
437 clear_bit(SAB82532_XPR, &up->irqflags);
438
439 for (i = 0; i < up->port.fifosize; i++) {
440 writeb(xmit->buf[xmit->tail],
441 &up->regs->w.xfifo[i]);
442 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
443 up->port.icount.tx++;
444 if (uart_circ_empty(xmit))
445 break;
446 }
447
448 /* Issue a Transmit Frame command. */
449 sunsab_cec_wait(up);
450 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
451}
452
453/* port->lock is not held. */
454static void sunsab_send_xchar(struct uart_port *port, char ch)
455{
456 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
457 unsigned long flags;
458
459 spin_lock_irqsave(&up->port.lock, flags);
460
461 sunsab_tec_wait(up);
462 writeb(ch, &up->regs->w.tic);
463
464 spin_unlock_irqrestore(&up->port.lock, flags);
465}
466
467/* port->lock held by caller. */
468static void sunsab_stop_rx(struct uart_port *port)
469{
470 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
471
472 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
473 writeb(up->interrupt_mask1, &up->regs->w.imr0);
474}
475
476/* port->lock held by caller. */
477static void sunsab_enable_ms(struct uart_port *port)
478{
479 /* For now we always receive these interrupts. */
480}
481
482/* port->lock is not held. */
483static void sunsab_break_ctl(struct uart_port *port, int break_state)
484{
485 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
486 unsigned long flags;
487 unsigned char val;
488
489 spin_lock_irqsave(&up->port.lock, flags);
490
491 val = up->cached_dafo;
492 if (break_state)
493 val |= SAB82532_DAFO_XBRK;
494 else
495 val &= ~SAB82532_DAFO_XBRK;
496 up->cached_dafo = val;
497
498 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
499 if (test_bit(SAB82532_XPR, &up->irqflags))
500 sunsab_tx_idle(up);
501
502 spin_unlock_irqrestore(&up->port.lock, flags);
503}
504
505/* port->lock is not held. */
506static int sunsab_startup(struct uart_port *port)
507{
508 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
509 unsigned long flags;
510 unsigned char tmp;
511 int err = request_irq(up->port.irq, sunsab_interrupt,
512 IRQF_SHARED, "sab", up);
513 if (err)
514 return err;
515
516 spin_lock_irqsave(&up->port.lock, flags);
517
518 /*
519 * Wait for any commands or immediate characters
520 */
521 sunsab_cec_wait(up);
522 sunsab_tec_wait(up);
523
524 /*
525 * Clear the FIFO buffers.
526 */
527 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
528 sunsab_cec_wait(up);
529 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
530
531 /*
532 * Clear the interrupt registers.
533 */
534 (void) readb(&up->regs->r.isr0);
535 (void) readb(&up->regs->r.isr1);
536
537 /*
538 * Now, initialize the UART
539 */
540 writeb(0, &up->regs->w.ccr0); /* power-down */
541 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
542 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
543 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
544 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
545 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
546 writeb(0, &up->regs->w.ccr3);
547 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
548 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
549 SAB82532_MODE_RAC);
550 writeb(up->cached_mode, &up->regs->w.mode);
551 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
552
553 tmp = readb(&up->regs->rw.ccr0);
554 tmp |= SAB82532_CCR0_PU; /* power-up */
555 writeb(tmp, &up->regs->rw.ccr0);
556
557 /*
558 * Finally, enable interrupts
559 */
560 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
561 SAB82532_IMR0_PLLA);
562 writeb(up->interrupt_mask0, &up->regs->w.imr0);
563 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
564 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
565 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
566 SAB82532_IMR1_XPR);
567 writeb(up->interrupt_mask1, &up->regs->w.imr1);
568 set_bit(SAB82532_ALLS, &up->irqflags);
569 set_bit(SAB82532_XPR, &up->irqflags);
570
571 spin_unlock_irqrestore(&up->port.lock, flags);
572
573 return 0;
574}
575
576/* port->lock is not held. */
577static void sunsab_shutdown(struct uart_port *port)
578{
579 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
580 unsigned long flags;
581
582 spin_lock_irqsave(&up->port.lock, flags);
583
584 /* Disable Interrupts */
585 up->interrupt_mask0 = 0xff;
586 writeb(up->interrupt_mask0, &up->regs->w.imr0);
587 up->interrupt_mask1 = 0xff;
588 writeb(up->interrupt_mask1, &up->regs->w.imr1);
589
590 /* Disable break condition */
591 up->cached_dafo = readb(&up->regs->rw.dafo);
592 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
593 writeb(up->cached_dafo, &up->regs->rw.dafo);
594
595 /* Disable Receiver */
596 up->cached_mode &= ~SAB82532_MODE_RAC;
597 writeb(up->cached_mode, &up->regs->rw.mode);
598
599 /*
600 * XXX FIXME
601 *
602 * If the chip is powered down here the system hangs/crashes during
603 * reboot or shutdown. This needs to be investigated further,
604 * similar behaviour occurs in 2.4 when the driver is configured
605 * as a module only. One hint may be that data is sometimes
606 * transmitted at 9600 baud during shutdown (regardless of the
607 * speed the chip was configured for when the port was open).
608 */
609#if 0
610 /* Power Down */
611 tmp = readb(&up->regs->rw.ccr0);
612 tmp &= ~SAB82532_CCR0_PU;
613 writeb(tmp, &up->regs->rw.ccr0);
614#endif
615
616 spin_unlock_irqrestore(&up->port.lock, flags);
617 free_irq(up->port.irq, up);
618}
619
620/*
621 * This is used to figure out the divisor speeds.
622 *
623 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
624 *
625 * with 0 <= N < 64 and 0 <= M < 16
626 */
627
628static void calc_ebrg(int baud, int *n_ret, int *m_ret)
629{
630 int n, m;
631
632 if (baud == 0) {
633 *n_ret = 0;
634 *m_ret = 0;
635 return;
636 }
637
638 /*
639 * We scale numbers by 10 so that we get better accuracy
640 * without having to use floating point. Here we increment m
641 * until n is within the valid range.
642 */
643 n = (SAB_BASE_BAUD * 10) / baud;
644 m = 0;
645 while (n >= 640) {
646 n = n / 2;
647 m++;
648 }
649 n = (n+5) / 10;
650 /*
651 * We try very hard to avoid speeds with M == 0 since they may
652 * not work correctly for XTAL frequences above 10 MHz.
653 */
654 if ((m == 0) && ((n & 1) == 0)) {
655 n = n / 2;
656 m++;
657 }
658 *n_ret = n - 1;
659 *m_ret = m;
660}
661
662/* Internal routine, port->lock is held and local interrupts are disabled. */
663static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
664 unsigned int iflag, unsigned int baud,
665 unsigned int quot)
666{
667 unsigned char dafo;
668 int bits, n, m;
669
670 /* Byte size and parity */
671 switch (cflag & CSIZE) {
672 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
673 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
674 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
675 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
676 /* Never happens, but GCC is too dumb to figure it out */
677 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
678 }
679
680 if (cflag & CSTOPB) {
681 dafo |= SAB82532_DAFO_STOP;
682 bits++;
683 }
684
685 if (cflag & PARENB) {
686 dafo |= SAB82532_DAFO_PARE;
687 bits++;
688 }
689
690 if (cflag & PARODD) {
691 dafo |= SAB82532_DAFO_PAR_ODD;
692 } else {
693 dafo |= SAB82532_DAFO_PAR_EVEN;
694 }
695 up->cached_dafo = dafo;
696
697 calc_ebrg(baud, &n, &m);
698
699 up->cached_ebrg = n | (m << 6);
700
701 up->tec_timeout = (10 * 1000000) / baud;
702 up->cec_timeout = up->tec_timeout >> 2;
703
704 /* CTS flow control flags */
705 /* We encode read_status_mask and ignore_status_mask like so:
706 *
707 * ---------------------
708 * | ... | ISR1 | ISR0 |
709 * ---------------------
710 * .. 15 8 7 0
711 */
712
713 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
714 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
715 SAB82532_ISR0_CDSC);
716 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
717 SAB82532_ISR1_ALLS |
718 SAB82532_ISR1_XPR) << 8;
719 if (iflag & INPCK)
720 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
721 SAB82532_ISR0_FERR);
722 if (iflag & (BRKINT | PARMRK))
723 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
724
725 /*
726 * Characteres to ignore
727 */
728 up->port.ignore_status_mask = 0;
729 if (iflag & IGNPAR)
730 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
731 SAB82532_ISR0_FERR);
732 if (iflag & IGNBRK) {
733 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
734 /*
735 * If we're ignoring parity and break indicators,
736 * ignore overruns too (for real raw support).
737 */
738 if (iflag & IGNPAR)
739 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
740 }
741
742 /*
743 * ignore all characters if CREAD is not set
744 */
745 if ((cflag & CREAD) == 0)
746 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
747 SAB82532_ISR0_TCD);
748
749 uart_update_timeout(&up->port, cflag,
750 (up->port.uartclk / (16 * quot)));
751
752 /* Now schedule a register update when the chip's
753 * transmitter is idle.
754 */
755 up->cached_mode |= SAB82532_MODE_RAC;
756 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
757 if (test_bit(SAB82532_XPR, &up->irqflags))
758 sunsab_tx_idle(up);
759}
760
761/* port->lock is not held. */
762static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
763 struct ktermios *old)
764{
765 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
766 unsigned long flags;
767 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
768 unsigned int quot = uart_get_divisor(port, baud);
769
770 spin_lock_irqsave(&up->port.lock, flags);
771 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
772 spin_unlock_irqrestore(&up->port.lock, flags);
773}
774
775static const char *sunsab_type(struct uart_port *port)
776{
777 struct uart_sunsab_port *up = (void *)port;
778 static char buf[36];
779
780 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
781 return buf;
782}
783
784static void sunsab_release_port(struct uart_port *port)
785{
786}
787
788static int sunsab_request_port(struct uart_port *port)
789{
790 return 0;
791}
792
793static void sunsab_config_port(struct uart_port *port, int flags)
794{
795}
796
797static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
798{
799 return -EINVAL;
800}
801
802static struct uart_ops sunsab_pops = {
803 .tx_empty = sunsab_tx_empty,
804 .set_mctrl = sunsab_set_mctrl,
805 .get_mctrl = sunsab_get_mctrl,
806 .stop_tx = sunsab_stop_tx,
807 .start_tx = sunsab_start_tx,
808 .send_xchar = sunsab_send_xchar,
809 .stop_rx = sunsab_stop_rx,
810 .enable_ms = sunsab_enable_ms,
811 .break_ctl = sunsab_break_ctl,
812 .startup = sunsab_startup,
813 .shutdown = sunsab_shutdown,
814 .set_termios = sunsab_set_termios,
815 .type = sunsab_type,
816 .release_port = sunsab_release_port,
817 .request_port = sunsab_request_port,
818 .config_port = sunsab_config_port,
819 .verify_port = sunsab_verify_port,
820};
821
822static struct uart_driver sunsab_reg = {
823 .owner = THIS_MODULE,
824 .driver_name = "sunsab",
825 .dev_name = "ttyS",
826 .major = TTY_MAJOR,
827};
828
829static struct uart_sunsab_port *sunsab_ports;
830
831#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
832
833static void sunsab_console_putchar(struct uart_port *port, int c)
834{
835 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
836
837 sunsab_tec_wait(up);
838 writeb(c, &up->regs->w.tic);
839}
840
841static void sunsab_console_write(struct console *con, const char *s, unsigned n)
842{
843 struct uart_sunsab_port *up = &sunsab_ports[con->index];
844 unsigned long flags;
845 int locked = 1;
846
847 if (up->port.sysrq || oops_in_progress)
848 locked = spin_trylock_irqsave(&up->port.lock, flags);
849 else
850 spin_lock_irqsave(&up->port.lock, flags);
851
852 uart_console_write(&up->port, s, n, sunsab_console_putchar);
853 sunsab_tec_wait(up);
854
855 if (locked)
856 spin_unlock_irqrestore(&up->port.lock, flags);
857}
858
859static int sunsab_console_setup(struct console *con, char *options)
860{
861 struct uart_sunsab_port *up = &sunsab_ports[con->index];
862 unsigned long flags;
863 unsigned int baud, quot;
864
865 /*
866 * The console framework calls us for each and every port
867 * registered. Defer the console setup until the requested
868 * port has been properly discovered. A bit of a hack,
869 * though...
870 */
871 if (up->port.type != PORT_SUNSAB)
872 return -1;
873
874 printk("Console: ttyS%d (SAB82532)\n",
875 (sunsab_reg.minor - 64) + con->index);
876
877 sunserial_console_termios(con, up->port.dev->of_node);
878
879 switch (con->cflag & CBAUD) {
880 case B150: baud = 150; break;
881 case B300: baud = 300; break;
882 case B600: baud = 600; break;
883 case B1200: baud = 1200; break;
884 case B2400: baud = 2400; break;
885 case B4800: baud = 4800; break;
886 default: case B9600: baud = 9600; break;
887 case B19200: baud = 19200; break;
888 case B38400: baud = 38400; break;
889 case B57600: baud = 57600; break;
890 case B115200: baud = 115200; break;
891 case B230400: baud = 230400; break;
892 case B460800: baud = 460800; break;
893 }
894
895 /*
896 * Temporary fix.
897 */
898 spin_lock_init(&up->port.lock);
899
900 /*
901 * Initialize the hardware
902 */
903 sunsab_startup(&up->port);
904
905 spin_lock_irqsave(&up->port.lock, flags);
906
907 /*
908 * Finally, enable interrupts
909 */
910 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
911 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
912 writeb(up->interrupt_mask0, &up->regs->w.imr0);
913 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
914 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
915 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
916 SAB82532_IMR1_XPR;
917 writeb(up->interrupt_mask1, &up->regs->w.imr1);
918
919 quot = uart_get_divisor(&up->port, baud);
920 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
921 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
922
923 spin_unlock_irqrestore(&up->port.lock, flags);
924
925 return 0;
926}
927
928static struct console sunsab_console = {
929 .name = "ttyS",
930 .write = sunsab_console_write,
931 .device = uart_console_device,
932 .setup = sunsab_console_setup,
933 .flags = CON_PRINTBUFFER,
934 .index = -1,
935 .data = &sunsab_reg,
936};
937
938static inline struct console *SUNSAB_CONSOLE(void)
939{
940 return &sunsab_console;
941}
942#else
943#define SUNSAB_CONSOLE() (NULL)
944#define sunsab_console_init() do { } while (0)
945#endif
946
947static int sunsab_init_one(struct uart_sunsab_port *up,
948 struct platform_device *op,
949 unsigned long offset,
950 int line)
951{
952 up->port.line = line;
953 up->port.dev = &op->dev;
954
955 up->port.mapbase = op->resource[0].start + offset;
956 up->port.membase = of_ioremap(&op->resource[0], offset,
957 sizeof(union sab82532_async_regs),
958 "sab");
959 if (!up->port.membase)
960 return -ENOMEM;
961 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
962
963 up->port.irq = op->archdata.irqs[0];
964
965 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
966 up->port.iotype = UPIO_MEM;
967
968 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
969
970 up->port.ops = &sunsab_pops;
971 up->port.type = PORT_SUNSAB;
972 up->port.uartclk = SAB_BASE_BAUD;
973
974 up->type = readb(&up->regs->r.vstr) & 0x0f;
975 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
976 writeb(0xff, &up->regs->w.pim);
977 if ((up->port.line & 0x1) == 0) {
978 up->pvr_dsr_bit = (1 << 0);
979 up->pvr_dtr_bit = (1 << 1);
980 up->gis_shift = 2;
981 } else {
982 up->pvr_dsr_bit = (1 << 3);
983 up->pvr_dtr_bit = (1 << 2);
984 up->gis_shift = 0;
985 }
986 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
987 writeb(up->cached_pvr, &up->regs->w.pvr);
988 up->cached_mode = readb(&up->regs->rw.mode);
989 up->cached_mode |= SAB82532_MODE_FRTS;
990 writeb(up->cached_mode, &up->regs->rw.mode);
991 up->cached_mode |= SAB82532_MODE_RTS;
992 writeb(up->cached_mode, &up->regs->rw.mode);
993
994 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
995 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
996
997 return 0;
998}
999
1000static int sab_probe(struct platform_device *op)
1001{
1002 static int inst;
1003 struct uart_sunsab_port *up;
1004 int err;
1005
1006 up = &sunsab_ports[inst * 2];
1007
1008 err = sunsab_init_one(&up[0], op,
1009 0,
1010 (inst * 2) + 0);
1011 if (err)
1012 goto out;
1013
1014 err = sunsab_init_one(&up[1], op,
1015 sizeof(union sab82532_async_regs),
1016 (inst * 2) + 1);
1017 if (err)
1018 goto out1;
1019
1020 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1021 &sunsab_reg, up[0].port.line,
1022 false);
1023
1024 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1025 &sunsab_reg, up[1].port.line,
1026 false);
1027
1028 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1029 if (err)
1030 goto out2;
1031
1032 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1033 if (err)
1034 goto out3;
1035
1036 platform_set_drvdata(op, &up[0]);
1037
1038 inst++;
1039
1040 return 0;
1041
1042out3:
1043 uart_remove_one_port(&sunsab_reg, &up[0].port);
1044out2:
1045 of_iounmap(&op->resource[0],
1046 up[1].port.membase,
1047 sizeof(union sab82532_async_regs));
1048out1:
1049 of_iounmap(&op->resource[0],
1050 up[0].port.membase,
1051 sizeof(union sab82532_async_regs));
1052out:
1053 return err;
1054}
1055
1056static int sab_remove(struct platform_device *op)
1057{
1058 struct uart_sunsab_port *up = platform_get_drvdata(op);
1059
1060 uart_remove_one_port(&sunsab_reg, &up[1].port);
1061 uart_remove_one_port(&sunsab_reg, &up[0].port);
1062 of_iounmap(&op->resource[0],
1063 up[1].port.membase,
1064 sizeof(union sab82532_async_regs));
1065 of_iounmap(&op->resource[0],
1066 up[0].port.membase,
1067 sizeof(union sab82532_async_regs));
1068
1069 return 0;
1070}
1071
1072static const struct of_device_id sab_match[] = {
1073 {
1074 .name = "se",
1075 },
1076 {
1077 .name = "serial",
1078 .compatible = "sab82532",
1079 },
1080 {},
1081};
1082MODULE_DEVICE_TABLE(of, sab_match);
1083
1084static struct platform_driver sab_driver = {
1085 .driver = {
1086 .name = "sab",
1087 .owner = THIS_MODULE,
1088 .of_match_table = sab_match,
1089 },
1090 .probe = sab_probe,
1091 .remove = sab_remove,
1092};
1093
1094static int __init sunsab_init(void)
1095{
1096 struct device_node *dp;
1097 int err;
1098 int num_channels = 0;
1099
1100 for_each_node_by_name(dp, "se")
1101 num_channels += 2;
1102 for_each_node_by_name(dp, "serial") {
1103 if (of_device_is_compatible(dp, "sab82532"))
1104 num_channels += 2;
1105 }
1106
1107 if (num_channels) {
1108 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1109 num_channels, GFP_KERNEL);
1110 if (!sunsab_ports)
1111 return -ENOMEM;
1112
1113 err = sunserial_register_minors(&sunsab_reg, num_channels);
1114 if (err) {
1115 kfree(sunsab_ports);
1116 sunsab_ports = NULL;
1117
1118 return err;
1119 }
1120 }
1121
1122 return platform_driver_register(&sab_driver);
1123}
1124
1125static void __exit sunsab_exit(void)
1126{
1127 platform_driver_unregister(&sab_driver);
1128 if (sunsab_reg.nr) {
1129 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1130 }
1131
1132 kfree(sunsab_ports);
1133 sunsab_ports = NULL;
1134}
1135
1136module_init(sunsab_init);
1137module_exit(sunsab_exit);
1138
1139MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1140MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1141MODULE_LICENSE("GPL");