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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel Low Power Subsystem PWM controller driver
4 *
5 * Copyright (C) 2014, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
8 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
9 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
10 * Author: Alan Cox <alan@linux.intel.com>
11 */
12
13#include <linux/bits.h>
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/iopoll.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/pm_runtime.h>
20#include <linux/time.h>
21
22#define DEFAULT_SYMBOL_NAMESPACE PWM_LPSS
23
24#include "pwm-lpss.h"
25
26#define PWM 0x00000000
27#define PWM_ENABLE BIT(31)
28#define PWM_SW_UPDATE BIT(30)
29#define PWM_BASE_UNIT_SHIFT 8
30#define PWM_ON_TIME_DIV_MASK GENMASK(7, 0)
31
32/* Size of each PWM register space if multiple */
33#define PWM_SIZE 0x400
34
35/* BayTrail */
36const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
37 .clk_rate = 25000000,
38 .npwm = 1,
39 .base_unit_bits = 16,
40};
41EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
42
43/* Braswell */
44const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
45 .clk_rate = 19200000,
46 .npwm = 1,
47 .base_unit_bits = 16,
48 .other_devices_aml_touches_pwm_regs = true,
49};
50EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
51
52/* Broxton */
53const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
54 .clk_rate = 19200000,
55 .npwm = 4,
56 .base_unit_bits = 22,
57 .bypass = true,
58};
59EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
60
61/* Tangier */
62const struct pwm_lpss_boardinfo pwm_lpss_tng_info = {
63 .clk_rate = 19200000,
64 .npwm = 4,
65 .base_unit_bits = 22,
66};
67EXPORT_SYMBOL_GPL(pwm_lpss_tng_info);
68
69static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
70{
71 return container_of(chip, struct pwm_lpss_chip, chip);
72}
73
74static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
75{
76 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
77
78 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
79}
80
81static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
82{
83 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
84
85 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
86}
87
88static int pwm_lpss_wait_for_update(struct pwm_device *pwm)
89{
90 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
91 const void __iomem *addr = lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM;
92 const unsigned int ms = 500 * USEC_PER_MSEC;
93 u32 val;
94 int err;
95
96 /*
97 * PWM Configuration register has SW_UPDATE bit that is set when a new
98 * configuration is written to the register. The bit is automatically
99 * cleared at the start of the next output cycle by the IP block.
100 *
101 * If one writes a new configuration to the register while it still has
102 * the bit enabled, PWM may freeze. That is, while one can still write
103 * to the register, it won't have an effect. Thus, we try to sleep long
104 * enough that the bit gets cleared and make sure the bit is not
105 * enabled while we update the configuration.
106 */
107 err = readl_poll_timeout(addr, val, !(val & PWM_SW_UPDATE), 40, ms);
108 if (err)
109 dev_err(pwm->chip->dev, "PWM_SW_UPDATE was not cleared\n");
110
111 return err;
112}
113
114static inline int pwm_lpss_is_updating(struct pwm_device *pwm)
115{
116 if (pwm_lpss_read(pwm) & PWM_SW_UPDATE) {
117 dev_err(pwm->chip->dev, "PWM_SW_UPDATE is still set, skipping update\n");
118 return -EBUSY;
119 }
120
121 return 0;
122}
123
124static void pwm_lpss_prepare(struct pwm_lpss_chip *lpwm, struct pwm_device *pwm,
125 int duty_ns, int period_ns)
126{
127 unsigned long long on_time_div;
128 unsigned long c = lpwm->info->clk_rate, base_unit_range;
129 unsigned long long base_unit, freq = NSEC_PER_SEC;
130 u32 ctrl;
131
132 do_div(freq, period_ns);
133
134 /*
135 * The equation is:
136 * base_unit = round(base_unit_range * freq / c)
137 */
138 base_unit_range = BIT(lpwm->info->base_unit_bits);
139 freq *= base_unit_range;
140
141 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c);
142 /* base_unit must not be 0 and we also want to avoid overflowing it */
143 base_unit = clamp_val(base_unit, 1, base_unit_range - 1);
144
145 on_time_div = 255ULL * duty_ns;
146 do_div(on_time_div, period_ns);
147 on_time_div = 255ULL - on_time_div;
148
149 ctrl = pwm_lpss_read(pwm);
150 ctrl &= ~PWM_ON_TIME_DIV_MASK;
151 ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT);
152 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT;
153 ctrl |= on_time_div;
154
155 pwm_lpss_write(pwm, ctrl);
156 pwm_lpss_write(pwm, ctrl | PWM_SW_UPDATE);
157}
158
159static inline void pwm_lpss_cond_enable(struct pwm_device *pwm, bool cond)
160{
161 if (cond)
162 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
163}
164
165static int pwm_lpss_prepare_enable(struct pwm_lpss_chip *lpwm,
166 struct pwm_device *pwm,
167 const struct pwm_state *state)
168{
169 int ret;
170
171 ret = pwm_lpss_is_updating(pwm);
172 if (ret)
173 return ret;
174
175 pwm_lpss_prepare(lpwm, pwm, state->duty_cycle, state->period);
176 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == false);
177 ret = pwm_lpss_wait_for_update(pwm);
178 if (ret)
179 return ret;
180
181 pwm_lpss_cond_enable(pwm, lpwm->info->bypass == true);
182 return 0;
183}
184
185static int pwm_lpss_apply(struct pwm_chip *chip, struct pwm_device *pwm,
186 const struct pwm_state *state)
187{
188 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
189 int ret = 0;
190
191 if (state->enabled) {
192 if (!pwm_is_enabled(pwm)) {
193 pm_runtime_get_sync(chip->dev);
194 ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
195 if (ret)
196 pm_runtime_put(chip->dev);
197 } else {
198 ret = pwm_lpss_prepare_enable(lpwm, pwm, state);
199 }
200 } else if (pwm_is_enabled(pwm)) {
201 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
202 pm_runtime_put(chip->dev);
203 }
204
205 return ret;
206}
207
208static int pwm_lpss_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
209 struct pwm_state *state)
210{
211 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
212 unsigned long base_unit_range;
213 unsigned long long base_unit, freq, on_time_div;
214 u32 ctrl;
215
216 pm_runtime_get_sync(chip->dev);
217
218 base_unit_range = BIT(lpwm->info->base_unit_bits);
219
220 ctrl = pwm_lpss_read(pwm);
221 on_time_div = 255 - (ctrl & PWM_ON_TIME_DIV_MASK);
222 base_unit = (ctrl >> PWM_BASE_UNIT_SHIFT) & (base_unit_range - 1);
223
224 freq = base_unit * lpwm->info->clk_rate;
225 do_div(freq, base_unit_range);
226 if (freq == 0)
227 state->period = NSEC_PER_SEC;
228 else
229 state->period = NSEC_PER_SEC / (unsigned long)freq;
230
231 on_time_div *= state->period;
232 do_div(on_time_div, 255);
233 state->duty_cycle = on_time_div;
234
235 state->polarity = PWM_POLARITY_NORMAL;
236 state->enabled = !!(ctrl & PWM_ENABLE);
237
238 pm_runtime_put(chip->dev);
239
240 return 0;
241}
242
243static const struct pwm_ops pwm_lpss_ops = {
244 .apply = pwm_lpss_apply,
245 .get_state = pwm_lpss_get_state,
246 .owner = THIS_MODULE,
247};
248
249struct pwm_lpss_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base,
250 const struct pwm_lpss_boardinfo *info)
251{
252 struct pwm_lpss_chip *lpwm;
253 unsigned long c;
254 int i, ret;
255 u32 ctrl;
256
257 if (WARN_ON(info->npwm > LPSS_MAX_PWMS))
258 return ERR_PTR(-ENODEV);
259
260 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
261 if (!lpwm)
262 return ERR_PTR(-ENOMEM);
263
264 lpwm->regs = base;
265 lpwm->info = info;
266
267 c = lpwm->info->clk_rate;
268 if (!c)
269 return ERR_PTR(-EINVAL);
270
271 lpwm->chip.dev = dev;
272 lpwm->chip.ops = &pwm_lpss_ops;
273 lpwm->chip.npwm = info->npwm;
274
275 ret = devm_pwmchip_add(dev, &lpwm->chip);
276 if (ret) {
277 dev_err(dev, "failed to add PWM chip: %d\n", ret);
278 return ERR_PTR(ret);
279 }
280
281 for (i = 0; i < lpwm->info->npwm; i++) {
282 ctrl = pwm_lpss_read(&lpwm->chip.pwms[i]);
283 if (ctrl & PWM_ENABLE)
284 pm_runtime_get(dev);
285 }
286
287 return lpwm;
288}
289EXPORT_SYMBOL_GPL(devm_pwm_lpss_probe);
290
291MODULE_DESCRIPTION("PWM driver for Intel LPSS");
292MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
293MODULE_LICENSE("GPL v2");
1/*
2 * Intel Low Power Subsystem PWM controller driver
3 *
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 * Author: Chew Kean Ho <kean.ho.chew@intel.com>
7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/acpi.h>
16#include <linux/clk.h>
17#include <linux/device.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pwm.h>
21#include <linux/platform_device.h>
22
23#define PWM 0x00000000
24#define PWM_ENABLE BIT(31)
25#define PWM_SW_UPDATE BIT(30)
26#define PWM_BASE_UNIT_SHIFT 8
27#define PWM_BASE_UNIT_MASK 0x00ffff00
28#define PWM_ON_TIME_DIV_MASK 0x000000ff
29#define PWM_DIVISION_CORRECTION 0x2
30#define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION)
31#define NSECS_PER_SEC 1000000000UL
32
33struct pwm_lpss_chip {
34 struct pwm_chip chip;
35 void __iomem *regs;
36 struct clk *clk;
37};
38
39static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
40{
41 return container_of(chip, struct pwm_lpss_chip, chip);
42}
43
44static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
45 int duty_ns, int period_ns)
46{
47 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
48 u8 on_time_div;
49 unsigned long c;
50 unsigned long long base_unit, freq = NSECS_PER_SEC;
51 u32 ctrl;
52
53 do_div(freq, period_ns);
54
55 /* The equation is: base_unit = ((freq / c) * 65536) + correction */
56 base_unit = freq * 65536;
57
58 c = clk_get_rate(lpwm->clk);
59 if (!c)
60 return -EINVAL;
61
62 do_div(base_unit, c);
63 base_unit += PWM_DIVISION_CORRECTION;
64 if (base_unit > PWM_LIMIT)
65 return -EINVAL;
66
67 if (duty_ns <= 0)
68 duty_ns = 1;
69 on_time_div = 255 - (255 * duty_ns / period_ns);
70
71 ctrl = readl(lpwm->regs + PWM);
72 ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
73 ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
74 ctrl |= on_time_div;
75 /* request PWM to update on next cycle */
76 ctrl |= PWM_SW_UPDATE;
77 writel(ctrl, lpwm->regs + PWM);
78
79 return 0;
80}
81
82static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
83{
84 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
85 u32 ctrl;
86 int ret;
87
88 ret = clk_prepare_enable(lpwm->clk);
89 if (ret)
90 return ret;
91
92 ctrl = readl(lpwm->regs + PWM);
93 writel(ctrl | PWM_ENABLE, lpwm->regs + PWM);
94
95 return 0;
96}
97
98static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
99{
100 struct pwm_lpss_chip *lpwm = to_lpwm(chip);
101 u32 ctrl;
102
103 ctrl = readl(lpwm->regs + PWM);
104 writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
105
106 clk_disable_unprepare(lpwm->clk);
107}
108
109static const struct pwm_ops pwm_lpss_ops = {
110 .config = pwm_lpss_config,
111 .enable = pwm_lpss_enable,
112 .disable = pwm_lpss_disable,
113 .owner = THIS_MODULE,
114};
115
116static const struct acpi_device_id pwm_lpss_acpi_match[] = {
117 { "80860F09", 0 },
118 { },
119};
120MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match);
121
122static int pwm_lpss_probe(struct platform_device *pdev)
123{
124 struct pwm_lpss_chip *lpwm;
125 struct resource *r;
126 int ret;
127
128 lpwm = devm_kzalloc(&pdev->dev, sizeof(*lpwm), GFP_KERNEL);
129 if (!lpwm)
130 return -ENOMEM;
131
132 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133
134 lpwm->regs = devm_ioremap_resource(&pdev->dev, r);
135 if (IS_ERR(lpwm->regs))
136 return PTR_ERR(lpwm->regs);
137
138 lpwm->clk = devm_clk_get(&pdev->dev, NULL);
139 if (IS_ERR(lpwm->clk)) {
140 dev_err(&pdev->dev, "failed to get PWM clock\n");
141 return PTR_ERR(lpwm->clk);
142 }
143
144 lpwm->chip.dev = &pdev->dev;
145 lpwm->chip.ops = &pwm_lpss_ops;
146 lpwm->chip.base = -1;
147 lpwm->chip.npwm = 1;
148
149 ret = pwmchip_add(&lpwm->chip);
150 if (ret) {
151 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
152 return ret;
153 }
154
155 platform_set_drvdata(pdev, lpwm);
156 return 0;
157}
158
159static int pwm_lpss_remove(struct platform_device *pdev)
160{
161 struct pwm_lpss_chip *lpwm = platform_get_drvdata(pdev);
162 u32 ctrl;
163
164 ctrl = readl(lpwm->regs + PWM);
165 writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM);
166
167 return pwmchip_remove(&lpwm->chip);
168}
169
170static struct platform_driver pwm_lpss_driver = {
171 .driver = {
172 .name = "pwm-lpss",
173 .acpi_match_table = pwm_lpss_acpi_match,
174 },
175 .probe = pwm_lpss_probe,
176 .remove = pwm_lpss_remove,
177};
178module_platform_driver(pwm_lpss_driver);
179
180MODULE_DESCRIPTION("PWM driver for Intel LPSS");
181MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
182MODULE_LICENSE("GPL v2");
183MODULE_ALIAS("platform:pwm-lpss");