1/*
  2 * Copyright (c) 2010 Broadcom Corporation
  3 *
  4 * Permission to use, copy, modify, and/or distribute this software for any
  5 * purpose with or without fee is hereby granted, provided that the above
  6 * copyright notice and this permission notice appear in all copies.
  7 *
  8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 15 */
 16
 17/*
 18 * phy_shim.h: stuff defined in phy_shim.c and included only by the phy
 19 */
 20
 21#ifndef _BRCM_PHY_SHIM_H_
 22#define _BRCM_PHY_SHIM_H_
 23
 24#include "types.h"
 25
 26#define RADAR_TYPE_NONE		0	/* Radar type None */
 27#define RADAR_TYPE_ETSI_1	1	/* ETSI 1 Radar type */
 28#define RADAR_TYPE_ETSI_2	2	/* ETSI 2 Radar type */
 29#define RADAR_TYPE_ETSI_3	3	/* ETSI 3 Radar type */
 30#define RADAR_TYPE_ITU_E	4	/* ITU E Radar type */
 31#define RADAR_TYPE_ITU_K	5	/* ITU K Radar type */
 32#define RADAR_TYPE_UNCLASSIFIED	6	/* Unclassified Radar type  */
 33#define RADAR_TYPE_BIN5		7	/* long pulse radar type */
 34#define RADAR_TYPE_STG2		8	/* staggered-2 radar */
 35#define RADAR_TYPE_STG3		9	/* staggered-3 radar */
 36#define RADAR_TYPE_FRA		10	/* French radar */
 37
 38/* French radar pulse widths */
 39#define FRA_T1_20MHZ	52770
 40#define FRA_T2_20MHZ	61538
 41#define FRA_T3_20MHZ	66002
 42#define FRA_T1_40MHZ	105541
 43#define FRA_T2_40MHZ	123077
 44#define FRA_T3_40MHZ	132004
 45#define FRA_ERR_20MHZ	60
 46#define FRA_ERR_40MHZ	120
 47
 48#define ANTSEL_NA		0 /* No boardlevel selection available */
 49#define ANTSEL_2x4		1 /* 2x4 boardlevel selection available */
 50#define ANTSEL_2x3		2 /* 2x3 CB2 boardlevel selection available */
 51
 52/* Rx Antenna diversity control values */
 53#define	ANT_RX_DIV_FORCE_0	0	/* Use antenna 0 */
 54#define	ANT_RX_DIV_FORCE_1	1	/* Use antenna 1 */
 55#define	ANT_RX_DIV_START_1	2	/* Choose starting with 1 */
 56#define	ANT_RX_DIV_START_0	3	/* Choose starting with 0 */
 57#define	ANT_RX_DIV_ENABLE	3	/* APHY bbConfig Enable RX Diversity */
 58#define ANT_RX_DIV_DEF		ANT_RX_DIV_START_0 /* default antdiv setting */
 59
 60#define WL_ANT_RX_MAX		2	/* max 2 receive antennas */
 61#define WL_ANT_HT_RX_MAX	3	/* max 3 receive antennas/cores */
 62#define WL_ANT_IDX_1		0	/* antenna index 1 */
 63#define WL_ANT_IDX_2		1	/* antenna index 2 */
 64
 65/* values for n_preamble_type */
 66#define BRCMS_N_PREAMBLE_MIXEDMODE	0
 67#define BRCMS_N_PREAMBLE_GF		1
 68#define BRCMS_N_PREAMBLE_GF_BRCM          2
 69
 70#define WL_TX_POWER_RATES_LEGACY	45
 71#define WL_TX_POWER_MCS20_FIRST	        12
 72#define WL_TX_POWER_MCS20_NUM	        16
 73#define WL_TX_POWER_MCS40_FIRST	        28
 74#define WL_TX_POWER_MCS40_NUM	        17
 75
 76
 77#define WL_TX_POWER_RATES	       101
 78#define WL_TX_POWER_CCK_FIRST	       0
 79#define WL_TX_POWER_CCK_NUM	       4
 80/* Index for first 20MHz OFDM SISO rate */
 81#define WL_TX_POWER_OFDM_FIRST	       4
 82/* Index for first 20MHz OFDM CDD rate */
 83#define WL_TX_POWER_OFDM20_CDD_FIRST   12
 84/* Index for first 40MHz OFDM SISO rate */
 85#define WL_TX_POWER_OFDM40_SISO_FIRST  52
 86/* Index for first 40MHz OFDM CDD rate */
 87#define WL_TX_POWER_OFDM40_CDD_FIRST   60
 88#define WL_TX_POWER_OFDM_NUM	       8
 89/* Index for first 20MHz MCS SISO rate */
 90#define WL_TX_POWER_MCS20_SISO_FIRST   20
 91/* Index for first 20MHz MCS CDD rate */
 92#define WL_TX_POWER_MCS20_CDD_FIRST    28
 93/* Index for first 20MHz MCS STBC rate */
 94#define WL_TX_POWER_MCS20_STBC_FIRST   36
 95/* Index for first 20MHz MCS SDM rate */
 96#define WL_TX_POWER_MCS20_SDM_FIRST    44
 97/* Index for first 40MHz MCS SISO rate */
 98#define WL_TX_POWER_MCS40_SISO_FIRST   68
 99/* Index for first 40MHz MCS CDD rate */
100#define WL_TX_POWER_MCS40_CDD_FIRST    76
101/* Index for first 40MHz MCS STBC rate */
102#define WL_TX_POWER_MCS40_STBC_FIRST   84
103/* Index for first 40MHz MCS SDM rate */
104#define WL_TX_POWER_MCS40_SDM_FIRST    92
105#define WL_TX_POWER_MCS_1_STREAM_NUM   8
106#define WL_TX_POWER_MCS_2_STREAM_NUM   8
107/* Index for 40MHz rate MCS 32 */
108#define WL_TX_POWER_MCS_32	       100
109#define WL_TX_POWER_MCS_32_NUM	       1
110
111/* sslpnphy specifics */
112/* Index for first 20MHz MCS SISO rate */
113#define WL_TX_POWER_MCS20_SISO_FIRST_SSN   12
114
115/* struct tx_power::flags bits */
116#define WL_TX_POWER_F_ENABLED	1
117#define WL_TX_POWER_F_HW	2
118#define WL_TX_POWER_F_MIMO	4
119#define WL_TX_POWER_F_SISO	8
120
121/* values to force tx/rx chain */
122#define BRCMS_N_TXRX_CHAIN0		0
123#define BRCMS_N_TXRX_CHAIN1		1
124
125struct brcms_phy;
126
127struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw,
128					  struct brcms_info *wl,
129					  struct brcms_c_info *wlc);
130void wlc_phy_shim_detach(struct phy_shim_info *physhim);
131
132/* PHY to WL utility functions */
133struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim,
134				     void (*fn)(struct brcms_phy *pi),
135				     void *arg, const char *name);
136void wlapi_free_timer(struct wlapi_timer *t);
137void wlapi_add_timer(struct wlapi_timer *t, uint ms, int periodic);
138bool wlapi_del_timer(struct wlapi_timer *t);
139void wlapi_intrson(struct phy_shim_info *physhim);
140u32 wlapi_intrsoff(struct phy_shim_info *physhim);
141void wlapi_intrsrestore(struct phy_shim_info *physhim, u32 macintmask);
142
143void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v);
144u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset);
145void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, u16 val,
146		    int bands);
147void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags);
148void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim);
149void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode);
150void wlapi_enable_mac(struct phy_shim_info *physhim);
151void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val);
152void wlapi_bmac_phy_reset(struct phy_shim_info *physhim);
153void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw);
154void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk);
155void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk);
156void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on);
157void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim);
158void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim);
159void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim);
160void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int o,
161				   int len, void *buf);
162u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim, u8 rate);
163void wlapi_ucode_sample_init(struct phy_shim_info *physhim);
164void wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint, void *buf,
165			   int, u32 sel);
166void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint, const void *buf,
167			 int, u32);
168
169void wlapi_high_update_phy_mode(struct phy_shim_info *physhim, u32 phy_mode);
170u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
171
172#endif				/* _BRCM_PHY_SHIM_H_ */