Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
4 *
5 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
6 *
7 * Current driver maintained by Ben Dooks and Simtec Electronics
8 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
9 */
10
11#include <linux/module.h>
12#include <linux/dmaengine.h>
13#include <linux/dma-mapping.h>
14#include <linux/clk.h>
15#include <linux/mmc/host.h>
16#include <linux/platform_device.h>
17#include <linux/cpufreq.h>
18#include <linux/debugfs.h>
19#include <linux/seq_file.h>
20#include <linux/gpio/consumer.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/mmc/slot-gpio.h>
27#include <linux/platform_data/mmc-s3cmci.h>
28
29#include "s3cmci.h"
30
31#define DRIVER_NAME "s3c-mci"
32
33#define S3C2410_SDICON (0x00)
34#define S3C2410_SDIPRE (0x04)
35#define S3C2410_SDICMDARG (0x08)
36#define S3C2410_SDICMDCON (0x0C)
37#define S3C2410_SDICMDSTAT (0x10)
38#define S3C2410_SDIRSP0 (0x14)
39#define S3C2410_SDIRSP1 (0x18)
40#define S3C2410_SDIRSP2 (0x1C)
41#define S3C2410_SDIRSP3 (0x20)
42#define S3C2410_SDITIMER (0x24)
43#define S3C2410_SDIBSIZE (0x28)
44#define S3C2410_SDIDCON (0x2C)
45#define S3C2410_SDIDCNT (0x30)
46#define S3C2410_SDIDSTA (0x34)
47#define S3C2410_SDIFSTA (0x38)
48
49#define S3C2410_SDIDATA (0x3C)
50#define S3C2410_SDIIMSK (0x40)
51
52#define S3C2440_SDIDATA (0x40)
53#define S3C2440_SDIIMSK (0x3C)
54
55#define S3C2440_SDICON_SDRESET (1 << 8)
56#define S3C2410_SDICON_SDIOIRQ (1 << 3)
57#define S3C2410_SDICON_FIFORESET (1 << 1)
58#define S3C2410_SDICON_CLOCKTYPE (1 << 0)
59
60#define S3C2410_SDICMDCON_LONGRSP (1 << 10)
61#define S3C2410_SDICMDCON_WAITRSP (1 << 9)
62#define S3C2410_SDICMDCON_CMDSTART (1 << 8)
63#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
64#define S3C2410_SDICMDCON_INDEX (0x3f)
65
66#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
67#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
68#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
69#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
70
71#define S3C2440_SDIDCON_DS_WORD (2 << 22)
72#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
73#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
74#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
75#define S3C2410_SDIDCON_WIDEBUS (1 << 16)
76#define S3C2410_SDIDCON_DMAEN (1 << 15)
77#define S3C2410_SDIDCON_STOP (1 << 14)
78#define S3C2440_SDIDCON_DATSTART (1 << 14)
79
80#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
81#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
82
83#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
84
85#define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
86#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
87#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
88#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
89#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
90#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
91#define S3C2410_SDIDSTA_TXDATAON (1 << 1)
92#define S3C2410_SDIDSTA_RXDATAON (1 << 0)
93
94#define S3C2440_SDIFSTA_FIFORESET (1 << 16)
95#define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
96#define S3C2410_SDIFSTA_TFDET (1 << 13)
97#define S3C2410_SDIFSTA_RFDET (1 << 12)
98#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
99
100#define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
101#define S3C2410_SDIIMSK_CMDSENT (1 << 16)
102#define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
103#define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
104#define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
105#define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
106#define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
107#define S3C2410_SDIIMSK_DATACRC (1 << 9)
108#define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
109#define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
110#define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
111#define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
112#define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
113
114enum dbg_channels {
115 dbg_err = (1 << 0),
116 dbg_debug = (1 << 1),
117 dbg_info = (1 << 2),
118 dbg_irq = (1 << 3),
119 dbg_sg = (1 << 4),
120 dbg_dma = (1 << 5),
121 dbg_pio = (1 << 6),
122 dbg_fail = (1 << 7),
123 dbg_conf = (1 << 8),
124};
125
126static const int dbgmap_err = dbg_fail;
127static const int dbgmap_info = dbg_info | dbg_conf;
128static const int dbgmap_debug = dbg_err | dbg_debug;
129
130#define dbg(host, channels, args...) \
131 do { \
132 if (dbgmap_err & channels) \
133 dev_err(&host->pdev->dev, args); \
134 else if (dbgmap_info & channels) \
135 dev_info(&host->pdev->dev, args); \
136 else if (dbgmap_debug & channels) \
137 dev_dbg(&host->pdev->dev, args); \
138 } while (0)
139
140static void finalize_request(struct s3cmci_host *host);
141static void s3cmci_send_request(struct mmc_host *mmc);
142static void s3cmci_reset(struct s3cmci_host *host);
143
144#ifdef CONFIG_MMC_DEBUG
145
146static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
147{
148 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer;
149 u32 datcon, datcnt, datsta, fsta;
150
151 con = readl(host->base + S3C2410_SDICON);
152 pre = readl(host->base + S3C2410_SDIPRE);
153 cmdarg = readl(host->base + S3C2410_SDICMDARG);
154 cmdcon = readl(host->base + S3C2410_SDICMDCON);
155 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
156 r0 = readl(host->base + S3C2410_SDIRSP0);
157 r1 = readl(host->base + S3C2410_SDIRSP1);
158 r2 = readl(host->base + S3C2410_SDIRSP2);
159 r3 = readl(host->base + S3C2410_SDIRSP3);
160 timer = readl(host->base + S3C2410_SDITIMER);
161 datcon = readl(host->base + S3C2410_SDIDCON);
162 datcnt = readl(host->base + S3C2410_SDIDCNT);
163 datsta = readl(host->base + S3C2410_SDIDSTA);
164 fsta = readl(host->base + S3C2410_SDIFSTA);
165
166 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
167 prefix, con, pre, timer);
168
169 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
170 prefix, cmdcon, cmdarg, cmdsta);
171
172 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
173 " DSTA:[%08x] DCNT:[%08x]\n",
174 prefix, datcon, fsta, datsta, datcnt);
175
176 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
177 " R2:[%08x] R3:[%08x]\n",
178 prefix, r0, r1, r2, r3);
179}
180
181static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
182 int stop)
183{
184 snprintf(host->dbgmsg_cmd, 300,
185 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
186 host->ccnt, (stop ? " (STOP)" : ""),
187 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
188
189 if (cmd->data) {
190 snprintf(host->dbgmsg_dat, 300,
191 "#%u bsize:%u blocks:%u bytes:%u",
192 host->dcnt, cmd->data->blksz,
193 cmd->data->blocks,
194 cmd->data->blocks * cmd->data->blksz);
195 } else {
196 host->dbgmsg_dat[0] = '\0';
197 }
198}
199
200static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
201 int fail)
202{
203 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
204
205 if (!cmd)
206 return;
207
208 if (cmd->error == 0) {
209 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
210 host->dbgmsg_cmd, cmd->resp[0]);
211 } else {
212 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
213 cmd->error, host->dbgmsg_cmd, host->status);
214 }
215
216 if (!cmd->data)
217 return;
218
219 if (cmd->data->error == 0) {
220 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
221 } else {
222 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
223 cmd->data->error, host->dbgmsg_dat,
224 readl(host->base + S3C2410_SDIDCNT));
225 }
226}
227#else
228static void dbg_dumpcmd(struct s3cmci_host *host,
229 struct mmc_command *cmd, int fail) { }
230
231static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
232 int stop) { }
233
234static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
235
236#endif /* CONFIG_MMC_DEBUG */
237
238/**
239 * s3cmci_host_usedma - return whether the host is using dma or pio
240 * @host: The host state
241 *
242 * Return true if the host is using DMA to transfer data, else false
243 * to use PIO mode. Will return static data depending on the driver
244 * configuration.
245 */
246static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
247{
248#ifdef CONFIG_MMC_S3C_PIO
249 return false;
250#else /* CONFIG_MMC_S3C_DMA */
251 return true;
252#endif
253}
254
255static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
256{
257 u32 newmask;
258
259 newmask = readl(host->base + host->sdiimsk);
260 newmask |= imask;
261
262 writel(newmask, host->base + host->sdiimsk);
263
264 return newmask;
265}
266
267static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
268{
269 u32 newmask;
270
271 newmask = readl(host->base + host->sdiimsk);
272 newmask &= ~imask;
273
274 writel(newmask, host->base + host->sdiimsk);
275
276 return newmask;
277}
278
279static inline void clear_imask(struct s3cmci_host *host)
280{
281 u32 mask = readl(host->base + host->sdiimsk);
282
283 /* preserve the SDIO IRQ mask state */
284 mask &= S3C2410_SDIIMSK_SDIOIRQ;
285 writel(mask, host->base + host->sdiimsk);
286}
287
288/**
289 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
290 * @host: The host to check.
291 *
292 * Test to see if the SDIO interrupt is being signalled in case the
293 * controller has failed to re-detect a card interrupt. Read GPE8 and
294 * see if it is low and if so, signal a SDIO interrupt.
295 *
296 * This is currently called if a request is finished (we assume that the
297 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
298 * already being indicated.
299*/
300static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
301{
302 if (host->sdio_irqen) {
303 if (host->pdata->bus[3] &&
304 gpiod_get_value(host->pdata->bus[3]) == 0) {
305 pr_debug("%s: signalling irq\n", __func__);
306 mmc_signal_sdio_irq(host->mmc);
307 }
308 }
309}
310
311static inline int get_data_buffer(struct s3cmci_host *host,
312 u32 *bytes, u32 **pointer)
313{
314 struct scatterlist *sg;
315
316 if (host->pio_active == XFER_NONE)
317 return -EINVAL;
318
319 if ((!host->mrq) || (!host->mrq->data))
320 return -EINVAL;
321
322 if (host->pio_sgptr >= host->mrq->data->sg_len) {
323 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
324 host->pio_sgptr, host->mrq->data->sg_len);
325 return -EBUSY;
326 }
327 sg = &host->mrq->data->sg[host->pio_sgptr];
328
329 *bytes = sg->length;
330 *pointer = sg_virt(sg);
331
332 host->pio_sgptr++;
333
334 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
335 host->pio_sgptr, host->mrq->data->sg_len);
336
337 return 0;
338}
339
340static inline u32 fifo_count(struct s3cmci_host *host)
341{
342 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
343
344 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
345 return fifostat;
346}
347
348static inline u32 fifo_free(struct s3cmci_host *host)
349{
350 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
351
352 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
353 return 63 - fifostat;
354}
355
356/**
357 * s3cmci_enable_irq - enable IRQ, after having disabled it.
358 * @host: The device state.
359 * @more: True if more IRQs are expected from transfer.
360 *
361 * Enable the main IRQ if needed after it has been disabled.
362 *
363 * The IRQ can be one of the following states:
364 * - disabled during IDLE
365 * - disabled whilst processing data
366 * - enabled during transfer
367 * - enabled whilst awaiting SDIO interrupt detection
368 */
369static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
370{
371 unsigned long flags;
372 bool enable = false;
373
374 local_irq_save(flags);
375
376 host->irq_enabled = more;
377 host->irq_disabled = false;
378
379 enable = more | host->sdio_irqen;
380
381 if (host->irq_state != enable) {
382 host->irq_state = enable;
383
384 if (enable)
385 enable_irq(host->irq);
386 else
387 disable_irq(host->irq);
388 }
389
390 local_irq_restore(flags);
391}
392
393static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
394{
395 unsigned long flags;
396
397 local_irq_save(flags);
398
399 /* pr_debug("%s: transfer %d\n", __func__, transfer); */
400
401 host->irq_disabled = transfer;
402
403 if (transfer && host->irq_state) {
404 host->irq_state = false;
405 disable_irq(host->irq);
406 }
407
408 local_irq_restore(flags);
409}
410
411static void do_pio_read(struct s3cmci_host *host)
412{
413 int res;
414 u32 fifo;
415 u32 *ptr;
416 u32 fifo_words;
417 void __iomem *from_ptr;
418
419 /* write real prescaler to host, it might be set slow to fix */
420 writel(host->prescaler, host->base + S3C2410_SDIPRE);
421
422 from_ptr = host->base + host->sdidata;
423
424 while ((fifo = fifo_count(host))) {
425 if (!host->pio_bytes) {
426 res = get_data_buffer(host, &host->pio_bytes,
427 &host->pio_ptr);
428 if (res) {
429 host->pio_active = XFER_NONE;
430 host->complete_what = COMPLETION_FINALIZE;
431
432 dbg(host, dbg_pio, "pio_read(): "
433 "complete (no more data).\n");
434 return;
435 }
436
437 dbg(host, dbg_pio,
438 "pio_read(): new target: [%i]@[%p]\n",
439 host->pio_bytes, host->pio_ptr);
440 }
441
442 dbg(host, dbg_pio,
443 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
444 fifo, host->pio_bytes,
445 readl(host->base + S3C2410_SDIDCNT));
446
447 /* If we have reached the end of the block, we can
448 * read a word and get 1 to 3 bytes. If we in the
449 * middle of the block, we have to read full words,
450 * otherwise we will write garbage, so round down to
451 * an even multiple of 4. */
452 if (fifo >= host->pio_bytes)
453 fifo = host->pio_bytes;
454 else
455 fifo -= fifo & 3;
456
457 host->pio_bytes -= fifo;
458 host->pio_count += fifo;
459
460 fifo_words = fifo >> 2;
461 ptr = host->pio_ptr;
462 while (fifo_words--)
463 *ptr++ = readl(from_ptr);
464 host->pio_ptr = ptr;
465
466 if (fifo & 3) {
467 u32 n = fifo & 3;
468 u32 data = readl(from_ptr);
469 u8 *p = (u8 *)host->pio_ptr;
470
471 while (n--) {
472 *p++ = data;
473 data >>= 8;
474 }
475 }
476 }
477
478 if (!host->pio_bytes) {
479 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
480 if (res) {
481 dbg(host, dbg_pio,
482 "pio_read(): complete (no more buffers).\n");
483 host->pio_active = XFER_NONE;
484 host->complete_what = COMPLETION_FINALIZE;
485
486 return;
487 }
488 }
489
490 enable_imask(host,
491 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
492}
493
494static void do_pio_write(struct s3cmci_host *host)
495{
496 void __iomem *to_ptr;
497 int res;
498 u32 fifo;
499 u32 *ptr;
500
501 to_ptr = host->base + host->sdidata;
502
503 while ((fifo = fifo_free(host)) > 3) {
504 if (!host->pio_bytes) {
505 res = get_data_buffer(host, &host->pio_bytes,
506 &host->pio_ptr);
507 if (res) {
508 dbg(host, dbg_pio,
509 "pio_write(): complete (no more data).\n");
510 host->pio_active = XFER_NONE;
511
512 return;
513 }
514
515 dbg(host, dbg_pio,
516 "pio_write(): new source: [%i]@[%p]\n",
517 host->pio_bytes, host->pio_ptr);
518
519 }
520
521 /* If we have reached the end of the block, we have to
522 * write exactly the remaining number of bytes. If we
523 * in the middle of the block, we have to write full
524 * words, so round down to an even multiple of 4. */
525 if (fifo >= host->pio_bytes)
526 fifo = host->pio_bytes;
527 else
528 fifo -= fifo & 3;
529
530 host->pio_bytes -= fifo;
531 host->pio_count += fifo;
532
533 fifo = (fifo + 3) >> 2;
534 ptr = host->pio_ptr;
535 while (fifo--)
536 writel(*ptr++, to_ptr);
537 host->pio_ptr = ptr;
538 }
539
540 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
541}
542
543static void pio_tasklet(struct tasklet_struct *t)
544{
545 struct s3cmci_host *host = from_tasklet(host, t, pio_tasklet);
546
547 s3cmci_disable_irq(host, true);
548
549 if (host->pio_active == XFER_WRITE)
550 do_pio_write(host);
551
552 if (host->pio_active == XFER_READ)
553 do_pio_read(host);
554
555 if (host->complete_what == COMPLETION_FINALIZE) {
556 clear_imask(host);
557 if (host->pio_active != XFER_NONE) {
558 dbg(host, dbg_err, "unfinished %s "
559 "- pio_count:[%u] pio_bytes:[%u]\n",
560 (host->pio_active == XFER_READ) ? "read" : "write",
561 host->pio_count, host->pio_bytes);
562
563 if (host->mrq->data)
564 host->mrq->data->error = -EINVAL;
565 }
566
567 s3cmci_enable_irq(host, false);
568 finalize_request(host);
569 } else
570 s3cmci_enable_irq(host, true);
571}
572
573/*
574 * ISR for SDI Interface IRQ
575 * Communication between driver and ISR works as follows:
576 * host->mrq points to current request
577 * host->complete_what Indicates when the request is considered done
578 * COMPLETION_CMDSENT when the command was sent
579 * COMPLETION_RSPFIN when a response was received
580 * COMPLETION_XFERFINISH when the data transfer is finished
581 * COMPLETION_XFERFINISH_RSPFIN both of the above.
582 * host->complete_request is the completion-object the driver waits for
583 *
584 * 1) Driver sets up host->mrq and host->complete_what
585 * 2) Driver prepares the transfer
586 * 3) Driver enables interrupts
587 * 4) Driver starts transfer
588 * 5) Driver waits for host->complete_rquest
589 * 6) ISR checks for request status (errors and success)
590 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
591 * 7) ISR completes host->complete_request
592 * 8) ISR disables interrupts
593 * 9) Driver wakes up and takes care of the request
594 *
595 * Note: "->error"-fields are expected to be set to 0 before the request
596 * was issued by mmc.c - therefore they are only set, when an error
597 * contition comes up
598 */
599
600static irqreturn_t s3cmci_irq(int irq, void *dev_id)
601{
602 struct s3cmci_host *host = dev_id;
603 struct mmc_command *cmd;
604 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
605 u32 mci_cclear = 0, mci_dclear;
606 unsigned long iflags;
607
608 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
609 mci_imsk = readl(host->base + host->sdiimsk);
610
611 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
612 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
613 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
614 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
615
616 mmc_signal_sdio_irq(host->mmc);
617 return IRQ_HANDLED;
618 }
619 }
620
621 spin_lock_irqsave(&host->complete_lock, iflags);
622
623 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
624 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
625 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
626 mci_dclear = 0;
627
628 if ((host->complete_what == COMPLETION_NONE) ||
629 (host->complete_what == COMPLETION_FINALIZE)) {
630 host->status = "nothing to complete";
631 clear_imask(host);
632 goto irq_out;
633 }
634
635 if (!host->mrq) {
636 host->status = "no active mrq";
637 clear_imask(host);
638 goto irq_out;
639 }
640
641 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
642
643 if (!cmd) {
644 host->status = "no active cmd";
645 clear_imask(host);
646 goto irq_out;
647 }
648
649 if (!s3cmci_host_usedma(host)) {
650 if ((host->pio_active == XFER_WRITE) &&
651 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
652
653 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
654 tasklet_schedule(&host->pio_tasklet);
655 host->status = "pio tx";
656 }
657
658 if ((host->pio_active == XFER_READ) &&
659 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
660
661 disable_imask(host,
662 S3C2410_SDIIMSK_RXFIFOHALF |
663 S3C2410_SDIIMSK_RXFIFOLAST);
664
665 tasklet_schedule(&host->pio_tasklet);
666 host->status = "pio rx";
667 }
668 }
669
670 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
671 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
672 cmd->error = -ETIMEDOUT;
673 host->status = "error: command timeout";
674 goto fail_transfer;
675 }
676
677 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
678 if (host->complete_what == COMPLETION_CMDSENT) {
679 host->status = "ok: command sent";
680 goto close_transfer;
681 }
682
683 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
684 }
685
686 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
687 if (cmd->flags & MMC_RSP_CRC) {
688 if (host->mrq->cmd->flags & MMC_RSP_136) {
689 dbg(host, dbg_irq,
690 "fixup: ignore CRC fail with long rsp\n");
691 } else {
692 /* note, we used to fail the transfer
693 * here, but it seems that this is just
694 * the hardware getting it wrong.
695 *
696 * cmd->error = -EILSEQ;
697 * host->status = "error: bad command crc";
698 * goto fail_transfer;
699 */
700 }
701 }
702
703 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
704 }
705
706 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
707 if (host->complete_what == COMPLETION_RSPFIN) {
708 host->status = "ok: command response received";
709 goto close_transfer;
710 }
711
712 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
713 host->complete_what = COMPLETION_XFERFINISH;
714
715 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
716 }
717
718 /* errors handled after this point are only relevant
719 when a data transfer is in progress */
720
721 if (!cmd->data)
722 goto clear_status_bits;
723
724 /* Check for FIFO failure */
725 if (host->is2440) {
726 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
727 dbg(host, dbg_err, "FIFO failure\n");
728 host->mrq->data->error = -EILSEQ;
729 host->status = "error: 2440 fifo failure";
730 goto fail_transfer;
731 }
732 } else {
733 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
734 dbg(host, dbg_err, "FIFO failure\n");
735 cmd->data->error = -EILSEQ;
736 host->status = "error: fifo failure";
737 goto fail_transfer;
738 }
739 }
740
741 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
742 dbg(host, dbg_err, "bad data crc (outgoing)\n");
743 cmd->data->error = -EILSEQ;
744 host->status = "error: bad data crc (outgoing)";
745 goto fail_transfer;
746 }
747
748 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
749 dbg(host, dbg_err, "bad data crc (incoming)\n");
750 cmd->data->error = -EILSEQ;
751 host->status = "error: bad data crc (incoming)";
752 goto fail_transfer;
753 }
754
755 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
756 dbg(host, dbg_err, "data timeout\n");
757 cmd->data->error = -ETIMEDOUT;
758 host->status = "error: data timeout";
759 goto fail_transfer;
760 }
761
762 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
763 if (host->complete_what == COMPLETION_XFERFINISH) {
764 host->status = "ok: data transfer completed";
765 goto close_transfer;
766 }
767
768 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
769 host->complete_what = COMPLETION_RSPFIN;
770
771 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
772 }
773
774clear_status_bits:
775 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
776 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
777
778 goto irq_out;
779
780fail_transfer:
781 host->pio_active = XFER_NONE;
782
783close_transfer:
784 host->complete_what = COMPLETION_FINALIZE;
785
786 clear_imask(host);
787 tasklet_schedule(&host->pio_tasklet);
788
789 goto irq_out;
790
791irq_out:
792 dbg(host, dbg_irq,
793 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
794 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
795
796 spin_unlock_irqrestore(&host->complete_lock, iflags);
797 return IRQ_HANDLED;
798
799}
800
801static void s3cmci_dma_done_callback(void *arg)
802{
803 struct s3cmci_host *host = arg;
804 unsigned long iflags;
805
806 BUG_ON(!host->mrq);
807 BUG_ON(!host->mrq->data);
808
809 spin_lock_irqsave(&host->complete_lock, iflags);
810
811 dbg(host, dbg_dma, "DMA FINISHED\n");
812
813 host->dma_complete = 1;
814 host->complete_what = COMPLETION_FINALIZE;
815
816 tasklet_schedule(&host->pio_tasklet);
817 spin_unlock_irqrestore(&host->complete_lock, iflags);
818
819}
820
821static void finalize_request(struct s3cmci_host *host)
822{
823 struct mmc_request *mrq = host->mrq;
824 struct mmc_command *cmd;
825 int debug_as_failure = 0;
826
827 if (host->complete_what != COMPLETION_FINALIZE)
828 return;
829
830 if (!mrq)
831 return;
832 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
833
834 if (cmd->data && (cmd->error == 0) &&
835 (cmd->data->error == 0)) {
836 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
837 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
838 host->dma_complete);
839 return;
840 }
841 }
842
843 /* Read response from controller. */
844 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
845 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
846 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
847 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
848
849 writel(host->prescaler, host->base + S3C2410_SDIPRE);
850
851 if (cmd->error)
852 debug_as_failure = 1;
853
854 if (cmd->data && cmd->data->error)
855 debug_as_failure = 1;
856
857 dbg_dumpcmd(host, cmd, debug_as_failure);
858
859 /* Cleanup controller */
860 writel(0, host->base + S3C2410_SDICMDARG);
861 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
862 writel(0, host->base + S3C2410_SDICMDCON);
863 clear_imask(host);
864
865 if (cmd->data && cmd->error)
866 cmd->data->error = cmd->error;
867
868 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
869 host->cmd_is_stop = 1;
870 s3cmci_send_request(host->mmc);
871 return;
872 }
873
874 /* If we have no data transfer we are finished here */
875 if (!mrq->data)
876 goto request_done;
877
878 /* Calculate the amout of bytes transfer if there was no error */
879 if (mrq->data->error == 0) {
880 mrq->data->bytes_xfered =
881 (mrq->data->blocks * mrq->data->blksz);
882 } else {
883 mrq->data->bytes_xfered = 0;
884 }
885
886 /* If we had an error while transferring data we flush the
887 * DMA channel and the fifo to clear out any garbage. */
888 if (mrq->data->error != 0) {
889 if (s3cmci_host_usedma(host))
890 dmaengine_terminate_all(host->dma);
891
892 if (host->is2440) {
893 /* Clear failure register and reset fifo. */
894 writel(S3C2440_SDIFSTA_FIFORESET |
895 S3C2440_SDIFSTA_FIFOFAIL,
896 host->base + S3C2410_SDIFSTA);
897 } else {
898 u32 mci_con;
899
900 /* reset fifo */
901 mci_con = readl(host->base + S3C2410_SDICON);
902 mci_con |= S3C2410_SDICON_FIFORESET;
903
904 writel(mci_con, host->base + S3C2410_SDICON);
905 }
906 }
907
908request_done:
909 host->complete_what = COMPLETION_NONE;
910 host->mrq = NULL;
911
912 s3cmci_check_sdio_irq(host);
913 mmc_request_done(host->mmc, mrq);
914}
915
916static void s3cmci_send_command(struct s3cmci_host *host,
917 struct mmc_command *cmd)
918{
919 u32 ccon, imsk;
920
921 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
922 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
923 S3C2410_SDIIMSK_RESPONSECRC;
924
925 enable_imask(host, imsk);
926
927 if (cmd->data)
928 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
929 else if (cmd->flags & MMC_RSP_PRESENT)
930 host->complete_what = COMPLETION_RSPFIN;
931 else
932 host->complete_what = COMPLETION_CMDSENT;
933
934 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
935
936 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
937 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
938
939 if (cmd->flags & MMC_RSP_PRESENT)
940 ccon |= S3C2410_SDICMDCON_WAITRSP;
941
942 if (cmd->flags & MMC_RSP_136)
943 ccon |= S3C2410_SDICMDCON_LONGRSP;
944
945 writel(ccon, host->base + S3C2410_SDICMDCON);
946}
947
948static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
949{
950 u32 dcon, imsk, stoptries = 3;
951
952 if ((data->blksz & 3) != 0) {
953 /* We cannot deal with unaligned blocks with more than
954 * one block being transferred. */
955
956 if (data->blocks > 1) {
957 pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
958 __func__, data->blksz);
959 return -EINVAL;
960 }
961 }
962
963 while (readl(host->base + S3C2410_SDIDSTA) &
964 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
965
966 dbg(host, dbg_err,
967 "mci_setup_data() transfer stillin progress.\n");
968
969 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
970 s3cmci_reset(host);
971
972 if ((stoptries--) == 0) {
973 dbg_dumpregs(host, "DRF");
974 return -EINVAL;
975 }
976 }
977
978 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
979
980 if (s3cmci_host_usedma(host))
981 dcon |= S3C2410_SDIDCON_DMAEN;
982
983 if (host->bus_width == MMC_BUS_WIDTH_4)
984 dcon |= S3C2410_SDIDCON_WIDEBUS;
985
986 dcon |= S3C2410_SDIDCON_BLOCKMODE;
987
988 if (data->flags & MMC_DATA_WRITE) {
989 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
990 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
991 }
992
993 if (data->flags & MMC_DATA_READ) {
994 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
995 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
996 }
997
998 if (host->is2440) {
999 dcon |= S3C2440_SDIDCON_DS_WORD;
1000 dcon |= S3C2440_SDIDCON_DATSTART;
1001 }
1002
1003 writel(dcon, host->base + S3C2410_SDIDCON);
1004
1005 /* write BSIZE register */
1006
1007 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1008
1009 /* add to IMASK register */
1010 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1011 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1012
1013 enable_imask(host, imsk);
1014
1015 /* write TIMER register */
1016
1017 if (host->is2440) {
1018 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1019 } else {
1020 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1021
1022 /* FIX: set slow clock to prevent timeouts on read */
1023 if (data->flags & MMC_DATA_READ)
1024 writel(0xFF, host->base + S3C2410_SDIPRE);
1025 }
1026
1027 return 0;
1028}
1029
1030#define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1031
1032static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1033{
1034 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1035
1036 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1037
1038 host->pio_sgptr = 0;
1039 host->pio_bytes = 0;
1040 host->pio_count = 0;
1041 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1042
1043 if (rw) {
1044 do_pio_write(host);
1045 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1046 } else {
1047 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1048 | S3C2410_SDIIMSK_RXFIFOLAST);
1049 }
1050
1051 return 0;
1052}
1053
1054static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1055{
1056 int rw = data->flags & MMC_DATA_WRITE;
1057 struct dma_async_tx_descriptor *desc;
1058 struct dma_slave_config conf = {
1059 .src_addr = host->mem->start + host->sdidata,
1060 .dst_addr = host->mem->start + host->sdidata,
1061 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1062 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1063 };
1064
1065 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1066
1067 /* Restore prescaler value */
1068 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1069
1070 if (!rw)
1071 conf.direction = DMA_DEV_TO_MEM;
1072 else
1073 conf.direction = DMA_MEM_TO_DEV;
1074
1075 dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1076 mmc_get_dma_dir(data));
1077
1078 dmaengine_slave_config(host->dma, &conf);
1079 desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1080 conf.direction,
1081 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1082 if (!desc)
1083 goto unmap_exit;
1084 desc->callback = s3cmci_dma_done_callback;
1085 desc->callback_param = host;
1086 dmaengine_submit(desc);
1087 dma_async_issue_pending(host->dma);
1088
1089 return 0;
1090
1091unmap_exit:
1092 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1093 mmc_get_dma_dir(data));
1094 return -ENOMEM;
1095}
1096
1097static void s3cmci_send_request(struct mmc_host *mmc)
1098{
1099 struct s3cmci_host *host = mmc_priv(mmc);
1100 struct mmc_request *mrq = host->mrq;
1101 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1102
1103 host->ccnt++;
1104 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1105
1106 /* Clear command, data and fifo status registers
1107 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1108 */
1109 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1110 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1111 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1112
1113 if (cmd->data) {
1114 int res = s3cmci_setup_data(host, cmd->data);
1115
1116 host->dcnt++;
1117
1118 if (res) {
1119 dbg(host, dbg_err, "setup data error %d\n", res);
1120 cmd->error = res;
1121 cmd->data->error = res;
1122
1123 mmc_request_done(mmc, mrq);
1124 return;
1125 }
1126
1127 if (s3cmci_host_usedma(host))
1128 res = s3cmci_prepare_dma(host, cmd->data);
1129 else
1130 res = s3cmci_prepare_pio(host, cmd->data);
1131
1132 if (res) {
1133 dbg(host, dbg_err, "data prepare error %d\n", res);
1134 cmd->error = res;
1135 cmd->data->error = res;
1136
1137 mmc_request_done(mmc, mrq);
1138 return;
1139 }
1140 }
1141
1142 /* Send command */
1143 s3cmci_send_command(host, cmd);
1144
1145 /* Enable Interrupt */
1146 s3cmci_enable_irq(host, true);
1147}
1148
1149static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1150{
1151 struct s3cmci_host *host = mmc_priv(mmc);
1152
1153 host->status = "mmc request";
1154 host->cmd_is_stop = 0;
1155 host->mrq = mrq;
1156
1157 if (mmc_gpio_get_cd(mmc) == 0) {
1158 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1159 host->mrq->cmd->error = -ENOMEDIUM;
1160 mmc_request_done(mmc, mrq);
1161 } else
1162 s3cmci_send_request(mmc);
1163}
1164
1165static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1166{
1167 u32 mci_psc;
1168
1169 /* Set clock */
1170 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1171 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1172
1173 if (host->real_rate <= ios->clock)
1174 break;
1175 }
1176
1177 if (mci_psc > 255)
1178 mci_psc = 255;
1179
1180 host->prescaler = mci_psc;
1181 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1182
1183 /* If requested clock is 0, real_rate will be 0, too */
1184 if (ios->clock == 0)
1185 host->real_rate = 0;
1186}
1187
1188static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1189{
1190 struct s3cmci_host *host = mmc_priv(mmc);
1191 u32 mci_con;
1192
1193 /* Set the power state */
1194
1195 mci_con = readl(host->base + S3C2410_SDICON);
1196
1197 switch (ios->power_mode) {
1198 case MMC_POWER_ON:
1199 case MMC_POWER_UP:
1200 if (!host->is2440)
1201 mci_con |= S3C2410_SDICON_FIFORESET;
1202 break;
1203
1204 case MMC_POWER_OFF:
1205 default:
1206 if (host->is2440)
1207 mci_con |= S3C2440_SDICON_SDRESET;
1208 break;
1209 }
1210
1211 if (host->pdata->set_power)
1212 host->pdata->set_power(ios->power_mode, ios->vdd);
1213
1214 s3cmci_set_clk(host, ios);
1215
1216 /* Set CLOCK_ENABLE */
1217 if (ios->clock)
1218 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1219 else
1220 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1221
1222 writel(mci_con, host->base + S3C2410_SDICON);
1223
1224 if ((ios->power_mode == MMC_POWER_ON) ||
1225 (ios->power_mode == MMC_POWER_UP)) {
1226 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1227 host->real_rate/1000, ios->clock/1000);
1228 } else {
1229 dbg(host, dbg_conf, "powered down.\n");
1230 }
1231
1232 host->bus_width = ios->bus_width;
1233}
1234
1235static void s3cmci_reset(struct s3cmci_host *host)
1236{
1237 u32 con = readl(host->base + S3C2410_SDICON);
1238
1239 con |= S3C2440_SDICON_SDRESET;
1240 writel(con, host->base + S3C2410_SDICON);
1241}
1242
1243static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1244{
1245 struct s3cmci_host *host = mmc_priv(mmc);
1246 unsigned long flags;
1247 u32 con;
1248
1249 local_irq_save(flags);
1250
1251 con = readl(host->base + S3C2410_SDICON);
1252 host->sdio_irqen = enable;
1253
1254 if (enable == host->sdio_irqen)
1255 goto same_state;
1256
1257 if (enable) {
1258 con |= S3C2410_SDICON_SDIOIRQ;
1259 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1260
1261 if (!host->irq_state && !host->irq_disabled) {
1262 host->irq_state = true;
1263 enable_irq(host->irq);
1264 }
1265 } else {
1266 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1267 con &= ~S3C2410_SDICON_SDIOIRQ;
1268
1269 if (!host->irq_enabled && host->irq_state) {
1270 disable_irq_nosync(host->irq);
1271 host->irq_state = false;
1272 }
1273 }
1274
1275 writel(con, host->base + S3C2410_SDICON);
1276
1277 same_state:
1278 local_irq_restore(flags);
1279
1280 s3cmci_check_sdio_irq(host);
1281}
1282
1283static const struct mmc_host_ops s3cmci_ops = {
1284 .request = s3cmci_request,
1285 .set_ios = s3cmci_set_ios,
1286 .get_ro = mmc_gpio_get_ro,
1287 .get_cd = mmc_gpio_get_cd,
1288 .enable_sdio_irq = s3cmci_enable_sdio_irq,
1289};
1290
1291#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1292
1293static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1294 unsigned long val, void *data)
1295{
1296 struct s3cmci_host *host;
1297 struct mmc_host *mmc;
1298 unsigned long newclk;
1299 unsigned long flags;
1300
1301 host = container_of(nb, struct s3cmci_host, freq_transition);
1302 newclk = clk_get_rate(host->clk);
1303 mmc = host->mmc;
1304
1305 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1306 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1307 spin_lock_irqsave(&mmc->lock, flags);
1308
1309 host->clk_rate = newclk;
1310
1311 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1312 mmc->ios.clock != 0)
1313 s3cmci_set_clk(host, &mmc->ios);
1314
1315 spin_unlock_irqrestore(&mmc->lock, flags);
1316 }
1317
1318 return 0;
1319}
1320
1321static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1322{
1323 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1324
1325 return cpufreq_register_notifier(&host->freq_transition,
1326 CPUFREQ_TRANSITION_NOTIFIER);
1327}
1328
1329static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1330{
1331 cpufreq_unregister_notifier(&host->freq_transition,
1332 CPUFREQ_TRANSITION_NOTIFIER);
1333}
1334
1335#else
1336static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1337{
1338 return 0;
1339}
1340
1341static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1342{
1343}
1344#endif
1345
1346
1347#ifdef CONFIG_DEBUG_FS
1348
1349static int s3cmci_state_show(struct seq_file *seq, void *v)
1350{
1351 struct s3cmci_host *host = seq->private;
1352
1353 seq_printf(seq, "Register base = 0x%p\n", host->base);
1354 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1355 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1356 seq_printf(seq, "is2440 = %d\n", host->is2440);
1357 seq_printf(seq, "IRQ = %d\n", host->irq);
1358 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1359 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1360 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1361 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1362 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1363 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1364 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1365
1366 return 0;
1367}
1368
1369DEFINE_SHOW_ATTRIBUTE(s3cmci_state);
1370
1371#define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1372
1373struct s3cmci_reg {
1374 unsigned short addr;
1375 unsigned char *name;
1376};
1377
1378static const struct s3cmci_reg debug_regs[] = {
1379 DBG_REG(CON),
1380 DBG_REG(PRE),
1381 DBG_REG(CMDARG),
1382 DBG_REG(CMDCON),
1383 DBG_REG(CMDSTAT),
1384 DBG_REG(RSP0),
1385 DBG_REG(RSP1),
1386 DBG_REG(RSP2),
1387 DBG_REG(RSP3),
1388 DBG_REG(TIMER),
1389 DBG_REG(BSIZE),
1390 DBG_REG(DCON),
1391 DBG_REG(DCNT),
1392 DBG_REG(DSTA),
1393 DBG_REG(FSTA),
1394 {}
1395};
1396
1397static int s3cmci_regs_show(struct seq_file *seq, void *v)
1398{
1399 struct s3cmci_host *host = seq->private;
1400 const struct s3cmci_reg *rptr = debug_regs;
1401
1402 for (; rptr->name; rptr++)
1403 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1404 readl(host->base + rptr->addr));
1405
1406 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1407
1408 return 0;
1409}
1410
1411DEFINE_SHOW_ATTRIBUTE(s3cmci_regs);
1412
1413static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1414{
1415 struct device *dev = &host->pdev->dev;
1416 struct dentry *root;
1417
1418 root = debugfs_create_dir(dev_name(dev), NULL);
1419 host->debug_root = root;
1420
1421 debugfs_create_file("state", 0444, root, host, &s3cmci_state_fops);
1422 debugfs_create_file("regs", 0444, root, host, &s3cmci_regs_fops);
1423}
1424
1425static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1426{
1427 debugfs_remove_recursive(host->debug_root);
1428}
1429
1430#else
1431static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1432static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1433
1434#endif /* CONFIG_DEBUG_FS */
1435
1436static int s3cmci_probe_pdata(struct s3cmci_host *host)
1437{
1438 struct platform_device *pdev = host->pdev;
1439 struct mmc_host *mmc = host->mmc;
1440 struct s3c24xx_mci_pdata *pdata;
1441 int i, ret;
1442
1443 host->is2440 = platform_get_device_id(pdev)->driver_data;
1444 pdata = pdev->dev.platform_data;
1445 if (!pdata) {
1446 dev_err(&pdev->dev, "need platform data");
1447 return -ENXIO;
1448 }
1449
1450 for (i = 0; i < 6; i++) {
1451 pdata->bus[i] = devm_gpiod_get_index(&pdev->dev, "bus", i,
1452 GPIOD_OUT_LOW);
1453 if (IS_ERR(pdata->bus[i])) {
1454 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1455 return PTR_ERR(pdata->bus[i]);
1456 }
1457 }
1458
1459 if (pdata->no_wprotect)
1460 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1461
1462 if (pdata->no_detect)
1463 mmc->caps |= MMC_CAP_NEEDS_POLL;
1464
1465 if (pdata->wprotect_invert)
1466 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1467
1468 /* If we get -ENOENT we have no card detect GPIO line */
1469 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
1470 if (ret != -ENOENT) {
1471 dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
1472 ret);
1473 return ret;
1474 }
1475
1476 ret = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1477 if (ret != -ENOENT) {
1478 dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
1479 ret);
1480 return ret;
1481 }
1482
1483 return 0;
1484}
1485
1486static int s3cmci_probe_dt(struct s3cmci_host *host)
1487{
1488 struct platform_device *pdev = host->pdev;
1489 struct s3c24xx_mci_pdata *pdata;
1490 struct mmc_host *mmc = host->mmc;
1491 int ret;
1492
1493 host->is2440 = (long) of_device_get_match_data(&pdev->dev);
1494
1495 ret = mmc_of_parse(mmc);
1496 if (ret)
1497 return ret;
1498
1499 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1500 if (!pdata)
1501 return -ENOMEM;
1502
1503 pdev->dev.platform_data = pdata;
1504
1505 return 0;
1506}
1507
1508static int s3cmci_probe(struct platform_device *pdev)
1509{
1510 struct s3cmci_host *host;
1511 struct mmc_host *mmc;
1512 int ret;
1513
1514 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1515 if (!mmc) {
1516 ret = -ENOMEM;
1517 goto probe_out;
1518 }
1519
1520 host = mmc_priv(mmc);
1521 host->mmc = mmc;
1522 host->pdev = pdev;
1523
1524 if (pdev->dev.of_node)
1525 ret = s3cmci_probe_dt(host);
1526 else
1527 ret = s3cmci_probe_pdata(host);
1528
1529 if (ret)
1530 goto probe_free_host;
1531
1532 host->pdata = pdev->dev.platform_data;
1533
1534 spin_lock_init(&host->complete_lock);
1535 tasklet_setup(&host->pio_tasklet, pio_tasklet);
1536
1537 if (host->is2440) {
1538 host->sdiimsk = S3C2440_SDIIMSK;
1539 host->sdidata = S3C2440_SDIDATA;
1540 host->clk_div = 1;
1541 } else {
1542 host->sdiimsk = S3C2410_SDIIMSK;
1543 host->sdidata = S3C2410_SDIDATA;
1544 host->clk_div = 2;
1545 }
1546
1547 host->complete_what = COMPLETION_NONE;
1548 host->pio_active = XFER_NONE;
1549
1550 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1551 if (!host->mem) {
1552 dev_err(&pdev->dev,
1553 "failed to get io memory region resource.\n");
1554
1555 ret = -ENOENT;
1556 goto probe_free_host;
1557 }
1558
1559 host->mem = request_mem_region(host->mem->start,
1560 resource_size(host->mem), pdev->name);
1561
1562 if (!host->mem) {
1563 dev_err(&pdev->dev, "failed to request io memory region.\n");
1564 ret = -ENOENT;
1565 goto probe_free_host;
1566 }
1567
1568 host->base = ioremap(host->mem->start, resource_size(host->mem));
1569 if (!host->base) {
1570 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1571 ret = -EINVAL;
1572 goto probe_free_mem_region;
1573 }
1574
1575 host->irq = platform_get_irq(pdev, 0);
1576 if (host->irq <= 0) {
1577 ret = -EINVAL;
1578 goto probe_iounmap;
1579 }
1580
1581 if (request_irq(host->irq, s3cmci_irq, IRQF_NO_AUTOEN, DRIVER_NAME, host)) {
1582 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1583 ret = -ENOENT;
1584 goto probe_iounmap;
1585 }
1586
1587 host->irq_state = false;
1588
1589 /* Depending on the dma state, get a DMA channel to use. */
1590
1591 if (s3cmci_host_usedma(host)) {
1592 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1593 ret = PTR_ERR_OR_ZERO(host->dma);
1594 if (ret) {
1595 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1596 goto probe_free_irq;
1597 }
1598 }
1599
1600 host->clk = clk_get(&pdev->dev, "sdi");
1601 if (IS_ERR(host->clk)) {
1602 dev_err(&pdev->dev, "failed to find clock source.\n");
1603 ret = PTR_ERR(host->clk);
1604 host->clk = NULL;
1605 goto probe_free_dma;
1606 }
1607
1608 ret = clk_prepare_enable(host->clk);
1609 if (ret) {
1610 dev_err(&pdev->dev, "failed to enable clock source.\n");
1611 goto clk_free;
1612 }
1613
1614 host->clk_rate = clk_get_rate(host->clk);
1615
1616 mmc->ops = &s3cmci_ops;
1617 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1618#ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1619 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1620#else
1621 mmc->caps = MMC_CAP_4_BIT_DATA;
1622#endif
1623 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1624 mmc->f_max = host->clk_rate / host->clk_div;
1625
1626 if (host->pdata->ocr_avail)
1627 mmc->ocr_avail = host->pdata->ocr_avail;
1628
1629 mmc->max_blk_count = 4095;
1630 mmc->max_blk_size = 4095;
1631 mmc->max_req_size = 4095 * 512;
1632 mmc->max_seg_size = mmc->max_req_size;
1633
1634 mmc->max_segs = 128;
1635
1636 dbg(host, dbg_debug,
1637 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1638 (host->is2440?"2440":""),
1639 host->base, host->irq, host->irq_cd, host->dma);
1640
1641 ret = s3cmci_cpufreq_register(host);
1642 if (ret) {
1643 dev_err(&pdev->dev, "failed to register cpufreq\n");
1644 goto free_dmabuf;
1645 }
1646
1647 ret = mmc_add_host(mmc);
1648 if (ret) {
1649 dev_err(&pdev->dev, "failed to add mmc host.\n");
1650 goto free_cpufreq;
1651 }
1652
1653 s3cmci_debugfs_attach(host);
1654
1655 platform_set_drvdata(pdev, mmc);
1656 dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1657 s3cmci_host_usedma(host) ? "dma" : "pio",
1658 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1659
1660 return 0;
1661
1662 free_cpufreq:
1663 s3cmci_cpufreq_deregister(host);
1664
1665 free_dmabuf:
1666 clk_disable_unprepare(host->clk);
1667
1668 clk_free:
1669 clk_put(host->clk);
1670
1671 probe_free_dma:
1672 if (s3cmci_host_usedma(host))
1673 dma_release_channel(host->dma);
1674
1675 probe_free_irq:
1676 free_irq(host->irq, host);
1677
1678 probe_iounmap:
1679 iounmap(host->base);
1680
1681 probe_free_mem_region:
1682 release_mem_region(host->mem->start, resource_size(host->mem));
1683
1684 probe_free_host:
1685 mmc_free_host(mmc);
1686
1687 probe_out:
1688 return ret;
1689}
1690
1691static void s3cmci_shutdown(struct platform_device *pdev)
1692{
1693 struct mmc_host *mmc = platform_get_drvdata(pdev);
1694 struct s3cmci_host *host = mmc_priv(mmc);
1695
1696 if (host->irq_cd >= 0)
1697 free_irq(host->irq_cd, host);
1698
1699 s3cmci_debugfs_remove(host);
1700 s3cmci_cpufreq_deregister(host);
1701 mmc_remove_host(mmc);
1702 clk_disable_unprepare(host->clk);
1703}
1704
1705static int s3cmci_remove(struct platform_device *pdev)
1706{
1707 struct mmc_host *mmc = platform_get_drvdata(pdev);
1708 struct s3cmci_host *host = mmc_priv(mmc);
1709
1710 s3cmci_shutdown(pdev);
1711
1712 clk_put(host->clk);
1713
1714 tasklet_disable(&host->pio_tasklet);
1715
1716 if (s3cmci_host_usedma(host))
1717 dma_release_channel(host->dma);
1718
1719 free_irq(host->irq, host);
1720
1721 iounmap(host->base);
1722 release_mem_region(host->mem->start, resource_size(host->mem));
1723
1724 mmc_free_host(mmc);
1725 return 0;
1726}
1727
1728static const struct of_device_id s3cmci_dt_match[] = {
1729 {
1730 .compatible = "samsung,s3c2410-sdi",
1731 .data = (void *)0,
1732 },
1733 {
1734 .compatible = "samsung,s3c2412-sdi",
1735 .data = (void *)1,
1736 },
1737 {
1738 .compatible = "samsung,s3c2440-sdi",
1739 .data = (void *)1,
1740 },
1741 { /* sentinel */ },
1742};
1743MODULE_DEVICE_TABLE(of, s3cmci_dt_match);
1744
1745static const struct platform_device_id s3cmci_driver_ids[] = {
1746 {
1747 .name = "s3c2410-sdi",
1748 .driver_data = 0,
1749 }, {
1750 .name = "s3c2412-sdi",
1751 .driver_data = 1,
1752 }, {
1753 .name = "s3c2440-sdi",
1754 .driver_data = 1,
1755 },
1756 { }
1757};
1758
1759MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1760
1761static struct platform_driver s3cmci_driver = {
1762 .driver = {
1763 .name = "s3c-sdi",
1764 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1765 .of_match_table = s3cmci_dt_match,
1766 },
1767 .id_table = s3cmci_driver_ids,
1768 .probe = s3cmci_probe,
1769 .remove = s3cmci_remove,
1770 .shutdown = s3cmci_shutdown,
1771};
1772
1773module_platform_driver(s3cmci_driver);
1774
1775MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1776MODULE_LICENSE("GPL v2");
1777MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
1/*
2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
3 *
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
5 *
6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/dma-mapping.h>
16#include <linux/clk.h>
17#include <linux/mmc/host.h>
18#include <linux/platform_device.h>
19#include <linux/cpufreq.h>
20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
22#include <linux/gpio.h>
23#include <linux/irq.h>
24#include <linux/io.h>
25
26#include <plat/gpio-cfg.h>
27#include <mach/dma.h>
28#include <mach/gpio-samsung.h>
29
30#include <linux/platform_data/mmc-s3cmci.h>
31
32#include "s3cmci.h"
33
34#define DRIVER_NAME "s3c-mci"
35
36#define S3C2410_SDICON (0x00)
37#define S3C2410_SDIPRE (0x04)
38#define S3C2410_SDICMDARG (0x08)
39#define S3C2410_SDICMDCON (0x0C)
40#define S3C2410_SDICMDSTAT (0x10)
41#define S3C2410_SDIRSP0 (0x14)
42#define S3C2410_SDIRSP1 (0x18)
43#define S3C2410_SDIRSP2 (0x1C)
44#define S3C2410_SDIRSP3 (0x20)
45#define S3C2410_SDITIMER (0x24)
46#define S3C2410_SDIBSIZE (0x28)
47#define S3C2410_SDIDCON (0x2C)
48#define S3C2410_SDIDCNT (0x30)
49#define S3C2410_SDIDSTA (0x34)
50#define S3C2410_SDIFSTA (0x38)
51
52#define S3C2410_SDIDATA (0x3C)
53#define S3C2410_SDIIMSK (0x40)
54
55#define S3C2440_SDIDATA (0x40)
56#define S3C2440_SDIIMSK (0x3C)
57
58#define S3C2440_SDICON_SDRESET (1 << 8)
59#define S3C2410_SDICON_SDIOIRQ (1 << 3)
60#define S3C2410_SDICON_FIFORESET (1 << 1)
61#define S3C2410_SDICON_CLOCKTYPE (1 << 0)
62
63#define S3C2410_SDICMDCON_LONGRSP (1 << 10)
64#define S3C2410_SDICMDCON_WAITRSP (1 << 9)
65#define S3C2410_SDICMDCON_CMDSTART (1 << 8)
66#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
67#define S3C2410_SDICMDCON_INDEX (0x3f)
68
69#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
70#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
71#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
72#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
73
74#define S3C2440_SDIDCON_DS_WORD (2 << 22)
75#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
76#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
77#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
78#define S3C2410_SDIDCON_WIDEBUS (1 << 16)
79#define S3C2410_SDIDCON_DMAEN (1 << 15)
80#define S3C2410_SDIDCON_STOP (1 << 14)
81#define S3C2440_SDIDCON_DATSTART (1 << 14)
82
83#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
84#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
85
86#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
87
88#define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
89#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
90#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
91#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
92#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
93#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
94#define S3C2410_SDIDSTA_TXDATAON (1 << 1)
95#define S3C2410_SDIDSTA_RXDATAON (1 << 0)
96
97#define S3C2440_SDIFSTA_FIFORESET (1 << 16)
98#define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
99#define S3C2410_SDIFSTA_TFDET (1 << 13)
100#define S3C2410_SDIFSTA_RFDET (1 << 12)
101#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
102
103#define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
104#define S3C2410_SDIIMSK_CMDSENT (1 << 16)
105#define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
106#define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
107#define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
108#define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
109#define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
110#define S3C2410_SDIIMSK_DATACRC (1 << 9)
111#define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
112#define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
113#define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
114#define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
115#define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
116
117enum dbg_channels {
118 dbg_err = (1 << 0),
119 dbg_debug = (1 << 1),
120 dbg_info = (1 << 2),
121 dbg_irq = (1 << 3),
122 dbg_sg = (1 << 4),
123 dbg_dma = (1 << 5),
124 dbg_pio = (1 << 6),
125 dbg_fail = (1 << 7),
126 dbg_conf = (1 << 8),
127};
128
129static const int dbgmap_err = dbg_fail;
130static const int dbgmap_info = dbg_info | dbg_conf;
131static const int dbgmap_debug = dbg_err | dbg_debug;
132
133#define dbg(host, channels, args...) \
134 do { \
135 if (dbgmap_err & channels) \
136 dev_err(&host->pdev->dev, args); \
137 else if (dbgmap_info & channels) \
138 dev_info(&host->pdev->dev, args); \
139 else if (dbgmap_debug & channels) \
140 dev_dbg(&host->pdev->dev, args); \
141 } while (0)
142
143static struct s3c2410_dma_client s3cmci_dma_client = {
144 .name = "s3c-mci",
145};
146
147static void finalize_request(struct s3cmci_host *host);
148static void s3cmci_send_request(struct mmc_host *mmc);
149static void s3cmci_reset(struct s3cmci_host *host);
150
151#ifdef CONFIG_MMC_DEBUG
152
153static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
154{
155 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
156 u32 datcon, datcnt, datsta, fsta, imask;
157
158 con = readl(host->base + S3C2410_SDICON);
159 pre = readl(host->base + S3C2410_SDIPRE);
160 cmdarg = readl(host->base + S3C2410_SDICMDARG);
161 cmdcon = readl(host->base + S3C2410_SDICMDCON);
162 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
163 r0 = readl(host->base + S3C2410_SDIRSP0);
164 r1 = readl(host->base + S3C2410_SDIRSP1);
165 r2 = readl(host->base + S3C2410_SDIRSP2);
166 r3 = readl(host->base + S3C2410_SDIRSP3);
167 timer = readl(host->base + S3C2410_SDITIMER);
168 bsize = readl(host->base + S3C2410_SDIBSIZE);
169 datcon = readl(host->base + S3C2410_SDIDCON);
170 datcnt = readl(host->base + S3C2410_SDIDCNT);
171 datsta = readl(host->base + S3C2410_SDIDSTA);
172 fsta = readl(host->base + S3C2410_SDIFSTA);
173 imask = readl(host->base + host->sdiimsk);
174
175 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
176 prefix, con, pre, timer);
177
178 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
179 prefix, cmdcon, cmdarg, cmdsta);
180
181 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
182 " DSTA:[%08x] DCNT:[%08x]\n",
183 prefix, datcon, fsta, datsta, datcnt);
184
185 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
186 " R2:[%08x] R3:[%08x]\n",
187 prefix, r0, r1, r2, r3);
188}
189
190static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
191 int stop)
192{
193 snprintf(host->dbgmsg_cmd, 300,
194 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
195 host->ccnt, (stop ? " (STOP)" : ""),
196 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
197
198 if (cmd->data) {
199 snprintf(host->dbgmsg_dat, 300,
200 "#%u bsize:%u blocks:%u bytes:%u",
201 host->dcnt, cmd->data->blksz,
202 cmd->data->blocks,
203 cmd->data->blocks * cmd->data->blksz);
204 } else {
205 host->dbgmsg_dat[0] = '\0';
206 }
207}
208
209static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
210 int fail)
211{
212 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
213
214 if (!cmd)
215 return;
216
217 if (cmd->error == 0) {
218 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
219 host->dbgmsg_cmd, cmd->resp[0]);
220 } else {
221 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
222 cmd->error, host->dbgmsg_cmd, host->status);
223 }
224
225 if (!cmd->data)
226 return;
227
228 if (cmd->data->error == 0) {
229 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
230 } else {
231 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
232 cmd->data->error, host->dbgmsg_dat,
233 readl(host->base + S3C2410_SDIDCNT));
234 }
235}
236#else
237static void dbg_dumpcmd(struct s3cmci_host *host,
238 struct mmc_command *cmd, int fail) { }
239
240static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
241 int stop) { }
242
243static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
244
245#endif /* CONFIG_MMC_DEBUG */
246
247/**
248 * s3cmci_host_usedma - return whether the host is using dma or pio
249 * @host: The host state
250 *
251 * Return true if the host is using DMA to transfer data, else false
252 * to use PIO mode. Will return static data depending on the driver
253 * configuration.
254 */
255static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
256{
257#ifdef CONFIG_MMC_S3C_PIO
258 return false;
259#elif defined(CONFIG_MMC_S3C_DMA)
260 return true;
261#else
262 return host->dodma;
263#endif
264}
265
266/**
267 * s3cmci_host_canpio - return true if host has pio code available
268 *
269 * Return true if the driver has been compiled with the PIO support code
270 * available.
271 */
272static inline bool s3cmci_host_canpio(void)
273{
274#ifdef CONFIG_MMC_S3C_PIO
275 return true;
276#else
277 return false;
278#endif
279}
280
281static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
282{
283 u32 newmask;
284
285 newmask = readl(host->base + host->sdiimsk);
286 newmask |= imask;
287
288 writel(newmask, host->base + host->sdiimsk);
289
290 return newmask;
291}
292
293static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
294{
295 u32 newmask;
296
297 newmask = readl(host->base + host->sdiimsk);
298 newmask &= ~imask;
299
300 writel(newmask, host->base + host->sdiimsk);
301
302 return newmask;
303}
304
305static inline void clear_imask(struct s3cmci_host *host)
306{
307 u32 mask = readl(host->base + host->sdiimsk);
308
309 /* preserve the SDIO IRQ mask state */
310 mask &= S3C2410_SDIIMSK_SDIOIRQ;
311 writel(mask, host->base + host->sdiimsk);
312}
313
314/**
315 * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
316 * @host: The host to check.
317 *
318 * Test to see if the SDIO interrupt is being signalled in case the
319 * controller has failed to re-detect a card interrupt. Read GPE8 and
320 * see if it is low and if so, signal a SDIO interrupt.
321 *
322 * This is currently called if a request is finished (we assume that the
323 * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
324 * already being indicated.
325*/
326static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
327{
328 if (host->sdio_irqen) {
329 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
330 pr_debug("%s: signalling irq\n", __func__);
331 mmc_signal_sdio_irq(host->mmc);
332 }
333 }
334}
335
336static inline int get_data_buffer(struct s3cmci_host *host,
337 u32 *bytes, u32 **pointer)
338{
339 struct scatterlist *sg;
340
341 if (host->pio_active == XFER_NONE)
342 return -EINVAL;
343
344 if ((!host->mrq) || (!host->mrq->data))
345 return -EINVAL;
346
347 if (host->pio_sgptr >= host->mrq->data->sg_len) {
348 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
349 host->pio_sgptr, host->mrq->data->sg_len);
350 return -EBUSY;
351 }
352 sg = &host->mrq->data->sg[host->pio_sgptr];
353
354 *bytes = sg->length;
355 *pointer = sg_virt(sg);
356
357 host->pio_sgptr++;
358
359 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
360 host->pio_sgptr, host->mrq->data->sg_len);
361
362 return 0;
363}
364
365static inline u32 fifo_count(struct s3cmci_host *host)
366{
367 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
368
369 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
370 return fifostat;
371}
372
373static inline u32 fifo_free(struct s3cmci_host *host)
374{
375 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
376
377 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
378 return 63 - fifostat;
379}
380
381/**
382 * s3cmci_enable_irq - enable IRQ, after having disabled it.
383 * @host: The device state.
384 * @more: True if more IRQs are expected from transfer.
385 *
386 * Enable the main IRQ if needed after it has been disabled.
387 *
388 * The IRQ can be one of the following states:
389 * - disabled during IDLE
390 * - disabled whilst processing data
391 * - enabled during transfer
392 * - enabled whilst awaiting SDIO interrupt detection
393 */
394static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
395{
396 unsigned long flags;
397 bool enable = false;
398
399 local_irq_save(flags);
400
401 host->irq_enabled = more;
402 host->irq_disabled = false;
403
404 enable = more | host->sdio_irqen;
405
406 if (host->irq_state != enable) {
407 host->irq_state = enable;
408
409 if (enable)
410 enable_irq(host->irq);
411 else
412 disable_irq(host->irq);
413 }
414
415 local_irq_restore(flags);
416}
417
418/**
419 *
420 */
421static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
422{
423 unsigned long flags;
424
425 local_irq_save(flags);
426
427 /* pr_debug("%s: transfer %d\n", __func__, transfer); */
428
429 host->irq_disabled = transfer;
430
431 if (transfer && host->irq_state) {
432 host->irq_state = false;
433 disable_irq(host->irq);
434 }
435
436 local_irq_restore(flags);
437}
438
439static void do_pio_read(struct s3cmci_host *host)
440{
441 int res;
442 u32 fifo;
443 u32 *ptr;
444 u32 fifo_words;
445 void __iomem *from_ptr;
446
447 /* write real prescaler to host, it might be set slow to fix */
448 writel(host->prescaler, host->base + S3C2410_SDIPRE);
449
450 from_ptr = host->base + host->sdidata;
451
452 while ((fifo = fifo_count(host))) {
453 if (!host->pio_bytes) {
454 res = get_data_buffer(host, &host->pio_bytes,
455 &host->pio_ptr);
456 if (res) {
457 host->pio_active = XFER_NONE;
458 host->complete_what = COMPLETION_FINALIZE;
459
460 dbg(host, dbg_pio, "pio_read(): "
461 "complete (no more data).\n");
462 return;
463 }
464
465 dbg(host, dbg_pio,
466 "pio_read(): new target: [%i]@[%p]\n",
467 host->pio_bytes, host->pio_ptr);
468 }
469
470 dbg(host, dbg_pio,
471 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
472 fifo, host->pio_bytes,
473 readl(host->base + S3C2410_SDIDCNT));
474
475 /* If we have reached the end of the block, we can
476 * read a word and get 1 to 3 bytes. If we in the
477 * middle of the block, we have to read full words,
478 * otherwise we will write garbage, so round down to
479 * an even multiple of 4. */
480 if (fifo >= host->pio_bytes)
481 fifo = host->pio_bytes;
482 else
483 fifo -= fifo & 3;
484
485 host->pio_bytes -= fifo;
486 host->pio_count += fifo;
487
488 fifo_words = fifo >> 2;
489 ptr = host->pio_ptr;
490 while (fifo_words--)
491 *ptr++ = readl(from_ptr);
492 host->pio_ptr = ptr;
493
494 if (fifo & 3) {
495 u32 n = fifo & 3;
496 u32 data = readl(from_ptr);
497 u8 *p = (u8 *)host->pio_ptr;
498
499 while (n--) {
500 *p++ = data;
501 data >>= 8;
502 }
503 }
504 }
505
506 if (!host->pio_bytes) {
507 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
508 if (res) {
509 dbg(host, dbg_pio,
510 "pio_read(): complete (no more buffers).\n");
511 host->pio_active = XFER_NONE;
512 host->complete_what = COMPLETION_FINALIZE;
513
514 return;
515 }
516 }
517
518 enable_imask(host,
519 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
520}
521
522static void do_pio_write(struct s3cmci_host *host)
523{
524 void __iomem *to_ptr;
525 int res;
526 u32 fifo;
527 u32 *ptr;
528
529 to_ptr = host->base + host->sdidata;
530
531 while ((fifo = fifo_free(host)) > 3) {
532 if (!host->pio_bytes) {
533 res = get_data_buffer(host, &host->pio_bytes,
534 &host->pio_ptr);
535 if (res) {
536 dbg(host, dbg_pio,
537 "pio_write(): complete (no more data).\n");
538 host->pio_active = XFER_NONE;
539
540 return;
541 }
542
543 dbg(host, dbg_pio,
544 "pio_write(): new source: [%i]@[%p]\n",
545 host->pio_bytes, host->pio_ptr);
546
547 }
548
549 /* If we have reached the end of the block, we have to
550 * write exactly the remaining number of bytes. If we
551 * in the middle of the block, we have to write full
552 * words, so round down to an even multiple of 4. */
553 if (fifo >= host->pio_bytes)
554 fifo = host->pio_bytes;
555 else
556 fifo -= fifo & 3;
557
558 host->pio_bytes -= fifo;
559 host->pio_count += fifo;
560
561 fifo = (fifo + 3) >> 2;
562 ptr = host->pio_ptr;
563 while (fifo--)
564 writel(*ptr++, to_ptr);
565 host->pio_ptr = ptr;
566 }
567
568 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
569}
570
571static void pio_tasklet(unsigned long data)
572{
573 struct s3cmci_host *host = (struct s3cmci_host *) data;
574
575 s3cmci_disable_irq(host, true);
576
577 if (host->pio_active == XFER_WRITE)
578 do_pio_write(host);
579
580 if (host->pio_active == XFER_READ)
581 do_pio_read(host);
582
583 if (host->complete_what == COMPLETION_FINALIZE) {
584 clear_imask(host);
585 if (host->pio_active != XFER_NONE) {
586 dbg(host, dbg_err, "unfinished %s "
587 "- pio_count:[%u] pio_bytes:[%u]\n",
588 (host->pio_active == XFER_READ) ? "read" : "write",
589 host->pio_count, host->pio_bytes);
590
591 if (host->mrq->data)
592 host->mrq->data->error = -EINVAL;
593 }
594
595 s3cmci_enable_irq(host, false);
596 finalize_request(host);
597 } else
598 s3cmci_enable_irq(host, true);
599}
600
601/*
602 * ISR for SDI Interface IRQ
603 * Communication between driver and ISR works as follows:
604 * host->mrq points to current request
605 * host->complete_what Indicates when the request is considered done
606 * COMPLETION_CMDSENT when the command was sent
607 * COMPLETION_RSPFIN when a response was received
608 * COMPLETION_XFERFINISH when the data transfer is finished
609 * COMPLETION_XFERFINISH_RSPFIN both of the above.
610 * host->complete_request is the completion-object the driver waits for
611 *
612 * 1) Driver sets up host->mrq and host->complete_what
613 * 2) Driver prepares the transfer
614 * 3) Driver enables interrupts
615 * 4) Driver starts transfer
616 * 5) Driver waits for host->complete_rquest
617 * 6) ISR checks for request status (errors and success)
618 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
619 * 7) ISR completes host->complete_request
620 * 8) ISR disables interrupts
621 * 9) Driver wakes up and takes care of the request
622 *
623 * Note: "->error"-fields are expected to be set to 0 before the request
624 * was issued by mmc.c - therefore they are only set, when an error
625 * contition comes up
626 */
627
628static irqreturn_t s3cmci_irq(int irq, void *dev_id)
629{
630 struct s3cmci_host *host = dev_id;
631 struct mmc_command *cmd;
632 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
633 u32 mci_cclear = 0, mci_dclear;
634 unsigned long iflags;
635
636 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
637 mci_imsk = readl(host->base + host->sdiimsk);
638
639 if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
640 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
641 mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
642 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
643
644 mmc_signal_sdio_irq(host->mmc);
645 return IRQ_HANDLED;
646 }
647 }
648
649 spin_lock_irqsave(&host->complete_lock, iflags);
650
651 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
652 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
653 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
654 mci_dclear = 0;
655
656 if ((host->complete_what == COMPLETION_NONE) ||
657 (host->complete_what == COMPLETION_FINALIZE)) {
658 host->status = "nothing to complete";
659 clear_imask(host);
660 goto irq_out;
661 }
662
663 if (!host->mrq) {
664 host->status = "no active mrq";
665 clear_imask(host);
666 goto irq_out;
667 }
668
669 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
670
671 if (!cmd) {
672 host->status = "no active cmd";
673 clear_imask(host);
674 goto irq_out;
675 }
676
677 if (!s3cmci_host_usedma(host)) {
678 if ((host->pio_active == XFER_WRITE) &&
679 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
680
681 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
682 tasklet_schedule(&host->pio_tasklet);
683 host->status = "pio tx";
684 }
685
686 if ((host->pio_active == XFER_READ) &&
687 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
688
689 disable_imask(host,
690 S3C2410_SDIIMSK_RXFIFOHALF |
691 S3C2410_SDIIMSK_RXFIFOLAST);
692
693 tasklet_schedule(&host->pio_tasklet);
694 host->status = "pio rx";
695 }
696 }
697
698 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
699 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
700 cmd->error = -ETIMEDOUT;
701 host->status = "error: command timeout";
702 goto fail_transfer;
703 }
704
705 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
706 if (host->complete_what == COMPLETION_CMDSENT) {
707 host->status = "ok: command sent";
708 goto close_transfer;
709 }
710
711 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
712 }
713
714 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
715 if (cmd->flags & MMC_RSP_CRC) {
716 if (host->mrq->cmd->flags & MMC_RSP_136) {
717 dbg(host, dbg_irq,
718 "fixup: ignore CRC fail with long rsp\n");
719 } else {
720 /* note, we used to fail the transfer
721 * here, but it seems that this is just
722 * the hardware getting it wrong.
723 *
724 * cmd->error = -EILSEQ;
725 * host->status = "error: bad command crc";
726 * goto fail_transfer;
727 */
728 }
729 }
730
731 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
732 }
733
734 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
735 if (host->complete_what == COMPLETION_RSPFIN) {
736 host->status = "ok: command response received";
737 goto close_transfer;
738 }
739
740 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
741 host->complete_what = COMPLETION_XFERFINISH;
742
743 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
744 }
745
746 /* errors handled after this point are only relevant
747 when a data transfer is in progress */
748
749 if (!cmd->data)
750 goto clear_status_bits;
751
752 /* Check for FIFO failure */
753 if (host->is2440) {
754 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
755 dbg(host, dbg_err, "FIFO failure\n");
756 host->mrq->data->error = -EILSEQ;
757 host->status = "error: 2440 fifo failure";
758 goto fail_transfer;
759 }
760 } else {
761 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
762 dbg(host, dbg_err, "FIFO failure\n");
763 cmd->data->error = -EILSEQ;
764 host->status = "error: fifo failure";
765 goto fail_transfer;
766 }
767 }
768
769 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
770 dbg(host, dbg_err, "bad data crc (outgoing)\n");
771 cmd->data->error = -EILSEQ;
772 host->status = "error: bad data crc (outgoing)";
773 goto fail_transfer;
774 }
775
776 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
777 dbg(host, dbg_err, "bad data crc (incoming)\n");
778 cmd->data->error = -EILSEQ;
779 host->status = "error: bad data crc (incoming)";
780 goto fail_transfer;
781 }
782
783 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
784 dbg(host, dbg_err, "data timeout\n");
785 cmd->data->error = -ETIMEDOUT;
786 host->status = "error: data timeout";
787 goto fail_transfer;
788 }
789
790 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
791 if (host->complete_what == COMPLETION_XFERFINISH) {
792 host->status = "ok: data transfer completed";
793 goto close_transfer;
794 }
795
796 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
797 host->complete_what = COMPLETION_RSPFIN;
798
799 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
800 }
801
802clear_status_bits:
803 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
804 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
805
806 goto irq_out;
807
808fail_transfer:
809 host->pio_active = XFER_NONE;
810
811close_transfer:
812 host->complete_what = COMPLETION_FINALIZE;
813
814 clear_imask(host);
815 tasklet_schedule(&host->pio_tasklet);
816
817 goto irq_out;
818
819irq_out:
820 dbg(host, dbg_irq,
821 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
822 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
823
824 spin_unlock_irqrestore(&host->complete_lock, iflags);
825 return IRQ_HANDLED;
826
827}
828
829/*
830 * ISR for the CardDetect Pin
831*/
832
833static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
834{
835 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
836
837 dbg(host, dbg_irq, "card detect\n");
838
839 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
840
841 return IRQ_HANDLED;
842}
843
844static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
845 void *buf_id, int size,
846 enum s3c2410_dma_buffresult result)
847{
848 struct s3cmci_host *host = buf_id;
849 unsigned long iflags;
850 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
851
852 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
853 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
854 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
855 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
856
857 BUG_ON(!host->mrq);
858 BUG_ON(!host->mrq->data);
859 BUG_ON(!host->dmatogo);
860
861 spin_lock_irqsave(&host->complete_lock, iflags);
862
863 if (result != S3C2410_RES_OK) {
864 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
865 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
866 mci_csta, mci_dsta, mci_fsta,
867 mci_dcnt, result, host->dmatogo);
868
869 goto fail_request;
870 }
871
872 host->dmatogo--;
873 if (host->dmatogo) {
874 dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
875 "DCNT:[%08x] toGo:%u\n",
876 size, mci_dsta, mci_dcnt, host->dmatogo);
877
878 goto out;
879 }
880
881 dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
882 size, mci_dsta, mci_dcnt);
883
884 host->dma_complete = 1;
885 host->complete_what = COMPLETION_FINALIZE;
886
887out:
888 tasklet_schedule(&host->pio_tasklet);
889 spin_unlock_irqrestore(&host->complete_lock, iflags);
890 return;
891
892fail_request:
893 host->mrq->data->error = -EINVAL;
894 host->complete_what = COMPLETION_FINALIZE;
895 clear_imask(host);
896
897 goto out;
898}
899
900static void finalize_request(struct s3cmci_host *host)
901{
902 struct mmc_request *mrq = host->mrq;
903 struct mmc_command *cmd;
904 int debug_as_failure = 0;
905
906 if (host->complete_what != COMPLETION_FINALIZE)
907 return;
908
909 if (!mrq)
910 return;
911 cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
912
913 if (cmd->data && (cmd->error == 0) &&
914 (cmd->data->error == 0)) {
915 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
916 dbg(host, dbg_dma, "DMA Missing (%d)!\n",
917 host->dma_complete);
918 return;
919 }
920 }
921
922 /* Read response from controller. */
923 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
924 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
925 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
926 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
927
928 writel(host->prescaler, host->base + S3C2410_SDIPRE);
929
930 if (cmd->error)
931 debug_as_failure = 1;
932
933 if (cmd->data && cmd->data->error)
934 debug_as_failure = 1;
935
936 dbg_dumpcmd(host, cmd, debug_as_failure);
937
938 /* Cleanup controller */
939 writel(0, host->base + S3C2410_SDICMDARG);
940 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
941 writel(0, host->base + S3C2410_SDICMDCON);
942 clear_imask(host);
943
944 if (cmd->data && cmd->error)
945 cmd->data->error = cmd->error;
946
947 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
948 host->cmd_is_stop = 1;
949 s3cmci_send_request(host->mmc);
950 return;
951 }
952
953 /* If we have no data transfer we are finished here */
954 if (!mrq->data)
955 goto request_done;
956
957 /* Calculate the amout of bytes transfer if there was no error */
958 if (mrq->data->error == 0) {
959 mrq->data->bytes_xfered =
960 (mrq->data->blocks * mrq->data->blksz);
961 } else {
962 mrq->data->bytes_xfered = 0;
963 }
964
965 /* If we had an error while transferring data we flush the
966 * DMA channel and the fifo to clear out any garbage. */
967 if (mrq->data->error != 0) {
968 if (s3cmci_host_usedma(host))
969 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
970
971 if (host->is2440) {
972 /* Clear failure register and reset fifo. */
973 writel(S3C2440_SDIFSTA_FIFORESET |
974 S3C2440_SDIFSTA_FIFOFAIL,
975 host->base + S3C2410_SDIFSTA);
976 } else {
977 u32 mci_con;
978
979 /* reset fifo */
980 mci_con = readl(host->base + S3C2410_SDICON);
981 mci_con |= S3C2410_SDICON_FIFORESET;
982
983 writel(mci_con, host->base + S3C2410_SDICON);
984 }
985 }
986
987request_done:
988 host->complete_what = COMPLETION_NONE;
989 host->mrq = NULL;
990
991 s3cmci_check_sdio_irq(host);
992 mmc_request_done(host->mmc, mrq);
993}
994
995static void s3cmci_dma_setup(struct s3cmci_host *host,
996 enum dma_data_direction source)
997{
998 static enum dma_data_direction last_source = -1;
999 static int setup_ok;
1000
1001 if (last_source == source)
1002 return;
1003
1004 last_source = source;
1005
1006 s3c2410_dma_devconfig(host->dma, source,
1007 host->mem->start + host->sdidata);
1008
1009 if (!setup_ok) {
1010 s3c2410_dma_config(host->dma, 4);
1011 s3c2410_dma_set_buffdone_fn(host->dma,
1012 s3cmci_dma_done_callback);
1013 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
1014 setup_ok = 1;
1015 }
1016}
1017
1018static void s3cmci_send_command(struct s3cmci_host *host,
1019 struct mmc_command *cmd)
1020{
1021 u32 ccon, imsk;
1022
1023 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
1024 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
1025 S3C2410_SDIIMSK_RESPONSECRC;
1026
1027 enable_imask(host, imsk);
1028
1029 if (cmd->data)
1030 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
1031 else if (cmd->flags & MMC_RSP_PRESENT)
1032 host->complete_what = COMPLETION_RSPFIN;
1033 else
1034 host->complete_what = COMPLETION_CMDSENT;
1035
1036 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
1037
1038 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
1039 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
1040
1041 if (cmd->flags & MMC_RSP_PRESENT)
1042 ccon |= S3C2410_SDICMDCON_WAITRSP;
1043
1044 if (cmd->flags & MMC_RSP_136)
1045 ccon |= S3C2410_SDICMDCON_LONGRSP;
1046
1047 writel(ccon, host->base + S3C2410_SDICMDCON);
1048}
1049
1050static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
1051{
1052 u32 dcon, imsk, stoptries = 3;
1053
1054 /* write DCON register */
1055
1056 if (!data) {
1057 writel(0, host->base + S3C2410_SDIDCON);
1058 return 0;
1059 }
1060
1061 if ((data->blksz & 3) != 0) {
1062 /* We cannot deal with unaligned blocks with more than
1063 * one block being transferred. */
1064
1065 if (data->blocks > 1) {
1066 pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
1067 return -EINVAL;
1068 }
1069 }
1070
1071 while (readl(host->base + S3C2410_SDIDSTA) &
1072 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
1073
1074 dbg(host, dbg_err,
1075 "mci_setup_data() transfer stillin progress.\n");
1076
1077 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
1078 s3cmci_reset(host);
1079
1080 if ((stoptries--) == 0) {
1081 dbg_dumpregs(host, "DRF");
1082 return -EINVAL;
1083 }
1084 }
1085
1086 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1087
1088 if (s3cmci_host_usedma(host))
1089 dcon |= S3C2410_SDIDCON_DMAEN;
1090
1091 if (host->bus_width == MMC_BUS_WIDTH_4)
1092 dcon |= S3C2410_SDIDCON_WIDEBUS;
1093
1094 if (!(data->flags & MMC_DATA_STREAM))
1095 dcon |= S3C2410_SDIDCON_BLOCKMODE;
1096
1097 if (data->flags & MMC_DATA_WRITE) {
1098 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1099 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1100 }
1101
1102 if (data->flags & MMC_DATA_READ) {
1103 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1104 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1105 }
1106
1107 if (host->is2440) {
1108 dcon |= S3C2440_SDIDCON_DS_WORD;
1109 dcon |= S3C2440_SDIDCON_DATSTART;
1110 }
1111
1112 writel(dcon, host->base + S3C2410_SDIDCON);
1113
1114 /* write BSIZE register */
1115
1116 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1117
1118 /* add to IMASK register */
1119 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1120 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1121
1122 enable_imask(host, imsk);
1123
1124 /* write TIMER register */
1125
1126 if (host->is2440) {
1127 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1128 } else {
1129 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1130
1131 /* FIX: set slow clock to prevent timeouts on read */
1132 if (data->flags & MMC_DATA_READ)
1133 writel(0xFF, host->base + S3C2410_SDIPRE);
1134 }
1135
1136 return 0;
1137}
1138
1139#define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1140
1141static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1142{
1143 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1144
1145 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1146
1147 host->pio_sgptr = 0;
1148 host->pio_bytes = 0;
1149 host->pio_count = 0;
1150 host->pio_active = rw ? XFER_WRITE : XFER_READ;
1151
1152 if (rw) {
1153 do_pio_write(host);
1154 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1155 } else {
1156 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1157 | S3C2410_SDIIMSK_RXFIFOLAST);
1158 }
1159
1160 return 0;
1161}
1162
1163static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1164{
1165 int dma_len, i;
1166 int rw = data->flags & MMC_DATA_WRITE;
1167
1168 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1169
1170 s3cmci_dma_setup(host, rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1171 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1172
1173 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1174 rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1175
1176 if (dma_len == 0)
1177 return -ENOMEM;
1178
1179 host->dma_complete = 0;
1180 host->dmatogo = dma_len;
1181
1182 for (i = 0; i < dma_len; i++) {
1183 int res;
1184
1185 dbg(host, dbg_dma, "enqueue %i: %08x@%u\n", i,
1186 sg_dma_address(&data->sg[i]),
1187 sg_dma_len(&data->sg[i]));
1188
1189 res = s3c2410_dma_enqueue(host->dma, host,
1190 sg_dma_address(&data->sg[i]),
1191 sg_dma_len(&data->sg[i]));
1192
1193 if (res) {
1194 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
1195 return -EBUSY;
1196 }
1197 }
1198
1199 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
1200
1201 return 0;
1202}
1203
1204static void s3cmci_send_request(struct mmc_host *mmc)
1205{
1206 struct s3cmci_host *host = mmc_priv(mmc);
1207 struct mmc_request *mrq = host->mrq;
1208 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1209
1210 host->ccnt++;
1211 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1212
1213 /* Clear command, data and fifo status registers
1214 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1215 */
1216 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1217 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1218 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1219
1220 if (cmd->data) {
1221 int res = s3cmci_setup_data(host, cmd->data);
1222
1223 host->dcnt++;
1224
1225 if (res) {
1226 dbg(host, dbg_err, "setup data error %d\n", res);
1227 cmd->error = res;
1228 cmd->data->error = res;
1229
1230 mmc_request_done(mmc, mrq);
1231 return;
1232 }
1233
1234 if (s3cmci_host_usedma(host))
1235 res = s3cmci_prepare_dma(host, cmd->data);
1236 else
1237 res = s3cmci_prepare_pio(host, cmd->data);
1238
1239 if (res) {
1240 dbg(host, dbg_err, "data prepare error %d\n", res);
1241 cmd->error = res;
1242 cmd->data->error = res;
1243
1244 mmc_request_done(mmc, mrq);
1245 return;
1246 }
1247 }
1248
1249 /* Send command */
1250 s3cmci_send_command(host, cmd);
1251
1252 /* Enable Interrupt */
1253 s3cmci_enable_irq(host, true);
1254}
1255
1256static int s3cmci_card_present(struct mmc_host *mmc)
1257{
1258 struct s3cmci_host *host = mmc_priv(mmc);
1259 struct s3c24xx_mci_pdata *pdata = host->pdata;
1260 int ret;
1261
1262 if (pdata->no_detect)
1263 return -ENOSYS;
1264
1265 ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1266 return ret ^ pdata->detect_invert;
1267}
1268
1269static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1270{
1271 struct s3cmci_host *host = mmc_priv(mmc);
1272
1273 host->status = "mmc request";
1274 host->cmd_is_stop = 0;
1275 host->mrq = mrq;
1276
1277 if (s3cmci_card_present(mmc) == 0) {
1278 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1279 host->mrq->cmd->error = -ENOMEDIUM;
1280 mmc_request_done(mmc, mrq);
1281 } else
1282 s3cmci_send_request(mmc);
1283}
1284
1285static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1286{
1287 u32 mci_psc;
1288
1289 /* Set clock */
1290 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1291 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1292
1293 if (host->real_rate <= ios->clock)
1294 break;
1295 }
1296
1297 if (mci_psc > 255)
1298 mci_psc = 255;
1299
1300 host->prescaler = mci_psc;
1301 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1302
1303 /* If requested clock is 0, real_rate will be 0, too */
1304 if (ios->clock == 0)
1305 host->real_rate = 0;
1306}
1307
1308static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1309{
1310 struct s3cmci_host *host = mmc_priv(mmc);
1311 u32 mci_con;
1312
1313 /* Set the power state */
1314
1315 mci_con = readl(host->base + S3C2410_SDICON);
1316
1317 switch (ios->power_mode) {
1318 case MMC_POWER_ON:
1319 case MMC_POWER_UP:
1320 /* Configure GPE5...GPE10 pins in SD mode */
1321 s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1322 S3C_GPIO_PULL_NONE);
1323
1324 if (host->pdata->set_power)
1325 host->pdata->set_power(ios->power_mode, ios->vdd);
1326
1327 if (!host->is2440)
1328 mci_con |= S3C2410_SDICON_FIFORESET;
1329
1330 break;
1331
1332 case MMC_POWER_OFF:
1333 default:
1334 gpio_direction_output(S3C2410_GPE(5), 0);
1335
1336 if (host->is2440)
1337 mci_con |= S3C2440_SDICON_SDRESET;
1338
1339 if (host->pdata->set_power)
1340 host->pdata->set_power(ios->power_mode, ios->vdd);
1341
1342 break;
1343 }
1344
1345 s3cmci_set_clk(host, ios);
1346
1347 /* Set CLOCK_ENABLE */
1348 if (ios->clock)
1349 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1350 else
1351 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1352
1353 writel(mci_con, host->base + S3C2410_SDICON);
1354
1355 if ((ios->power_mode == MMC_POWER_ON) ||
1356 (ios->power_mode == MMC_POWER_UP)) {
1357 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1358 host->real_rate/1000, ios->clock/1000);
1359 } else {
1360 dbg(host, dbg_conf, "powered down.\n");
1361 }
1362
1363 host->bus_width = ios->bus_width;
1364}
1365
1366static void s3cmci_reset(struct s3cmci_host *host)
1367{
1368 u32 con = readl(host->base + S3C2410_SDICON);
1369
1370 con |= S3C2440_SDICON_SDRESET;
1371 writel(con, host->base + S3C2410_SDICON);
1372}
1373
1374static int s3cmci_get_ro(struct mmc_host *mmc)
1375{
1376 struct s3cmci_host *host = mmc_priv(mmc);
1377 struct s3c24xx_mci_pdata *pdata = host->pdata;
1378 int ret;
1379
1380 if (pdata->no_wprotect)
1381 return 0;
1382
1383 ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1384 ret ^= pdata->wprotect_invert;
1385
1386 return ret;
1387}
1388
1389static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1390{
1391 struct s3cmci_host *host = mmc_priv(mmc);
1392 unsigned long flags;
1393 u32 con;
1394
1395 local_irq_save(flags);
1396
1397 con = readl(host->base + S3C2410_SDICON);
1398 host->sdio_irqen = enable;
1399
1400 if (enable == host->sdio_irqen)
1401 goto same_state;
1402
1403 if (enable) {
1404 con |= S3C2410_SDICON_SDIOIRQ;
1405 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1406
1407 if (!host->irq_state && !host->irq_disabled) {
1408 host->irq_state = true;
1409 enable_irq(host->irq);
1410 }
1411 } else {
1412 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1413 con &= ~S3C2410_SDICON_SDIOIRQ;
1414
1415 if (!host->irq_enabled && host->irq_state) {
1416 disable_irq_nosync(host->irq);
1417 host->irq_state = false;
1418 }
1419 }
1420
1421 writel(con, host->base + S3C2410_SDICON);
1422
1423 same_state:
1424 local_irq_restore(flags);
1425
1426 s3cmci_check_sdio_irq(host);
1427}
1428
1429static struct mmc_host_ops s3cmci_ops = {
1430 .request = s3cmci_request,
1431 .set_ios = s3cmci_set_ios,
1432 .get_ro = s3cmci_get_ro,
1433 .get_cd = s3cmci_card_present,
1434 .enable_sdio_irq = s3cmci_enable_sdio_irq,
1435};
1436
1437static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1438 /* This is currently here to avoid a number of if (host->pdata)
1439 * checks. Any zero fields to ensure reasonable defaults are picked. */
1440 .no_wprotect = 1,
1441 .no_detect = 1,
1442};
1443
1444#ifdef CONFIG_CPU_FREQ
1445
1446static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1447 unsigned long val, void *data)
1448{
1449 struct s3cmci_host *host;
1450 struct mmc_host *mmc;
1451 unsigned long newclk;
1452 unsigned long flags;
1453
1454 host = container_of(nb, struct s3cmci_host, freq_transition);
1455 newclk = clk_get_rate(host->clk);
1456 mmc = host->mmc;
1457
1458 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1459 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1460 spin_lock_irqsave(&mmc->lock, flags);
1461
1462 host->clk_rate = newclk;
1463
1464 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1465 mmc->ios.clock != 0)
1466 s3cmci_set_clk(host, &mmc->ios);
1467
1468 spin_unlock_irqrestore(&mmc->lock, flags);
1469 }
1470
1471 return 0;
1472}
1473
1474static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1475{
1476 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1477
1478 return cpufreq_register_notifier(&host->freq_transition,
1479 CPUFREQ_TRANSITION_NOTIFIER);
1480}
1481
1482static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1483{
1484 cpufreq_unregister_notifier(&host->freq_transition,
1485 CPUFREQ_TRANSITION_NOTIFIER);
1486}
1487
1488#else
1489static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1490{
1491 return 0;
1492}
1493
1494static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1495{
1496}
1497#endif
1498
1499
1500#ifdef CONFIG_DEBUG_FS
1501
1502static int s3cmci_state_show(struct seq_file *seq, void *v)
1503{
1504 struct s3cmci_host *host = seq->private;
1505
1506 seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1507 seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1508 seq_printf(seq, "Prescale = %d\n", host->prescaler);
1509 seq_printf(seq, "is2440 = %d\n", host->is2440);
1510 seq_printf(seq, "IRQ = %d\n", host->irq);
1511 seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1512 seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1513 seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1514 seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1515 seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1516 seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1517 seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1518
1519 return 0;
1520}
1521
1522static int s3cmci_state_open(struct inode *inode, struct file *file)
1523{
1524 return single_open(file, s3cmci_state_show, inode->i_private);
1525}
1526
1527static const struct file_operations s3cmci_fops_state = {
1528 .owner = THIS_MODULE,
1529 .open = s3cmci_state_open,
1530 .read = seq_read,
1531 .llseek = seq_lseek,
1532 .release = single_release,
1533};
1534
1535#define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1536
1537struct s3cmci_reg {
1538 unsigned short addr;
1539 unsigned char *name;
1540} debug_regs[] = {
1541 DBG_REG(CON),
1542 DBG_REG(PRE),
1543 DBG_REG(CMDARG),
1544 DBG_REG(CMDCON),
1545 DBG_REG(CMDSTAT),
1546 DBG_REG(RSP0),
1547 DBG_REG(RSP1),
1548 DBG_REG(RSP2),
1549 DBG_REG(RSP3),
1550 DBG_REG(TIMER),
1551 DBG_REG(BSIZE),
1552 DBG_REG(DCON),
1553 DBG_REG(DCNT),
1554 DBG_REG(DSTA),
1555 DBG_REG(FSTA),
1556 {}
1557};
1558
1559static int s3cmci_regs_show(struct seq_file *seq, void *v)
1560{
1561 struct s3cmci_host *host = seq->private;
1562 struct s3cmci_reg *rptr = debug_regs;
1563
1564 for (; rptr->name; rptr++)
1565 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1566 readl(host->base + rptr->addr));
1567
1568 seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1569
1570 return 0;
1571}
1572
1573static int s3cmci_regs_open(struct inode *inode, struct file *file)
1574{
1575 return single_open(file, s3cmci_regs_show, inode->i_private);
1576}
1577
1578static const struct file_operations s3cmci_fops_regs = {
1579 .owner = THIS_MODULE,
1580 .open = s3cmci_regs_open,
1581 .read = seq_read,
1582 .llseek = seq_lseek,
1583 .release = single_release,
1584};
1585
1586static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1587{
1588 struct device *dev = &host->pdev->dev;
1589
1590 host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1591 if (IS_ERR(host->debug_root)) {
1592 dev_err(dev, "failed to create debugfs root\n");
1593 return;
1594 }
1595
1596 host->debug_state = debugfs_create_file("state", 0444,
1597 host->debug_root, host,
1598 &s3cmci_fops_state);
1599
1600 if (IS_ERR(host->debug_state))
1601 dev_err(dev, "failed to create debug state file\n");
1602
1603 host->debug_regs = debugfs_create_file("regs", 0444,
1604 host->debug_root, host,
1605 &s3cmci_fops_regs);
1606
1607 if (IS_ERR(host->debug_regs))
1608 dev_err(dev, "failed to create debug regs file\n");
1609}
1610
1611static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1612{
1613 debugfs_remove(host->debug_regs);
1614 debugfs_remove(host->debug_state);
1615 debugfs_remove(host->debug_root);
1616}
1617
1618#else
1619static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1620static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1621
1622#endif /* CONFIG_DEBUG_FS */
1623
1624static int s3cmci_probe(struct platform_device *pdev)
1625{
1626 struct s3cmci_host *host;
1627 struct mmc_host *mmc;
1628 int ret;
1629 int is2440;
1630 int i;
1631
1632 is2440 = platform_get_device_id(pdev)->driver_data;
1633
1634 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1635 if (!mmc) {
1636 ret = -ENOMEM;
1637 goto probe_out;
1638 }
1639
1640 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1641 ret = gpio_request(i, dev_name(&pdev->dev));
1642 if (ret) {
1643 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1644
1645 for (i--; i >= S3C2410_GPE(5); i--)
1646 gpio_free(i);
1647
1648 goto probe_free_host;
1649 }
1650 }
1651
1652 host = mmc_priv(mmc);
1653 host->mmc = mmc;
1654 host->pdev = pdev;
1655 host->is2440 = is2440;
1656
1657 host->pdata = pdev->dev.platform_data;
1658 if (!host->pdata) {
1659 pdev->dev.platform_data = &s3cmci_def_pdata;
1660 host->pdata = &s3cmci_def_pdata;
1661 }
1662
1663 spin_lock_init(&host->complete_lock);
1664 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1665
1666 if (is2440) {
1667 host->sdiimsk = S3C2440_SDIIMSK;
1668 host->sdidata = S3C2440_SDIDATA;
1669 host->clk_div = 1;
1670 } else {
1671 host->sdiimsk = S3C2410_SDIIMSK;
1672 host->sdidata = S3C2410_SDIDATA;
1673 host->clk_div = 2;
1674 }
1675
1676 host->complete_what = COMPLETION_NONE;
1677 host->pio_active = XFER_NONE;
1678
1679#ifdef CONFIG_MMC_S3C_PIODMA
1680 host->dodma = host->pdata->use_dma;
1681#endif
1682
1683 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1684 if (!host->mem) {
1685 dev_err(&pdev->dev,
1686 "failed to get io memory region resource.\n");
1687
1688 ret = -ENOENT;
1689 goto probe_free_gpio;
1690 }
1691
1692 host->mem = request_mem_region(host->mem->start,
1693 resource_size(host->mem), pdev->name);
1694
1695 if (!host->mem) {
1696 dev_err(&pdev->dev, "failed to request io memory region.\n");
1697 ret = -ENOENT;
1698 goto probe_free_gpio;
1699 }
1700
1701 host->base = ioremap(host->mem->start, resource_size(host->mem));
1702 if (!host->base) {
1703 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1704 ret = -EINVAL;
1705 goto probe_free_mem_region;
1706 }
1707
1708 host->irq = platform_get_irq(pdev, 0);
1709 if (host->irq == 0) {
1710 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1711 ret = -EINVAL;
1712 goto probe_iounmap;
1713 }
1714
1715 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1716 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1717 ret = -ENOENT;
1718 goto probe_iounmap;
1719 }
1720
1721 /* We get spurious interrupts even when we have set the IMSK
1722 * register to ignore everything, so use disable_irq() to make
1723 * ensure we don't lock the system with un-serviceable requests. */
1724
1725 disable_irq(host->irq);
1726 host->irq_state = false;
1727
1728 if (!host->pdata->no_detect) {
1729 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1730 if (ret) {
1731 dev_err(&pdev->dev, "failed to get detect gpio\n");
1732 goto probe_free_irq;
1733 }
1734
1735 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1736
1737 if (host->irq_cd >= 0) {
1738 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1739 IRQF_TRIGGER_RISING |
1740 IRQF_TRIGGER_FALLING,
1741 DRIVER_NAME, host)) {
1742 dev_err(&pdev->dev,
1743 "can't get card detect irq.\n");
1744 ret = -ENOENT;
1745 goto probe_free_gpio_cd;
1746 }
1747 } else {
1748 dev_warn(&pdev->dev,
1749 "host detect has no irq available\n");
1750 gpio_direction_input(host->pdata->gpio_detect);
1751 }
1752 } else
1753 host->irq_cd = -1;
1754
1755 if (!host->pdata->no_wprotect) {
1756 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1757 if (ret) {
1758 dev_err(&pdev->dev, "failed to get writeprotect\n");
1759 goto probe_free_irq_cd;
1760 }
1761
1762 gpio_direction_input(host->pdata->gpio_wprotect);
1763 }
1764
1765 /* depending on the dma state, get a dma channel to use. */
1766
1767 if (s3cmci_host_usedma(host)) {
1768 host->dma = s3c2410_dma_request(DMACH_SDI, &s3cmci_dma_client,
1769 host);
1770 if (host->dma < 0) {
1771 dev_err(&pdev->dev, "cannot get DMA channel.\n");
1772 if (!s3cmci_host_canpio()) {
1773 ret = -EBUSY;
1774 goto probe_free_gpio_wp;
1775 } else {
1776 dev_warn(&pdev->dev, "falling back to PIO.\n");
1777 host->dodma = 0;
1778 }
1779 }
1780 }
1781
1782 host->clk = clk_get(&pdev->dev, "sdi");
1783 if (IS_ERR(host->clk)) {
1784 dev_err(&pdev->dev, "failed to find clock source.\n");
1785 ret = PTR_ERR(host->clk);
1786 host->clk = NULL;
1787 goto probe_free_dma;
1788 }
1789
1790 ret = clk_enable(host->clk);
1791 if (ret) {
1792 dev_err(&pdev->dev, "failed to enable clock source.\n");
1793 goto clk_free;
1794 }
1795
1796 host->clk_rate = clk_get_rate(host->clk);
1797
1798 mmc->ops = &s3cmci_ops;
1799 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1800#ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1801 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1802#else
1803 mmc->caps = MMC_CAP_4_BIT_DATA;
1804#endif
1805 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1806 mmc->f_max = host->clk_rate / host->clk_div;
1807
1808 if (host->pdata->ocr_avail)
1809 mmc->ocr_avail = host->pdata->ocr_avail;
1810
1811 mmc->max_blk_count = 4095;
1812 mmc->max_blk_size = 4095;
1813 mmc->max_req_size = 4095 * 512;
1814 mmc->max_seg_size = mmc->max_req_size;
1815
1816 mmc->max_segs = 128;
1817
1818 dbg(host, dbg_debug,
1819 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1820 (host->is2440?"2440":""),
1821 host->base, host->irq, host->irq_cd, host->dma);
1822
1823 ret = s3cmci_cpufreq_register(host);
1824 if (ret) {
1825 dev_err(&pdev->dev, "failed to register cpufreq\n");
1826 goto free_dmabuf;
1827 }
1828
1829 ret = mmc_add_host(mmc);
1830 if (ret) {
1831 dev_err(&pdev->dev, "failed to add mmc host.\n");
1832 goto free_cpufreq;
1833 }
1834
1835 s3cmci_debugfs_attach(host);
1836
1837 platform_set_drvdata(pdev, mmc);
1838 dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1839 s3cmci_host_usedma(host) ? "dma" : "pio",
1840 mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1841
1842 return 0;
1843
1844 free_cpufreq:
1845 s3cmci_cpufreq_deregister(host);
1846
1847 free_dmabuf:
1848 clk_disable(host->clk);
1849
1850 clk_free:
1851 clk_put(host->clk);
1852
1853 probe_free_dma:
1854 if (s3cmci_host_usedma(host))
1855 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1856
1857 probe_free_gpio_wp:
1858 if (!host->pdata->no_wprotect)
1859 gpio_free(host->pdata->gpio_wprotect);
1860
1861 probe_free_gpio_cd:
1862 if (!host->pdata->no_detect)
1863 gpio_free(host->pdata->gpio_detect);
1864
1865 probe_free_irq_cd:
1866 if (host->irq_cd >= 0)
1867 free_irq(host->irq_cd, host);
1868
1869 probe_free_irq:
1870 free_irq(host->irq, host);
1871
1872 probe_iounmap:
1873 iounmap(host->base);
1874
1875 probe_free_mem_region:
1876 release_mem_region(host->mem->start, resource_size(host->mem));
1877
1878 probe_free_gpio:
1879 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1880 gpio_free(i);
1881
1882 probe_free_host:
1883 mmc_free_host(mmc);
1884
1885 probe_out:
1886 return ret;
1887}
1888
1889static void s3cmci_shutdown(struct platform_device *pdev)
1890{
1891 struct mmc_host *mmc = platform_get_drvdata(pdev);
1892 struct s3cmci_host *host = mmc_priv(mmc);
1893
1894 if (host->irq_cd >= 0)
1895 free_irq(host->irq_cd, host);
1896
1897 s3cmci_debugfs_remove(host);
1898 s3cmci_cpufreq_deregister(host);
1899 mmc_remove_host(mmc);
1900 clk_disable(host->clk);
1901}
1902
1903static int s3cmci_remove(struct platform_device *pdev)
1904{
1905 struct mmc_host *mmc = platform_get_drvdata(pdev);
1906 struct s3cmci_host *host = mmc_priv(mmc);
1907 struct s3c24xx_mci_pdata *pd = host->pdata;
1908 int i;
1909
1910 s3cmci_shutdown(pdev);
1911
1912 clk_put(host->clk);
1913
1914 tasklet_disable(&host->pio_tasklet);
1915
1916 if (s3cmci_host_usedma(host))
1917 s3c2410_dma_free(host->dma, &s3cmci_dma_client);
1918
1919 free_irq(host->irq, host);
1920
1921 if (!pd->no_wprotect)
1922 gpio_free(pd->gpio_wprotect);
1923
1924 if (!pd->no_detect)
1925 gpio_free(pd->gpio_detect);
1926
1927 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1928 gpio_free(i);
1929
1930
1931 iounmap(host->base);
1932 release_mem_region(host->mem->start, resource_size(host->mem));
1933
1934 mmc_free_host(mmc);
1935 return 0;
1936}
1937
1938static struct platform_device_id s3cmci_driver_ids[] = {
1939 {
1940 .name = "s3c2410-sdi",
1941 .driver_data = 0,
1942 }, {
1943 .name = "s3c2412-sdi",
1944 .driver_data = 1,
1945 }, {
1946 .name = "s3c2440-sdi",
1947 .driver_data = 1,
1948 },
1949 { }
1950};
1951
1952MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1953
1954static struct platform_driver s3cmci_driver = {
1955 .driver = {
1956 .name = "s3c-sdi",
1957 .owner = THIS_MODULE,
1958 },
1959 .id_table = s3cmci_driver_ids,
1960 .probe = s3cmci_probe,
1961 .remove = s3cmci_remove,
1962 .shutdown = s3cmci_shutdown,
1963};
1964
1965module_platform_driver(s3cmci_driver);
1966
1967MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1968MODULE_LICENSE("GPL v2");
1969MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");