Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/plat-pxa/gpio.c
4 *
5 * Generic PXA GPIO handling
6 *
7 * Author: Nicolas Pitre
8 * Created: Jun 15, 2001
9 * Copyright: MontaVista Software Inc.
10 */
11#include <linux/module.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/gpio/driver.h>
15#include <linux/gpio-pxa.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/irqchip/chained_irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/platform_device.h>
26#include <linux/syscore_ops.h>
27#include <linux/slab.h>
28
29/*
30 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
31 * one set of registers. The register offsets are organized below:
32 *
33 * GPLR GPDR GPSR GPCR GRER GFER GEDR
34 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
35 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
36 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
37 *
38 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
39 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
40 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
41 *
42 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
43 *
44 * NOTE:
45 * BANK 3 is only available on PXA27x and later processors.
46 * BANK 4 and 5 are only available on PXA935, PXA1928
47 * BANK 6 is only available on PXA1928
48 */
49
50#define GPLR_OFFSET 0x00
51#define GPDR_OFFSET 0x0C
52#define GPSR_OFFSET 0x18
53#define GPCR_OFFSET 0x24
54#define GRER_OFFSET 0x30
55#define GFER_OFFSET 0x3C
56#define GEDR_OFFSET 0x48
57#define GAFR_OFFSET 0x54
58#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
59
60#define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
61
62int pxa_last_gpio;
63static int irq_base;
64
65struct pxa_gpio_bank {
66 void __iomem *regbase;
67 unsigned long irq_mask;
68 unsigned long irq_edge_rise;
69 unsigned long irq_edge_fall;
70
71#ifdef CONFIG_PM
72 unsigned long saved_gplr;
73 unsigned long saved_gpdr;
74 unsigned long saved_grer;
75 unsigned long saved_gfer;
76#endif
77};
78
79struct pxa_gpio_chip {
80 struct device *dev;
81 struct gpio_chip chip;
82 struct pxa_gpio_bank *banks;
83 struct irq_domain *irqdomain;
84
85 int irq0;
86 int irq1;
87 int (*set_wake)(unsigned int gpio, unsigned int on);
88};
89
90enum pxa_gpio_type {
91 PXA25X_GPIO = 0,
92 PXA26X_GPIO,
93 PXA27X_GPIO,
94 PXA3XX_GPIO,
95 PXA93X_GPIO,
96 MMP_GPIO = 0x10,
97 MMP2_GPIO,
98 PXA1928_GPIO,
99};
100
101struct pxa_gpio_id {
102 enum pxa_gpio_type type;
103 int gpio_nums;
104};
105
106static DEFINE_SPINLOCK(gpio_lock);
107static struct pxa_gpio_chip *pxa_gpio_chip;
108static enum pxa_gpio_type gpio_type;
109
110static struct pxa_gpio_id pxa25x_id = {
111 .type = PXA25X_GPIO,
112 .gpio_nums = 85,
113};
114
115static struct pxa_gpio_id pxa26x_id = {
116 .type = PXA26X_GPIO,
117 .gpio_nums = 90,
118};
119
120static struct pxa_gpio_id pxa27x_id = {
121 .type = PXA27X_GPIO,
122 .gpio_nums = 121,
123};
124
125static struct pxa_gpio_id pxa3xx_id = {
126 .type = PXA3XX_GPIO,
127 .gpio_nums = 128,
128};
129
130static struct pxa_gpio_id pxa93x_id = {
131 .type = PXA93X_GPIO,
132 .gpio_nums = 192,
133};
134
135static struct pxa_gpio_id mmp_id = {
136 .type = MMP_GPIO,
137 .gpio_nums = 128,
138};
139
140static struct pxa_gpio_id mmp2_id = {
141 .type = MMP2_GPIO,
142 .gpio_nums = 192,
143};
144
145static struct pxa_gpio_id pxa1928_id = {
146 .type = PXA1928_GPIO,
147 .gpio_nums = 224,
148};
149
150#define for_each_gpio_bank(i, b, pc) \
151 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
152
153static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
154{
155 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
156
157 return pxa_chip;
158}
159
160static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
161{
162 struct pxa_gpio_chip *p = gpiochip_get_data(c);
163 struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
164
165 return bank->regbase;
166}
167
168static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
169 unsigned gpio)
170{
171 return chip_to_pxachip(c)->banks + gpio / 32;
172}
173
174static inline int gpio_is_pxa_type(int type)
175{
176 return (type & MMP_GPIO) == 0;
177}
178
179static inline int gpio_is_mmp_type(int type)
180{
181 return (type & MMP_GPIO) != 0;
182}
183
184/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
185 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
186 */
187static inline int __gpio_is_inverted(int gpio)
188{
189 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
190 return 1;
191 return 0;
192}
193
194/*
195 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
196 * function of a GPIO, and GPDRx cannot be altered once configured. It
197 * is attributed as "occupied" here (I know this terminology isn't
198 * accurate, you are welcome to propose a better one :-)
199 */
200static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
201{
202 void __iomem *base;
203 unsigned long gafr = 0, gpdr = 0;
204 int ret, af = 0, dir = 0;
205
206 base = gpio_bank_base(&pchip->chip, gpio);
207 gpdr = readl_relaxed(base + GPDR_OFFSET);
208
209 switch (gpio_type) {
210 case PXA25X_GPIO:
211 case PXA26X_GPIO:
212 case PXA27X_GPIO:
213 gafr = readl_relaxed(base + GAFR_OFFSET);
214 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
215 dir = gpdr & GPIO_bit(gpio);
216
217 if (__gpio_is_inverted(gpio))
218 ret = (af != 1) || (dir == 0);
219 else
220 ret = (af != 0) || (dir != 0);
221 break;
222 default:
223 ret = gpdr & GPIO_bit(gpio);
224 break;
225 }
226 return ret;
227}
228
229int pxa_irq_to_gpio(int irq)
230{
231 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
232 int irq_gpio0;
233
234 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
235 if (irq_gpio0 > 0)
236 return irq - irq_gpio0;
237
238 return irq_gpio0;
239}
240
241static bool pxa_gpio_has_pinctrl(void)
242{
243 switch (gpio_type) {
244 case PXA3XX_GPIO:
245 case MMP2_GPIO:
246 return false;
247
248 default:
249 return true;
250 }
251}
252
253static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
254{
255 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
256
257 return irq_find_mapping(pchip->irqdomain, offset);
258}
259
260static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
261{
262 void __iomem *base = gpio_bank_base(chip, offset);
263 uint32_t value, mask = GPIO_bit(offset);
264 unsigned long flags;
265 int ret;
266
267 if (pxa_gpio_has_pinctrl()) {
268 ret = pinctrl_gpio_direction_input(chip->base + offset);
269 if (ret)
270 return ret;
271 }
272
273 spin_lock_irqsave(&gpio_lock, flags);
274
275 value = readl_relaxed(base + GPDR_OFFSET);
276 if (__gpio_is_inverted(chip->base + offset))
277 value |= mask;
278 else
279 value &= ~mask;
280 writel_relaxed(value, base + GPDR_OFFSET);
281
282 spin_unlock_irqrestore(&gpio_lock, flags);
283 return 0;
284}
285
286static int pxa_gpio_direction_output(struct gpio_chip *chip,
287 unsigned offset, int value)
288{
289 void __iomem *base = gpio_bank_base(chip, offset);
290 uint32_t tmp, mask = GPIO_bit(offset);
291 unsigned long flags;
292 int ret;
293
294 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
295
296 if (pxa_gpio_has_pinctrl()) {
297 ret = pinctrl_gpio_direction_output(chip->base + offset);
298 if (ret)
299 return ret;
300 }
301
302 spin_lock_irqsave(&gpio_lock, flags);
303
304 tmp = readl_relaxed(base + GPDR_OFFSET);
305 if (__gpio_is_inverted(chip->base + offset))
306 tmp &= ~mask;
307 else
308 tmp |= mask;
309 writel_relaxed(tmp, base + GPDR_OFFSET);
310
311 spin_unlock_irqrestore(&gpio_lock, flags);
312 return 0;
313}
314
315static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
316{
317 void __iomem *base = gpio_bank_base(chip, offset);
318 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
319
320 return !!(gplr & GPIO_bit(offset));
321}
322
323static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
324{
325 void __iomem *base = gpio_bank_base(chip, offset);
326
327 writel_relaxed(GPIO_bit(offset),
328 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
329}
330
331#ifdef CONFIG_OF_GPIO
332static int pxa_gpio_of_xlate(struct gpio_chip *gc,
333 const struct of_phandle_args *gpiospec,
334 u32 *flags)
335{
336 if (gpiospec->args[0] > pxa_last_gpio)
337 return -EINVAL;
338
339 if (flags)
340 *flags = gpiospec->args[1];
341
342 return gpiospec->args[0];
343}
344#endif
345
346static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase)
347{
348 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
349 struct pxa_gpio_bank *bank;
350
351 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
352 GFP_KERNEL);
353 if (!pchip->banks)
354 return -ENOMEM;
355
356 pchip->chip.parent = pchip->dev;
357 pchip->chip.label = "gpio-pxa";
358 pchip->chip.direction_input = pxa_gpio_direction_input;
359 pchip->chip.direction_output = pxa_gpio_direction_output;
360 pchip->chip.get = pxa_gpio_get;
361 pchip->chip.set = pxa_gpio_set;
362 pchip->chip.to_irq = pxa_gpio_to_irq;
363 pchip->chip.ngpio = ngpio;
364 pchip->chip.request = gpiochip_generic_request;
365 pchip->chip.free = gpiochip_generic_free;
366
367#ifdef CONFIG_OF_GPIO
368 pchip->chip.of_xlate = pxa_gpio_of_xlate;
369 pchip->chip.of_gpio_n_cells = 2;
370#endif
371
372 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
373 bank = pchip->banks + i;
374 bank->regbase = regbase + BANK_OFF(i);
375 }
376
377 return gpiochip_add_data(&pchip->chip, pchip);
378}
379
380/* Update only those GRERx and GFERx edge detection register bits if those
381 * bits are set in c->irq_mask
382 */
383static inline void update_edge_detect(struct pxa_gpio_bank *c)
384{
385 uint32_t grer, gfer;
386
387 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
388 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
389 grer |= c->irq_edge_rise & c->irq_mask;
390 gfer |= c->irq_edge_fall & c->irq_mask;
391 writel_relaxed(grer, c->regbase + GRER_OFFSET);
392 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
393}
394
395static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
396{
397 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
398 unsigned int gpio = irqd_to_hwirq(d);
399 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
400 unsigned long gpdr, mask = GPIO_bit(gpio);
401
402 if (type == IRQ_TYPE_PROBE) {
403 /* Don't mess with enabled GPIOs using preconfigured edges or
404 * GPIOs set to alternate function or to output during probe
405 */
406 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
407 return 0;
408
409 if (__gpio_is_occupied(pchip, gpio))
410 return 0;
411
412 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
413 }
414
415 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
416
417 if (__gpio_is_inverted(gpio))
418 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
419 else
420 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
421
422 if (type & IRQ_TYPE_EDGE_RISING)
423 c->irq_edge_rise |= mask;
424 else
425 c->irq_edge_rise &= ~mask;
426
427 if (type & IRQ_TYPE_EDGE_FALLING)
428 c->irq_edge_fall |= mask;
429 else
430 c->irq_edge_fall &= ~mask;
431
432 update_edge_detect(c);
433
434 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
435 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
436 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
437 return 0;
438}
439
440static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
441{
442 int loop, gpio, n, handled = 0;
443 unsigned long gedr;
444 struct pxa_gpio_chip *pchip = d;
445 struct pxa_gpio_bank *c;
446
447 do {
448 loop = 0;
449 for_each_gpio_bank(gpio, c, pchip) {
450 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
451 gedr = gedr & c->irq_mask;
452 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
453
454 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
455 loop = 1;
456
457 generic_handle_domain_irq(pchip->irqdomain,
458 gpio + n);
459 }
460 }
461 handled += loop;
462 } while (loop);
463
464 return handled ? IRQ_HANDLED : IRQ_NONE;
465}
466
467static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
468{
469 struct pxa_gpio_chip *pchip = d;
470
471 if (in_irq == pchip->irq0) {
472 generic_handle_domain_irq(pchip->irqdomain, 0);
473 } else if (in_irq == pchip->irq1) {
474 generic_handle_domain_irq(pchip->irqdomain, 1);
475 } else {
476 pr_err("%s() unknown irq %d\n", __func__, in_irq);
477 return IRQ_NONE;
478 }
479 return IRQ_HANDLED;
480}
481
482static void pxa_ack_muxed_gpio(struct irq_data *d)
483{
484 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
485 unsigned int gpio = irqd_to_hwirq(d);
486 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
487
488 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
489}
490
491static void pxa_mask_muxed_gpio(struct irq_data *d)
492{
493 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
494 unsigned int gpio = irqd_to_hwirq(d);
495 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
496 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
497 uint32_t grer, gfer;
498
499 b->irq_mask &= ~GPIO_bit(gpio);
500
501 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
502 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
503 writel_relaxed(grer, base + GRER_OFFSET);
504 writel_relaxed(gfer, base + GFER_OFFSET);
505}
506
507static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
508{
509 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
510 unsigned int gpio = irqd_to_hwirq(d);
511
512 if (pchip->set_wake)
513 return pchip->set_wake(gpio, on);
514 else
515 return 0;
516}
517
518static void pxa_unmask_muxed_gpio(struct irq_data *d)
519{
520 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
521 unsigned int gpio = irqd_to_hwirq(d);
522 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
523
524 c->irq_mask |= GPIO_bit(gpio);
525 update_edge_detect(c);
526}
527
528static struct irq_chip pxa_muxed_gpio_chip = {
529 .name = "GPIO",
530 .irq_ack = pxa_ack_muxed_gpio,
531 .irq_mask = pxa_mask_muxed_gpio,
532 .irq_unmask = pxa_unmask_muxed_gpio,
533 .irq_set_type = pxa_gpio_irq_type,
534 .irq_set_wake = pxa_gpio_set_wake,
535};
536
537static int pxa_gpio_nums(struct platform_device *pdev)
538{
539 const struct platform_device_id *id = platform_get_device_id(pdev);
540 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
541 int count = 0;
542
543 switch (pxa_id->type) {
544 case PXA25X_GPIO:
545 case PXA26X_GPIO:
546 case PXA27X_GPIO:
547 case PXA3XX_GPIO:
548 case PXA93X_GPIO:
549 case MMP_GPIO:
550 case MMP2_GPIO:
551 case PXA1928_GPIO:
552 gpio_type = pxa_id->type;
553 count = pxa_id->gpio_nums - 1;
554 break;
555 default:
556 count = -EINVAL;
557 break;
558 }
559 return count;
560}
561
562static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
563 irq_hw_number_t hw)
564{
565 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
566 handle_edge_irq);
567 irq_set_chip_data(irq, d->host_data);
568 irq_set_noprobe(irq);
569 return 0;
570}
571
572static const struct irq_domain_ops pxa_irq_domain_ops = {
573 .map = pxa_irq_domain_map,
574 .xlate = irq_domain_xlate_twocell,
575};
576
577#ifdef CONFIG_OF
578static const struct of_device_id pxa_gpio_dt_ids[] = {
579 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
580 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
581 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
582 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
583 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
584 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
585 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
586 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
587 {}
588};
589
590static int pxa_gpio_probe_dt(struct platform_device *pdev,
591 struct pxa_gpio_chip *pchip)
592{
593 int nr_gpios;
594 const struct pxa_gpio_id *gpio_id;
595
596 gpio_id = of_device_get_match_data(&pdev->dev);
597 gpio_type = gpio_id->type;
598
599 nr_gpios = gpio_id->gpio_nums;
600 pxa_last_gpio = nr_gpios - 1;
601
602 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
603 if (irq_base < 0) {
604 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
605 return irq_base;
606 }
607 return irq_base;
608}
609#else
610#define pxa_gpio_probe_dt(pdev, pchip) (-1)
611#endif
612
613static int pxa_gpio_probe(struct platform_device *pdev)
614{
615 struct pxa_gpio_chip *pchip;
616 struct pxa_gpio_bank *c;
617 struct clk *clk;
618 struct pxa_gpio_platform_data *info;
619 void __iomem *gpio_reg_base;
620 int gpio, ret;
621 int irq0 = 0, irq1 = 0, irq_mux;
622
623 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
624 if (!pchip)
625 return -ENOMEM;
626 pchip->dev = &pdev->dev;
627
628 info = dev_get_platdata(&pdev->dev);
629 if (info) {
630 irq_base = info->irq_base;
631 if (irq_base <= 0)
632 return -EINVAL;
633 pxa_last_gpio = pxa_gpio_nums(pdev);
634 pchip->set_wake = info->gpio_set_wake;
635 } else {
636 irq_base = pxa_gpio_probe_dt(pdev, pchip);
637 if (irq_base < 0)
638 return -EINVAL;
639 }
640
641 if (!pxa_last_gpio)
642 return -EINVAL;
643
644 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
645 pxa_last_gpio + 1, irq_base,
646 0, &pxa_irq_domain_ops, pchip);
647 if (!pchip->irqdomain)
648 return -ENOMEM;
649
650 irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
651 irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
652 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
653 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
654 || (irq_mux <= 0))
655 return -EINVAL;
656
657 pchip->irq0 = irq0;
658 pchip->irq1 = irq1;
659
660 gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
661 if (IS_ERR(gpio_reg_base))
662 return PTR_ERR(gpio_reg_base);
663
664 clk = devm_clk_get_enabled(&pdev->dev, NULL);
665 if (IS_ERR(clk)) {
666 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
667 PTR_ERR(clk));
668 return PTR_ERR(clk);
669 }
670
671 /* Initialize GPIO chips */
672 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base);
673 if (ret)
674 return ret;
675
676 /* clear all GPIO edge detects */
677 for_each_gpio_bank(gpio, c, pchip) {
678 writel_relaxed(0, c->regbase + GFER_OFFSET);
679 writel_relaxed(0, c->regbase + GRER_OFFSET);
680 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
681 /* unmask GPIO edge detect for AP side */
682 if (gpio_is_mmp_type(gpio_type))
683 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
684 }
685
686 if (irq0 > 0) {
687 ret = devm_request_irq(&pdev->dev,
688 irq0, pxa_gpio_direct_handler, 0,
689 "gpio-0", pchip);
690 if (ret)
691 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
692 ret);
693 }
694 if (irq1 > 0) {
695 ret = devm_request_irq(&pdev->dev,
696 irq1, pxa_gpio_direct_handler, 0,
697 "gpio-1", pchip);
698 if (ret)
699 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
700 ret);
701 }
702 ret = devm_request_irq(&pdev->dev,
703 irq_mux, pxa_gpio_demux_handler, 0,
704 "gpio-mux", pchip);
705 if (ret)
706 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
707 ret);
708
709 pxa_gpio_chip = pchip;
710
711 return 0;
712}
713
714static const struct platform_device_id gpio_id_table[] = {
715 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
716 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
717 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
718 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
719 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
720 { "mmp-gpio", (unsigned long)&mmp_id },
721 { "mmp2-gpio", (unsigned long)&mmp2_id },
722 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
723 { },
724};
725
726static struct platform_driver pxa_gpio_driver = {
727 .probe = pxa_gpio_probe,
728 .driver = {
729 .name = "pxa-gpio",
730 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
731 },
732 .id_table = gpio_id_table,
733};
734
735static int __init pxa_gpio_legacy_init(void)
736{
737 if (of_have_populated_dt())
738 return 0;
739
740 return platform_driver_register(&pxa_gpio_driver);
741}
742postcore_initcall(pxa_gpio_legacy_init);
743
744static int __init pxa_gpio_dt_init(void)
745{
746 if (of_have_populated_dt())
747 return platform_driver_register(&pxa_gpio_driver);
748
749 return 0;
750}
751device_initcall(pxa_gpio_dt_init);
752
753#ifdef CONFIG_PM
754static int pxa_gpio_suspend(void)
755{
756 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
757 struct pxa_gpio_bank *c;
758 int gpio;
759
760 if (!pchip)
761 return 0;
762
763 for_each_gpio_bank(gpio, c, pchip) {
764 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
765 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
766 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
767 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
768
769 /* Clear GPIO transition detect bits */
770 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
771 }
772 return 0;
773}
774
775static void pxa_gpio_resume(void)
776{
777 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
778 struct pxa_gpio_bank *c;
779 int gpio;
780
781 if (!pchip)
782 return;
783
784 for_each_gpio_bank(gpio, c, pchip) {
785 /* restore level with set/clear */
786 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
787 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
788
789 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
790 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
791 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
792 }
793}
794#else
795#define pxa_gpio_suspend NULL
796#define pxa_gpio_resume NULL
797#endif
798
799static struct syscore_ops pxa_gpio_syscore_ops = {
800 .suspend = pxa_gpio_suspend,
801 .resume = pxa_gpio_resume,
802};
803
804static int __init pxa_gpio_sysinit(void)
805{
806 register_syscore_ops(&pxa_gpio_syscore_ops);
807 return 0;
808}
809postcore_initcall(pxa_gpio_sysinit);
1/*
2 * linux/arch/arm/plat-pxa/gpio.c
3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/module.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/gpio-pxa.h>
19#include <linux/init.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/irqchip/chained_irq.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/syscore_ops.h>
28#include <linux/slab.h>
29
30#include <mach/irqs.h>
31
32/*
33 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
34 * one set of registers. The register offsets are organized below:
35 *
36 * GPLR GPDR GPSR GPCR GRER GFER GEDR
37 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
38 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
39 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
40 *
41 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
42 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
43 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
44 *
45 * NOTE:
46 * BANK 3 is only available on PXA27x and later processors.
47 * BANK 4 and 5 are only available on PXA935
48 */
49
50#define GPLR_OFFSET 0x00
51#define GPDR_OFFSET 0x0C
52#define GPSR_OFFSET 0x18
53#define GPCR_OFFSET 0x24
54#define GRER_OFFSET 0x30
55#define GFER_OFFSET 0x3C
56#define GEDR_OFFSET 0x48
57#define GAFR_OFFSET 0x54
58#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
59
60#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
61
62int pxa_last_gpio;
63static int irq_base;
64
65#ifdef CONFIG_OF
66static struct irq_domain *domain;
67static struct device_node *pxa_gpio_of_node;
68#endif
69
70struct pxa_gpio_chip {
71 struct gpio_chip chip;
72 void __iomem *regbase;
73 char label[10];
74
75 unsigned long irq_mask;
76 unsigned long irq_edge_rise;
77 unsigned long irq_edge_fall;
78 int (*set_wake)(unsigned int gpio, unsigned int on);
79
80#ifdef CONFIG_PM
81 unsigned long saved_gplr;
82 unsigned long saved_gpdr;
83 unsigned long saved_grer;
84 unsigned long saved_gfer;
85#endif
86};
87
88enum pxa_gpio_type {
89 PXA25X_GPIO = 0,
90 PXA26X_GPIO,
91 PXA27X_GPIO,
92 PXA3XX_GPIO,
93 PXA93X_GPIO,
94 MMP_GPIO = 0x10,
95 MMP2_GPIO,
96};
97
98struct pxa_gpio_id {
99 enum pxa_gpio_type type;
100 int gpio_nums;
101};
102
103static DEFINE_SPINLOCK(gpio_lock);
104static struct pxa_gpio_chip *pxa_gpio_chips;
105static enum pxa_gpio_type gpio_type;
106static void __iomem *gpio_reg_base;
107
108static struct pxa_gpio_id pxa25x_id = {
109 .type = PXA25X_GPIO,
110 .gpio_nums = 85,
111};
112
113static struct pxa_gpio_id pxa26x_id = {
114 .type = PXA26X_GPIO,
115 .gpio_nums = 90,
116};
117
118static struct pxa_gpio_id pxa27x_id = {
119 .type = PXA27X_GPIO,
120 .gpio_nums = 121,
121};
122
123static struct pxa_gpio_id pxa3xx_id = {
124 .type = PXA3XX_GPIO,
125 .gpio_nums = 128,
126};
127
128static struct pxa_gpio_id pxa93x_id = {
129 .type = PXA93X_GPIO,
130 .gpio_nums = 192,
131};
132
133static struct pxa_gpio_id mmp_id = {
134 .type = MMP_GPIO,
135 .gpio_nums = 128,
136};
137
138static struct pxa_gpio_id mmp2_id = {
139 .type = MMP2_GPIO,
140 .gpio_nums = 192,
141};
142
143#define for_each_gpio_chip(i, c) \
144 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
145
146static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
147{
148 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
149}
150
151static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
152{
153 return &pxa_gpio_chips[gpio_to_bank(gpio)];
154}
155
156static inline int gpio_is_pxa_type(int type)
157{
158 return (type & MMP_GPIO) == 0;
159}
160
161static inline int gpio_is_mmp_type(int type)
162{
163 return (type & MMP_GPIO) != 0;
164}
165
166/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
167 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
168 */
169static inline int __gpio_is_inverted(int gpio)
170{
171 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
172 return 1;
173 return 0;
174}
175
176/*
177 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
178 * function of a GPIO, and GPDRx cannot be altered once configured. It
179 * is attributed as "occupied" here (I know this terminology isn't
180 * accurate, you are welcome to propose a better one :-)
181 */
182static inline int __gpio_is_occupied(unsigned gpio)
183{
184 struct pxa_gpio_chip *pxachip;
185 void __iomem *base;
186 unsigned long gafr = 0, gpdr = 0;
187 int ret, af = 0, dir = 0;
188
189 pxachip = gpio_to_pxachip(gpio);
190 base = gpio_chip_base(&pxachip->chip);
191 gpdr = readl_relaxed(base + GPDR_OFFSET);
192
193 switch (gpio_type) {
194 case PXA25X_GPIO:
195 case PXA26X_GPIO:
196 case PXA27X_GPIO:
197 gafr = readl_relaxed(base + GAFR_OFFSET);
198 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
199 dir = gpdr & GPIO_bit(gpio);
200
201 if (__gpio_is_inverted(gpio))
202 ret = (af != 1) || (dir == 0);
203 else
204 ret = (af != 0) || (dir != 0);
205 break;
206 default:
207 ret = gpdr & GPIO_bit(gpio);
208 break;
209 }
210 return ret;
211}
212
213static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
214{
215 return chip->base + offset + irq_base;
216}
217
218int pxa_irq_to_gpio(int irq)
219{
220 return irq - irq_base;
221}
222
223static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
224{
225 void __iomem *base = gpio_chip_base(chip);
226 uint32_t value, mask = 1 << offset;
227 unsigned long flags;
228
229 spin_lock_irqsave(&gpio_lock, flags);
230
231 value = readl_relaxed(base + GPDR_OFFSET);
232 if (__gpio_is_inverted(chip->base + offset))
233 value |= mask;
234 else
235 value &= ~mask;
236 writel_relaxed(value, base + GPDR_OFFSET);
237
238 spin_unlock_irqrestore(&gpio_lock, flags);
239 return 0;
240}
241
242static int pxa_gpio_direction_output(struct gpio_chip *chip,
243 unsigned offset, int value)
244{
245 void __iomem *base = gpio_chip_base(chip);
246 uint32_t tmp, mask = 1 << offset;
247 unsigned long flags;
248
249 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
250
251 spin_lock_irqsave(&gpio_lock, flags);
252
253 tmp = readl_relaxed(base + GPDR_OFFSET);
254 if (__gpio_is_inverted(chip->base + offset))
255 tmp &= ~mask;
256 else
257 tmp |= mask;
258 writel_relaxed(tmp, base + GPDR_OFFSET);
259
260 spin_unlock_irqrestore(&gpio_lock, flags);
261 return 0;
262}
263
264static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
265{
266 u32 gplr = readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET);
267 return !!(gplr & (1 << offset));
268}
269
270static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
271{
272 writel_relaxed(1 << offset, gpio_chip_base(chip) +
273 (value ? GPSR_OFFSET : GPCR_OFFSET));
274}
275
276#ifdef CONFIG_OF_GPIO
277static int pxa_gpio_of_xlate(struct gpio_chip *gc,
278 const struct of_phandle_args *gpiospec,
279 u32 *flags)
280{
281 if (gpiospec->args[0] > pxa_last_gpio)
282 return -EINVAL;
283
284 if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip)
285 return -EINVAL;
286
287 if (flags)
288 *flags = gpiospec->args[1];
289
290 return gpiospec->args[0] % 32;
291}
292#endif
293
294static int pxa_init_gpio_chip(int gpio_end,
295 int (*set_wake)(unsigned int, unsigned int))
296{
297 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
298 struct pxa_gpio_chip *chips;
299
300 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
301 if (chips == NULL) {
302 pr_err("%s: failed to allocate GPIO chips\n", __func__);
303 return -ENOMEM;
304 }
305
306 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
307 struct gpio_chip *c = &chips[i].chip;
308
309 sprintf(chips[i].label, "gpio-%d", i);
310 chips[i].regbase = gpio_reg_base + BANK_OFF(i);
311 chips[i].set_wake = set_wake;
312
313 c->base = gpio;
314 c->label = chips[i].label;
315
316 c->direction_input = pxa_gpio_direction_input;
317 c->direction_output = pxa_gpio_direction_output;
318 c->get = pxa_gpio_get;
319 c->set = pxa_gpio_set;
320 c->to_irq = pxa_gpio_to_irq;
321#ifdef CONFIG_OF_GPIO
322 c->of_node = pxa_gpio_of_node;
323 c->of_xlate = pxa_gpio_of_xlate;
324 c->of_gpio_n_cells = 2;
325#endif
326
327 /* number of GPIOs on last bank may be less than 32 */
328 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
329 gpiochip_add(c);
330 }
331 pxa_gpio_chips = chips;
332 return 0;
333}
334
335/* Update only those GRERx and GFERx edge detection register bits if those
336 * bits are set in c->irq_mask
337 */
338static inline void update_edge_detect(struct pxa_gpio_chip *c)
339{
340 uint32_t grer, gfer;
341
342 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
343 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
344 grer |= c->irq_edge_rise & c->irq_mask;
345 gfer |= c->irq_edge_fall & c->irq_mask;
346 writel_relaxed(grer, c->regbase + GRER_OFFSET);
347 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
348}
349
350static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
351{
352 struct pxa_gpio_chip *c;
353 int gpio = pxa_irq_to_gpio(d->irq);
354 unsigned long gpdr, mask = GPIO_bit(gpio);
355
356 c = gpio_to_pxachip(gpio);
357
358 if (type == IRQ_TYPE_PROBE) {
359 /* Don't mess with enabled GPIOs using preconfigured edges or
360 * GPIOs set to alternate function or to output during probe
361 */
362 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
363 return 0;
364
365 if (__gpio_is_occupied(gpio))
366 return 0;
367
368 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
369 }
370
371 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
372
373 if (__gpio_is_inverted(gpio))
374 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
375 else
376 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
377
378 if (type & IRQ_TYPE_EDGE_RISING)
379 c->irq_edge_rise |= mask;
380 else
381 c->irq_edge_rise &= ~mask;
382
383 if (type & IRQ_TYPE_EDGE_FALLING)
384 c->irq_edge_fall |= mask;
385 else
386 c->irq_edge_fall &= ~mask;
387
388 update_edge_detect(c);
389
390 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
391 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
392 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
393 return 0;
394}
395
396static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
397{
398 struct pxa_gpio_chip *c;
399 int loop, gpio, gpio_base, n;
400 unsigned long gedr;
401 struct irq_chip *chip = irq_desc_get_chip(desc);
402
403 chained_irq_enter(chip, desc);
404
405 do {
406 loop = 0;
407 for_each_gpio_chip(gpio, c) {
408 gpio_base = c->chip.base;
409
410 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
411 gedr = gedr & c->irq_mask;
412 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
413
414 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
415 loop = 1;
416
417 generic_handle_irq(gpio_to_irq(gpio_base + n));
418 }
419 }
420 } while (loop);
421
422 chained_irq_exit(chip, desc);
423}
424
425static void pxa_ack_muxed_gpio(struct irq_data *d)
426{
427 int gpio = pxa_irq_to_gpio(d->irq);
428 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
429
430 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
431}
432
433static void pxa_mask_muxed_gpio(struct irq_data *d)
434{
435 int gpio = pxa_irq_to_gpio(d->irq);
436 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
437 uint32_t grer, gfer;
438
439 c->irq_mask &= ~GPIO_bit(gpio);
440
441 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
442 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
443 writel_relaxed(grer, c->regbase + GRER_OFFSET);
444 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
445}
446
447static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
448{
449 int gpio = pxa_irq_to_gpio(d->irq);
450 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
451
452 if (c->set_wake)
453 return c->set_wake(gpio, on);
454 else
455 return 0;
456}
457
458static void pxa_unmask_muxed_gpio(struct irq_data *d)
459{
460 int gpio = pxa_irq_to_gpio(d->irq);
461 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
462
463 c->irq_mask |= GPIO_bit(gpio);
464 update_edge_detect(c);
465}
466
467static struct irq_chip pxa_muxed_gpio_chip = {
468 .name = "GPIO",
469 .irq_ack = pxa_ack_muxed_gpio,
470 .irq_mask = pxa_mask_muxed_gpio,
471 .irq_unmask = pxa_unmask_muxed_gpio,
472 .irq_set_type = pxa_gpio_irq_type,
473 .irq_set_wake = pxa_gpio_set_wake,
474};
475
476static int pxa_gpio_nums(struct platform_device *pdev)
477{
478 const struct platform_device_id *id = platform_get_device_id(pdev);
479 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
480 int count = 0;
481
482 switch (pxa_id->type) {
483 case PXA25X_GPIO:
484 case PXA26X_GPIO:
485 case PXA27X_GPIO:
486 case PXA3XX_GPIO:
487 case PXA93X_GPIO:
488 case MMP_GPIO:
489 case MMP2_GPIO:
490 gpio_type = pxa_id->type;
491 count = pxa_id->gpio_nums - 1;
492 break;
493 default:
494 count = -EINVAL;
495 break;
496 }
497 return count;
498}
499
500#ifdef CONFIG_OF
501static struct of_device_id pxa_gpio_dt_ids[] = {
502 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
503 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
504 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
505 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
506 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
507 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
508 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
509 {}
510};
511
512static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
513 irq_hw_number_t hw)
514{
515 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
516 handle_edge_irq);
517 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
518 return 0;
519}
520
521const struct irq_domain_ops pxa_irq_domain_ops = {
522 .map = pxa_irq_domain_map,
523 .xlate = irq_domain_xlate_twocell,
524};
525
526static int pxa_gpio_probe_dt(struct platform_device *pdev)
527{
528 int ret = 0, nr_gpios;
529 struct device_node *np = pdev->dev.of_node;
530 const struct of_device_id *of_id =
531 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
532 const struct pxa_gpio_id *gpio_id;
533
534 if (!of_id || !of_id->data) {
535 dev_err(&pdev->dev, "Failed to find gpio controller\n");
536 return -EFAULT;
537 }
538 gpio_id = of_id->data;
539 gpio_type = gpio_id->type;
540
541 nr_gpios = gpio_id->gpio_nums;
542 pxa_last_gpio = nr_gpios - 1;
543
544 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
545 if (irq_base < 0) {
546 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
547 ret = irq_base;
548 goto err;
549 }
550 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
551 &pxa_irq_domain_ops, NULL);
552 pxa_gpio_of_node = np;
553 return 0;
554err:
555 iounmap(gpio_reg_base);
556 return ret;
557}
558#else
559#define pxa_gpio_probe_dt(pdev) (-1)
560#endif
561
562static int pxa_gpio_probe(struct platform_device *pdev)
563{
564 struct pxa_gpio_chip *c;
565 struct resource *res;
566 struct clk *clk;
567 struct pxa_gpio_platform_data *info;
568 int gpio, irq, ret, use_of = 0;
569 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
570
571 info = dev_get_platdata(&pdev->dev);
572 if (info) {
573 irq_base = info->irq_base;
574 if (irq_base <= 0)
575 return -EINVAL;
576 pxa_last_gpio = pxa_gpio_nums(pdev);
577 } else {
578 irq_base = 0;
579 use_of = 1;
580 ret = pxa_gpio_probe_dt(pdev);
581 if (ret < 0)
582 return -EINVAL;
583 }
584
585 if (!pxa_last_gpio)
586 return -EINVAL;
587
588 irq0 = platform_get_irq_byname(pdev, "gpio0");
589 irq1 = platform_get_irq_byname(pdev, "gpio1");
590 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
591 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
592 || (irq_mux <= 0))
593 return -EINVAL;
594 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
595 if (!res)
596 return -EINVAL;
597 gpio_reg_base = ioremap(res->start, resource_size(res));
598 if (!gpio_reg_base)
599 return -EINVAL;
600
601 if (irq0 > 0)
602 gpio_offset = 2;
603
604 clk = clk_get(&pdev->dev, NULL);
605 if (IS_ERR(clk)) {
606 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
607 PTR_ERR(clk));
608 iounmap(gpio_reg_base);
609 return PTR_ERR(clk);
610 }
611 ret = clk_prepare_enable(clk);
612 if (ret) {
613 clk_put(clk);
614 iounmap(gpio_reg_base);
615 return ret;
616 }
617
618 /* Initialize GPIO chips */
619 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
620
621 /* clear all GPIO edge detects */
622 for_each_gpio_chip(gpio, c) {
623 writel_relaxed(0, c->regbase + GFER_OFFSET);
624 writel_relaxed(0, c->regbase + GRER_OFFSET);
625 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
626 /* unmask GPIO edge detect for AP side */
627 if (gpio_is_mmp_type(gpio_type))
628 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
629 }
630
631 if (!use_of) {
632#ifdef CONFIG_ARCH_PXA
633 irq = gpio_to_irq(0);
634 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
635 handle_edge_irq);
636 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
637 irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
638
639 irq = gpio_to_irq(1);
640 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
641 handle_edge_irq);
642 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
643 irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
644#endif
645
646 for (irq = gpio_to_irq(gpio_offset);
647 irq <= gpio_to_irq(pxa_last_gpio); irq++) {
648 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
649 handle_edge_irq);
650 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
651 }
652 }
653
654 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
655 return 0;
656}
657
658static const struct platform_device_id gpio_id_table[] = {
659 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
660 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
661 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
662 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
663 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
664 { "mmp-gpio", (unsigned long)&mmp_id },
665 { "mmp2-gpio", (unsigned long)&mmp2_id },
666 { },
667};
668
669static struct platform_driver pxa_gpio_driver = {
670 .probe = pxa_gpio_probe,
671 .driver = {
672 .name = "pxa-gpio",
673 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
674 },
675 .id_table = gpio_id_table,
676};
677
678static int __init pxa_gpio_init(void)
679{
680 return platform_driver_register(&pxa_gpio_driver);
681}
682postcore_initcall(pxa_gpio_init);
683
684#ifdef CONFIG_PM
685static int pxa_gpio_suspend(void)
686{
687 struct pxa_gpio_chip *c;
688 int gpio;
689
690 for_each_gpio_chip(gpio, c) {
691 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
692 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
693 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
694 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
695
696 /* Clear GPIO transition detect bits */
697 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
698 }
699 return 0;
700}
701
702static void pxa_gpio_resume(void)
703{
704 struct pxa_gpio_chip *c;
705 int gpio;
706
707 for_each_gpio_chip(gpio, c) {
708 /* restore level with set/clear */
709 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
710 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
711
712 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
713 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
714 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
715 }
716}
717#else
718#define pxa_gpio_suspend NULL
719#define pxa_gpio_resume NULL
720#endif
721
722struct syscore_ops pxa_gpio_syscore_ops = {
723 .suspend = pxa_gpio_suspend,
724 .resume = pxa_gpio_resume,
725};
726
727static int __init pxa_gpio_sysinit(void)
728{
729 register_syscore_ops(&pxa_gpio_syscore_ops);
730 return 0;
731}
732postcore_initcall(pxa_gpio_sysinit);