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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Suspend support specific for i386/x86-64.
4 *
5 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
6 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
7 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
8 */
9
10#include <linux/suspend.h>
11#include <linux/export.h>
12#include <linux/smp.h>
13#include <linux/perf_event.h>
14#include <linux/tboot.h>
15#include <linux/dmi.h>
16#include <linux/pgtable.h>
17
18#include <asm/proto.h>
19#include <asm/mtrr.h>
20#include <asm/page.h>
21#include <asm/mce.h>
22#include <asm/suspend.h>
23#include <asm/fpu/api.h>
24#include <asm/debugreg.h>
25#include <asm/cpu.h>
26#include <asm/cacheinfo.h>
27#include <asm/mmu_context.h>
28#include <asm/cpu_device_id.h>
29#include <asm/microcode.h>
30
31#ifdef CONFIG_X86_32
32__visible unsigned long saved_context_ebx;
33__visible unsigned long saved_context_esp, saved_context_ebp;
34__visible unsigned long saved_context_esi, saved_context_edi;
35__visible unsigned long saved_context_eflags;
36#endif
37struct saved_context saved_context;
38
39static void msr_save_context(struct saved_context *ctxt)
40{
41 struct saved_msr *msr = ctxt->saved_msrs.array;
42 struct saved_msr *end = msr + ctxt->saved_msrs.num;
43
44 while (msr < end) {
45 if (msr->valid)
46 rdmsrl(msr->info.msr_no, msr->info.reg.q);
47 msr++;
48 }
49}
50
51static void msr_restore_context(struct saved_context *ctxt)
52{
53 struct saved_msr *msr = ctxt->saved_msrs.array;
54 struct saved_msr *end = msr + ctxt->saved_msrs.num;
55
56 while (msr < end) {
57 if (msr->valid)
58 wrmsrl(msr->info.msr_no, msr->info.reg.q);
59 msr++;
60 }
61}
62
63/**
64 * __save_processor_state() - Save CPU registers before creating a
65 * hibernation image and before restoring
66 * the memory state from it
67 * @ctxt: Structure to store the registers contents in.
68 *
69 * NOTE: If there is a CPU register the modification of which by the
70 * boot kernel (ie. the kernel used for loading the hibernation image)
71 * might affect the operations of the restored target kernel (ie. the one
72 * saved in the hibernation image), then its contents must be saved by this
73 * function. In other words, if kernel A is hibernated and different
74 * kernel B is used for loading the hibernation image into memory, the
75 * kernel A's __save_processor_state() function must save all registers
76 * needed by kernel A, so that it can operate correctly after the resume
77 * regardless of what kernel B does in the meantime.
78 */
79static void __save_processor_state(struct saved_context *ctxt)
80{
81#ifdef CONFIG_X86_32
82 mtrr_save_fixed_ranges(NULL);
83#endif
84 kernel_fpu_begin();
85
86 /*
87 * descriptor tables
88 */
89 store_idt(&ctxt->idt);
90
91 /*
92 * We save it here, but restore it only in the hibernate case.
93 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
94 * mode in "secondary_startup_64". In 32-bit mode it is done via
95 * 'pmode_gdt' in wakeup_start.
96 */
97 ctxt->gdt_desc.size = GDT_SIZE - 1;
98 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
99
100 store_tr(ctxt->tr);
101
102 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
103 /*
104 * segment registers
105 */
106 savesegment(gs, ctxt->gs);
107#ifdef CONFIG_X86_64
108 savesegment(fs, ctxt->fs);
109 savesegment(ds, ctxt->ds);
110 savesegment(es, ctxt->es);
111
112 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
113 rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
114 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
115 mtrr_save_fixed_ranges(NULL);
116
117 rdmsrl(MSR_EFER, ctxt->efer);
118#endif
119
120 /*
121 * control registers
122 */
123 ctxt->cr0 = read_cr0();
124 ctxt->cr2 = read_cr2();
125 ctxt->cr3 = __read_cr3();
126 ctxt->cr4 = __read_cr4();
127 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
128 &ctxt->misc_enable);
129 msr_save_context(ctxt);
130}
131
132/* Needed by apm.c */
133void save_processor_state(void)
134{
135 __save_processor_state(&saved_context);
136 x86_platform.save_sched_clock_state();
137}
138#ifdef CONFIG_X86_32
139EXPORT_SYMBOL(save_processor_state);
140#endif
141
142static void do_fpu_end(void)
143{
144 /*
145 * Restore FPU regs if necessary.
146 */
147 kernel_fpu_end();
148}
149
150static void fix_processor_context(void)
151{
152 int cpu = smp_processor_id();
153#ifdef CONFIG_X86_64
154 struct desc_struct *desc = get_cpu_gdt_rw(cpu);
155 tss_desc tss;
156#endif
157
158 /*
159 * We need to reload TR, which requires that we change the
160 * GDT entry to indicate "available" first.
161 *
162 * XXX: This could probably all be replaced by a call to
163 * force_reload_TR().
164 */
165 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
166
167#ifdef CONFIG_X86_64
168 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
169 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
170 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
171
172 syscall_init(); /* This sets MSR_*STAR and related */
173#else
174 if (boot_cpu_has(X86_FEATURE_SEP))
175 enable_sep_cpu();
176#endif
177 load_TR_desc(); /* This does ltr */
178 load_mm_ldt(current->active_mm); /* This does lldt */
179 initialize_tlbstate_and_flush();
180
181 fpu__resume_cpu();
182
183 /* The processor is back on the direct GDT, load back the fixmap */
184 load_fixmap_gdt(cpu);
185}
186
187/**
188 * __restore_processor_state() - Restore the contents of CPU registers saved
189 * by __save_processor_state()
190 * @ctxt: Structure to load the registers contents from.
191 *
192 * The asm code that gets us here will have restored a usable GDT, although
193 * it will be pointing to the wrong alias.
194 */
195static void notrace __restore_processor_state(struct saved_context *ctxt)
196{
197 struct cpuinfo_x86 *c;
198
199 if (ctxt->misc_enable_saved)
200 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
201 /*
202 * control registers
203 */
204 /* cr4 was introduced in the Pentium CPU */
205#ifdef CONFIG_X86_32
206 if (ctxt->cr4)
207 __write_cr4(ctxt->cr4);
208#else
209/* CONFIG X86_64 */
210 wrmsrl(MSR_EFER, ctxt->efer);
211 __write_cr4(ctxt->cr4);
212#endif
213 write_cr3(ctxt->cr3);
214 write_cr2(ctxt->cr2);
215 write_cr0(ctxt->cr0);
216
217 /* Restore the IDT. */
218 load_idt(&ctxt->idt);
219
220 /*
221 * Just in case the asm code got us here with the SS, DS, or ES
222 * out of sync with the GDT, update them.
223 */
224 loadsegment(ss, __KERNEL_DS);
225 loadsegment(ds, __USER_DS);
226 loadsegment(es, __USER_DS);
227
228 /*
229 * Restore percpu access. Percpu access can happen in exception
230 * handlers or in complicated helpers like load_gs_index().
231 */
232#ifdef CONFIG_X86_64
233 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
234#else
235 loadsegment(fs, __KERNEL_PERCPU);
236#endif
237
238 /* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */
239 fix_processor_context();
240
241 /*
242 * Now that we have descriptor tables fully restored and working
243 * exception handling, restore the usermode segments.
244 */
245#ifdef CONFIG_X86_64
246 loadsegment(ds, ctxt->es);
247 loadsegment(es, ctxt->es);
248 loadsegment(fs, ctxt->fs);
249 load_gs_index(ctxt->gs);
250
251 /*
252 * Restore FSBASE and GSBASE after restoring the selectors, since
253 * restoring the selectors clobbers the bases. Keep in mind
254 * that MSR_KERNEL_GS_BASE is horribly misnamed.
255 */
256 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
257 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
258#else
259 loadsegment(gs, ctxt->gs);
260#endif
261
262 do_fpu_end();
263 tsc_verify_tsc_adjust(true);
264 x86_platform.restore_sched_clock_state();
265 cache_bp_restore();
266 perf_restore_debug_store();
267
268 c = &cpu_data(smp_processor_id());
269 if (cpu_has(c, X86_FEATURE_MSR_IA32_FEAT_CTL))
270 init_ia32_feat_ctl(c);
271
272 microcode_bsp_resume();
273
274 /*
275 * This needs to happen after the microcode has been updated upon resume
276 * because some of the MSRs are "emulated" in microcode.
277 */
278 msr_restore_context(ctxt);
279}
280
281/* Needed by apm.c */
282void notrace restore_processor_state(void)
283{
284 __restore_processor_state(&saved_context);
285}
286#ifdef CONFIG_X86_32
287EXPORT_SYMBOL(restore_processor_state);
288#endif
289
290#if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
291static void resume_play_dead(void)
292{
293 play_dead_common();
294 tboot_shutdown(TB_SHUTDOWN_WFS);
295 hlt_play_dead();
296}
297
298int hibernate_resume_nonboot_cpu_disable(void)
299{
300 void (*play_dead)(void) = smp_ops.play_dead;
301 int ret;
302
303 /*
304 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
305 * during hibernate image restoration, because it is likely that the
306 * monitored address will be actually written to at that time and then
307 * the "dead" CPU will attempt to execute instructions again, but the
308 * address in its instruction pointer may not be possible to resolve
309 * any more at that point (the page tables used by it previously may
310 * have been overwritten by hibernate image data).
311 *
312 * First, make sure that we wake up all the potentially disabled SMT
313 * threads which have been initially brought up and then put into
314 * mwait/cpuidle sleep.
315 * Those will be put to proper (not interfering with hibernation
316 * resume) sleep afterwards, and the resumed kernel will decide itself
317 * what to do with them.
318 */
319 ret = cpuhp_smt_enable();
320 if (ret)
321 return ret;
322 smp_ops.play_dead = resume_play_dead;
323 ret = freeze_secondary_cpus(0);
324 smp_ops.play_dead = play_dead;
325 return ret;
326}
327#endif
328
329/*
330 * When bsp_check() is called in hibernate and suspend, cpu hotplug
331 * is disabled already. So it's unnecessary to handle race condition between
332 * cpumask query and cpu hotplug.
333 */
334static int bsp_check(void)
335{
336 if (cpumask_first(cpu_online_mask) != 0) {
337 pr_warn("CPU0 is offline.\n");
338 return -ENODEV;
339 }
340
341 return 0;
342}
343
344static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
345 void *ptr)
346{
347 int ret = 0;
348
349 switch (action) {
350 case PM_SUSPEND_PREPARE:
351 case PM_HIBERNATION_PREPARE:
352 ret = bsp_check();
353 break;
354#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
355 case PM_RESTORE_PREPARE:
356 /*
357 * When system resumes from hibernation, online CPU0 because
358 * 1. it's required for resume and
359 * 2. the CPU was online before hibernation
360 */
361 if (!cpu_online(0))
362 _debug_hotplug_cpu(0, 1);
363 break;
364 case PM_POST_RESTORE:
365 /*
366 * When a resume really happens, this code won't be called.
367 *
368 * This code is called only when user space hibernation software
369 * prepares for snapshot device during boot time. So we just
370 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
371 * preparing the snapshot device.
372 *
373 * This works for normal boot case in our CPU0 hotplug debug
374 * mode, i.e. CPU0 is offline and user mode hibernation
375 * software initializes during boot time.
376 *
377 * If CPU0 is online and user application accesses snapshot
378 * device after boot time, this will offline CPU0 and user may
379 * see different CPU0 state before and after accessing
380 * the snapshot device. But hopefully this is not a case when
381 * user debugging CPU0 hotplug. Even if users hit this case,
382 * they can easily online CPU0 back.
383 *
384 * To simplify this debug code, we only consider normal boot
385 * case. Otherwise we need to remember CPU0's state and restore
386 * to that state and resolve racy conditions etc.
387 */
388 _debug_hotplug_cpu(0, 0);
389 break;
390#endif
391 default:
392 break;
393 }
394 return notifier_from_errno(ret);
395}
396
397static int __init bsp_pm_check_init(void)
398{
399 /*
400 * Set this bsp_pm_callback as lower priority than
401 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
402 * earlier to disable cpu hotplug before bsp online check.
403 */
404 pm_notifier(bsp_pm_callback, -INT_MAX);
405 return 0;
406}
407
408core_initcall(bsp_pm_check_init);
409
410static int msr_build_context(const u32 *msr_id, const int num)
411{
412 struct saved_msrs *saved_msrs = &saved_context.saved_msrs;
413 struct saved_msr *msr_array;
414 int total_num;
415 int i, j;
416
417 total_num = saved_msrs->num + num;
418
419 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
420 if (!msr_array) {
421 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
422 return -ENOMEM;
423 }
424
425 if (saved_msrs->array) {
426 /*
427 * Multiple callbacks can invoke this function, so copy any
428 * MSR save requests from previous invocations.
429 */
430 memcpy(msr_array, saved_msrs->array,
431 sizeof(struct saved_msr) * saved_msrs->num);
432
433 kfree(saved_msrs->array);
434 }
435
436 for (i = saved_msrs->num, j = 0; i < total_num; i++, j++) {
437 u64 dummy;
438
439 msr_array[i].info.msr_no = msr_id[j];
440 msr_array[i].valid = !rdmsrl_safe(msr_id[j], &dummy);
441 msr_array[i].info.reg.q = 0;
442 }
443 saved_msrs->num = total_num;
444 saved_msrs->array = msr_array;
445
446 return 0;
447}
448
449/*
450 * The following sections are a quirk framework for problematic BIOSen:
451 * Sometimes MSRs are modified by the BIOSen after suspended to
452 * RAM, this might cause unexpected behavior after wakeup.
453 * Thus we save/restore these specified MSRs across suspend/resume
454 * in order to work around it.
455 *
456 * For any further problematic BIOSen/platforms,
457 * please add your own function similar to msr_initialize_bdw.
458 */
459static int msr_initialize_bdw(const struct dmi_system_id *d)
460{
461 /* Add any extra MSR ids into this array. */
462 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
463
464 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
465 return msr_build_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
466}
467
468static const struct dmi_system_id msr_save_dmi_table[] = {
469 {
470 .callback = msr_initialize_bdw,
471 .ident = "BROADWELL BDX_EP",
472 .matches = {
473 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
474 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
475 },
476 },
477 {}
478};
479
480static int msr_save_cpuid_features(const struct x86_cpu_id *c)
481{
482 u32 cpuid_msr_id[] = {
483 MSR_AMD64_CPUID_FN_1,
484 };
485
486 pr_info("x86/pm: family %#hx cpu detected, MSR saving is needed during suspending.\n",
487 c->family);
488
489 return msr_build_context(cpuid_msr_id, ARRAY_SIZE(cpuid_msr_id));
490}
491
492static const struct x86_cpu_id msr_save_cpu_table[] = {
493 X86_MATCH_VENDOR_FAM(AMD, 0x15, &msr_save_cpuid_features),
494 X86_MATCH_VENDOR_FAM(AMD, 0x16, &msr_save_cpuid_features),
495 {}
496};
497
498typedef int (*pm_cpu_match_t)(const struct x86_cpu_id *);
499static int pm_cpu_check(const struct x86_cpu_id *c)
500{
501 const struct x86_cpu_id *m;
502 int ret = 0;
503
504 m = x86_match_cpu(msr_save_cpu_table);
505 if (m) {
506 pm_cpu_match_t fn;
507
508 fn = (pm_cpu_match_t)m->driver_data;
509 ret = fn(m);
510 }
511
512 return ret;
513}
514
515static void pm_save_spec_msr(void)
516{
517 struct msr_enumeration {
518 u32 msr_no;
519 u32 feature;
520 } msr_enum[] = {
521 { MSR_IA32_SPEC_CTRL, X86_FEATURE_MSR_SPEC_CTRL },
522 { MSR_IA32_TSX_CTRL, X86_FEATURE_MSR_TSX_CTRL },
523 { MSR_TSX_FORCE_ABORT, X86_FEATURE_TSX_FORCE_ABORT },
524 { MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL },
525 { MSR_AMD64_LS_CFG, X86_FEATURE_LS_CFG_SSBD },
526 { MSR_AMD64_DE_CFG, X86_FEATURE_LFENCE_RDTSC },
527 };
528 int i;
529
530 for (i = 0; i < ARRAY_SIZE(msr_enum); i++) {
531 if (boot_cpu_has(msr_enum[i].feature))
532 msr_build_context(&msr_enum[i].msr_no, 1);
533 }
534}
535
536static int pm_check_save_msr(void)
537{
538 dmi_check_system(msr_save_dmi_table);
539 pm_cpu_check(msr_save_cpu_table);
540 pm_save_spec_msr();
541
542 return 0;
543}
544
545device_initcall(pm_check_save_msr);
1/*
2 * Suspend support specific for i386/x86-64.
3 *
4 * Distribute under GPLv2
5 *
6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
9 */
10
11#include <linux/suspend.h>
12#include <linux/export.h>
13#include <linux/smp.h>
14#include <linux/perf_event.h>
15
16#include <asm/pgtable.h>
17#include <asm/proto.h>
18#include <asm/mtrr.h>
19#include <asm/page.h>
20#include <asm/mce.h>
21#include <asm/xcr.h>
22#include <asm/suspend.h>
23#include <asm/debugreg.h>
24#include <asm/fpu-internal.h> /* pcntxt_mask */
25#include <asm/cpu.h>
26
27#ifdef CONFIG_X86_32
28__visible unsigned long saved_context_ebx;
29__visible unsigned long saved_context_esp, saved_context_ebp;
30__visible unsigned long saved_context_esi, saved_context_edi;
31__visible unsigned long saved_context_eflags;
32#endif
33struct saved_context saved_context;
34
35/**
36 * __save_processor_state - save CPU registers before creating a
37 * hibernation image and before restoring the memory state from it
38 * @ctxt - structure to store the registers contents in
39 *
40 * NOTE: If there is a CPU register the modification of which by the
41 * boot kernel (ie. the kernel used for loading the hibernation image)
42 * might affect the operations of the restored target kernel (ie. the one
43 * saved in the hibernation image), then its contents must be saved by this
44 * function. In other words, if kernel A is hibernated and different
45 * kernel B is used for loading the hibernation image into memory, the
46 * kernel A's __save_processor_state() function must save all registers
47 * needed by kernel A, so that it can operate correctly after the resume
48 * regardless of what kernel B does in the meantime.
49 */
50static void __save_processor_state(struct saved_context *ctxt)
51{
52#ifdef CONFIG_X86_32
53 mtrr_save_fixed_ranges(NULL);
54#endif
55 kernel_fpu_begin();
56
57 /*
58 * descriptor tables
59 */
60#ifdef CONFIG_X86_32
61 store_idt(&ctxt->idt);
62#else
63/* CONFIG_X86_64 */
64 store_idt((struct desc_ptr *)&ctxt->idt_limit);
65#endif
66 /*
67 * We save it here, but restore it only in the hibernate case.
68 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
69 * mode in "secondary_startup_64". In 32-bit mode it is done via
70 * 'pmode_gdt' in wakeup_start.
71 */
72 ctxt->gdt_desc.size = GDT_SIZE - 1;
73 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
74
75 store_tr(ctxt->tr);
76
77 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
78 /*
79 * segment registers
80 */
81#ifdef CONFIG_X86_32
82 savesegment(es, ctxt->es);
83 savesegment(fs, ctxt->fs);
84 savesegment(gs, ctxt->gs);
85 savesegment(ss, ctxt->ss);
86#else
87/* CONFIG_X86_64 */
88 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
89 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
90 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
91 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
92 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
93
94 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
95 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
96 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
97 mtrr_save_fixed_ranges(NULL);
98
99 rdmsrl(MSR_EFER, ctxt->efer);
100#endif
101
102 /*
103 * control registers
104 */
105 ctxt->cr0 = read_cr0();
106 ctxt->cr2 = read_cr2();
107 ctxt->cr3 = read_cr3();
108#ifdef CONFIG_X86_32
109 ctxt->cr4 = read_cr4_safe();
110#else
111/* CONFIG_X86_64 */
112 ctxt->cr4 = read_cr4();
113 ctxt->cr8 = read_cr8();
114#endif
115 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
116 &ctxt->misc_enable);
117}
118
119/* Needed by apm.c */
120void save_processor_state(void)
121{
122 __save_processor_state(&saved_context);
123 x86_platform.save_sched_clock_state();
124}
125#ifdef CONFIG_X86_32
126EXPORT_SYMBOL(save_processor_state);
127#endif
128
129static void do_fpu_end(void)
130{
131 /*
132 * Restore FPU regs if necessary.
133 */
134 kernel_fpu_end();
135}
136
137static void fix_processor_context(void)
138{
139 int cpu = smp_processor_id();
140 struct tss_struct *t = &per_cpu(init_tss, cpu);
141#ifdef CONFIG_X86_64
142 struct desc_struct *desc = get_cpu_gdt_table(cpu);
143 tss_desc tss;
144#endif
145 set_tss_desc(cpu, t); /*
146 * This just modifies memory; should not be
147 * necessary. But... This is necessary, because
148 * 386 hardware has concept of busy TSS or some
149 * similar stupidity.
150 */
151
152#ifdef CONFIG_X86_64
153 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
154 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
155 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
156
157 syscall_init(); /* This sets MSR_*STAR and related */
158#endif
159 load_TR_desc(); /* This does ltr */
160 load_LDT(¤t->active_mm->context); /* This does lldt */
161}
162
163/**
164 * __restore_processor_state - restore the contents of CPU registers saved
165 * by __save_processor_state()
166 * @ctxt - structure to load the registers contents from
167 */
168static void __restore_processor_state(struct saved_context *ctxt)
169{
170 if (ctxt->misc_enable_saved)
171 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
172 /*
173 * control registers
174 */
175 /* cr4 was introduced in the Pentium CPU */
176#ifdef CONFIG_X86_32
177 if (ctxt->cr4)
178 write_cr4(ctxt->cr4);
179#else
180/* CONFIG X86_64 */
181 wrmsrl(MSR_EFER, ctxt->efer);
182 write_cr8(ctxt->cr8);
183 write_cr4(ctxt->cr4);
184#endif
185 write_cr3(ctxt->cr3);
186 write_cr2(ctxt->cr2);
187 write_cr0(ctxt->cr0);
188
189 /*
190 * now restore the descriptor tables to their proper values
191 * ltr is done i fix_processor_context().
192 */
193#ifdef CONFIG_X86_32
194 load_idt(&ctxt->idt);
195#else
196/* CONFIG_X86_64 */
197 load_idt((const struct desc_ptr *)&ctxt->idt_limit);
198#endif
199
200 /*
201 * segment registers
202 */
203#ifdef CONFIG_X86_32
204 loadsegment(es, ctxt->es);
205 loadsegment(fs, ctxt->fs);
206 loadsegment(gs, ctxt->gs);
207 loadsegment(ss, ctxt->ss);
208
209 /*
210 * sysenter MSRs
211 */
212 if (boot_cpu_has(X86_FEATURE_SEP))
213 enable_sep_cpu();
214#else
215/* CONFIG_X86_64 */
216 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
217 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
218 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
219 load_gs_index(ctxt->gs);
220 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
221
222 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
223 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
224 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
225#endif
226
227 /*
228 * restore XCR0 for xsave capable cpu's.
229 */
230 if (cpu_has_xsave)
231 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
232
233 fix_processor_context();
234
235 do_fpu_end();
236 x86_platform.restore_sched_clock_state();
237 mtrr_bp_restore();
238 perf_restore_debug_store();
239}
240
241/* Needed by apm.c */
242void restore_processor_state(void)
243{
244 __restore_processor_state(&saved_context);
245}
246#ifdef CONFIG_X86_32
247EXPORT_SYMBOL(restore_processor_state);
248#endif
249
250/*
251 * When bsp_check() is called in hibernate and suspend, cpu hotplug
252 * is disabled already. So it's unnessary to handle race condition between
253 * cpumask query and cpu hotplug.
254 */
255static int bsp_check(void)
256{
257 if (cpumask_first(cpu_online_mask) != 0) {
258 pr_warn("CPU0 is offline.\n");
259 return -ENODEV;
260 }
261
262 return 0;
263}
264
265static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
266 void *ptr)
267{
268 int ret = 0;
269
270 switch (action) {
271 case PM_SUSPEND_PREPARE:
272 case PM_HIBERNATION_PREPARE:
273 ret = bsp_check();
274 break;
275#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
276 case PM_RESTORE_PREPARE:
277 /*
278 * When system resumes from hibernation, online CPU0 because
279 * 1. it's required for resume and
280 * 2. the CPU was online before hibernation
281 */
282 if (!cpu_online(0))
283 _debug_hotplug_cpu(0, 1);
284 break;
285 case PM_POST_RESTORE:
286 /*
287 * When a resume really happens, this code won't be called.
288 *
289 * This code is called only when user space hibernation software
290 * prepares for snapshot device during boot time. So we just
291 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
292 * preparing the snapshot device.
293 *
294 * This works for normal boot case in our CPU0 hotplug debug
295 * mode, i.e. CPU0 is offline and user mode hibernation
296 * software initializes during boot time.
297 *
298 * If CPU0 is online and user application accesses snapshot
299 * device after boot time, this will offline CPU0 and user may
300 * see different CPU0 state before and after accessing
301 * the snapshot device. But hopefully this is not a case when
302 * user debugging CPU0 hotplug. Even if users hit this case,
303 * they can easily online CPU0 back.
304 *
305 * To simplify this debug code, we only consider normal boot
306 * case. Otherwise we need to remember CPU0's state and restore
307 * to that state and resolve racy conditions etc.
308 */
309 _debug_hotplug_cpu(0, 0);
310 break;
311#endif
312 default:
313 break;
314 }
315 return notifier_from_errno(ret);
316}
317
318static int __init bsp_pm_check_init(void)
319{
320 /*
321 * Set this bsp_pm_callback as lower priority than
322 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
323 * earlier to disable cpu hotplug before bsp online check.
324 */
325 pm_notifier(bsp_pm_callback, -INT_MAX);
326 return 0;
327}
328
329core_initcall(bsp_pm_check_init);