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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * User-space Probes (UProbes) for x86
4 *
5 * Copyright (C) IBM Corporation, 2008-2011
6 * Authors:
7 * Srikar Dronamraju
8 * Jim Keniston
9 */
10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/ptrace.h>
13#include <linux/uprobes.h>
14#include <linux/uaccess.h>
15
16#include <linux/kdebug.h>
17#include <asm/processor.h>
18#include <asm/insn.h>
19#include <asm/mmu_context.h>
20
21/* Post-execution fixups. */
22
23/* Adjust IP back to vicinity of actual insn */
24#define UPROBE_FIX_IP 0x01
25
26/* Adjust the return address of a call insn */
27#define UPROBE_FIX_CALL 0x02
28
29/* Instruction will modify TF, don't change it */
30#define UPROBE_FIX_SETF 0x04
31
32#define UPROBE_FIX_RIP_SI 0x08
33#define UPROBE_FIX_RIP_DI 0x10
34#define UPROBE_FIX_RIP_BX 0x20
35#define UPROBE_FIX_RIP_MASK \
36 (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX)
37
38#define UPROBE_TRAP_NR UINT_MAX
39
40/* Adaptations for mhiramat x86 decoder v14. */
41#define OPCODE1(insn) ((insn)->opcode.bytes[0])
42#define OPCODE2(insn) ((insn)->opcode.bytes[1])
43#define OPCODE3(insn) ((insn)->opcode.bytes[2])
44#define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value)
45
46#define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
47 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
48 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
49 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
50 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
51 << (row % 32))
52
53/*
54 * Good-instruction tables for 32-bit apps. This is non-const and volatile
55 * to keep gcc from statically optimizing it out, as variable_test_bit makes
56 * some versions of gcc to think only *(unsigned long*) is used.
57 *
58 * Opcodes we'll probably never support:
59 * 6c-6f - ins,outs. SEGVs if used in userspace
60 * e4-e7 - in,out imm. SEGVs if used in userspace
61 * ec-ef - in,out acc. SEGVs if used in userspace
62 * cc - int3. SIGTRAP if used in userspace
63 * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs
64 * (why we support bound (62) then? it's similar, and similarly unused...)
65 * f1 - int1. SIGTRAP if used in userspace
66 * f4 - hlt. SEGVs if used in userspace
67 * fa - cli. SEGVs if used in userspace
68 * fb - sti. SEGVs if used in userspace
69 *
70 * Opcodes which need some work to be supported:
71 * 07,17,1f - pop es/ss/ds
72 * Normally not used in userspace, but would execute if used.
73 * Can cause GP or stack exception if tries to load wrong segment descriptor.
74 * We hesitate to run them under single step since kernel's handling
75 * of userspace single-stepping (TF flag) is fragile.
76 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e)
77 * on the same grounds that they are never used.
78 * cd - int N.
79 * Used by userspace for "int 80" syscall entry. (Other "int N"
80 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
81 * Not supported since kernel's handling of userspace single-stepping
82 * (TF flag) is fragile.
83 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
84 */
85#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
86static volatile u32 good_insns_32[256 / 32] = {
87 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
88 /* ---------------------------------------------- */
89 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */
90 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
91 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
92 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
93 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
94 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
95 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
96 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
97 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
98 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
99 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
100 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
101 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
102 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
103 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
104 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
105 /* ---------------------------------------------- */
106 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
107};
108#else
109#define good_insns_32 NULL
110#endif
111
112/* Good-instruction tables for 64-bit apps.
113 *
114 * Genuinely invalid opcodes:
115 * 06,07 - formerly push/pop es
116 * 0e - formerly push cs
117 * 16,17 - formerly push/pop ss
118 * 1e,1f - formerly push/pop ds
119 * 27,2f,37,3f - formerly daa/das/aaa/aas
120 * 60,61 - formerly pusha/popa
121 * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported)
122 * 82 - formerly redundant encoding of Group1
123 * 9a - formerly call seg:ofs
124 * ce - formerly into
125 * d4,d5 - formerly aam/aad
126 * d6 - formerly undocumented salc
127 * ea - formerly jmp seg:ofs
128 *
129 * Opcodes we'll probably never support:
130 * 6c-6f - ins,outs. SEGVs if used in userspace
131 * e4-e7 - in,out imm. SEGVs if used in userspace
132 * ec-ef - in,out acc. SEGVs if used in userspace
133 * cc - int3. SIGTRAP if used in userspace
134 * f1 - int1. SIGTRAP if used in userspace
135 * f4 - hlt. SEGVs if used in userspace
136 * fa - cli. SEGVs if used in userspace
137 * fb - sti. SEGVs if used in userspace
138 *
139 * Opcodes which need some work to be supported:
140 * cd - int N.
141 * Used by userspace for "int 80" syscall entry. (Other "int N"
142 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
143 * Not supported since kernel's handling of userspace single-stepping
144 * (TF flag) is fragile.
145 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
146 */
147#if defined(CONFIG_X86_64)
148static volatile u32 good_insns_64[256 / 32] = {
149 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
150 /* ---------------------------------------------- */
151 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */
152 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
153 W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */
154 W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */
155 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
156 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
157 W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
158 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
159 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
160 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */
161 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
162 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
163 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
164 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
165 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */
166 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
167 /* ---------------------------------------------- */
168 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
169};
170#else
171#define good_insns_64 NULL
172#endif
173
174/* Using this for both 64-bit and 32-bit apps.
175 * Opcodes we don't support:
176 * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns
177 * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group.
178 * Also encodes tons of other system insns if mod=11.
179 * Some are in fact non-system: xend, xtest, rdtscp, maybe more
180 * 0f 05 - syscall
181 * 0f 06 - clts (CPL0 insn)
182 * 0f 07 - sysret
183 * 0f 08 - invd (CPL0 insn)
184 * 0f 09 - wbinvd (CPL0 insn)
185 * 0f 0b - ud2
186 * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?)
187 * 0f 34 - sysenter
188 * 0f 35 - sysexit
189 * 0f 37 - getsec
190 * 0f 78 - vmread (Intel VMX. CPL0 insn)
191 * 0f 79 - vmwrite (Intel VMX. CPL0 insn)
192 * Note: with prefixes, these two opcodes are
193 * extrq/insertq/AVX512 convert vector ops.
194 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt],
195 * {rd,wr}{fs,gs}base,{s,l,m}fence.
196 * Why? They are all user-executable.
197 */
198static volatile u32 good_2byte_insns[256 / 32] = {
199 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
200 /* ---------------------------------------------- */
201 W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */
202 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
203 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
204 W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
205 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
206 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
207 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
208 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */
209 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
210 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
211 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
212 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
213 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
214 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
215 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
216 W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */
217 /* ---------------------------------------------- */
218 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
219};
220#undef W
221
222/*
223 * opcodes we may need to refine support for:
224 *
225 * 0f - 2-byte instructions: For many of these instructions, the validity
226 * depends on the prefix and/or the reg field. On such instructions, we
227 * just consider the opcode combination valid if it corresponds to any
228 * valid instruction.
229 *
230 * 8f - Group 1 - only reg = 0 is OK
231 * c6-c7 - Group 11 - only reg = 0 is OK
232 * d9-df - fpu insns with some illegal encodings
233 * f2, f3 - repnz, repz prefixes. These are also the first byte for
234 * certain floating-point instructions, such as addsd.
235 *
236 * fe - Group 4 - only reg = 0 or 1 is OK
237 * ff - Group 5 - only reg = 0-6 is OK
238 *
239 * others -- Do we need to support these?
240 *
241 * 0f - (floating-point?) prefetch instructions
242 * 07, 17, 1f - pop es, pop ss, pop ds
243 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
244 * but 64 and 65 (fs: and gs:) seem to be used, so we support them
245 * 67 - addr16 prefix
246 * ce - into
247 * f0 - lock prefix
248 */
249
250/*
251 * TODO:
252 * - Where necessary, examine the modrm byte and allow only valid instructions
253 * in the different Groups and fpu instructions.
254 */
255
256static bool is_prefix_bad(struct insn *insn)
257{
258 insn_byte_t p;
259 int i;
260
261 for_each_insn_prefix(insn, i, p) {
262 insn_attr_t attr;
263
264 attr = inat_get_opcode_attribute(p);
265 switch (attr) {
266 case INAT_MAKE_PREFIX(INAT_PFX_ES):
267 case INAT_MAKE_PREFIX(INAT_PFX_CS):
268 case INAT_MAKE_PREFIX(INAT_PFX_DS):
269 case INAT_MAKE_PREFIX(INAT_PFX_SS):
270 case INAT_MAKE_PREFIX(INAT_PFX_LOCK):
271 return true;
272 }
273 }
274 return false;
275}
276
277static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64)
278{
279 enum insn_mode m = x86_64 ? INSN_MODE_64 : INSN_MODE_32;
280 u32 volatile *good_insns;
281 int ret;
282
283 ret = insn_decode(insn, auprobe->insn, sizeof(auprobe->insn), m);
284 if (ret < 0)
285 return -ENOEXEC;
286
287 if (is_prefix_bad(insn))
288 return -ENOTSUPP;
289
290 /* We should not singlestep on the exception masking instructions */
291 if (insn_masking_exception(insn))
292 return -ENOTSUPP;
293
294 if (x86_64)
295 good_insns = good_insns_64;
296 else
297 good_insns = good_insns_32;
298
299 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns))
300 return 0;
301
302 if (insn->opcode.nbytes == 2) {
303 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
304 return 0;
305 }
306
307 return -ENOTSUPP;
308}
309
310#ifdef CONFIG_X86_64
311/*
312 * If arch_uprobe->insn doesn't use rip-relative addressing, return
313 * immediately. Otherwise, rewrite the instruction so that it accesses
314 * its memory operand indirectly through a scratch register. Set
315 * defparam->fixups accordingly. (The contents of the scratch register
316 * will be saved before we single-step the modified instruction,
317 * and restored afterward).
318 *
319 * We do this because a rip-relative instruction can access only a
320 * relatively small area (+/- 2 GB from the instruction), and the XOL
321 * area typically lies beyond that area. At least for instructions
322 * that store to memory, we can't execute the original instruction
323 * and "fix things up" later, because the misdirected store could be
324 * disastrous.
325 *
326 * Some useful facts about rip-relative instructions:
327 *
328 * - There's always a modrm byte with bit layout "00 reg 101".
329 * - There's never a SIB byte.
330 * - The displacement is always 4 bytes.
331 * - REX.B=1 bit in REX prefix, which normally extends r/m field,
332 * has no effect on rip-relative mode. It doesn't make modrm byte
333 * with r/m=101 refer to register 1101 = R13.
334 */
335static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
336{
337 u8 *cursor;
338 u8 reg;
339 u8 reg2;
340
341 if (!insn_rip_relative(insn))
342 return;
343
344 /*
345 * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm.
346 * Clear REX.b bit (extension of MODRM.rm field):
347 * we want to encode low numbered reg, not r8+.
348 */
349 if (insn->rex_prefix.nbytes) {
350 cursor = auprobe->insn + insn_offset_rex_prefix(insn);
351 /* REX byte has 0100wrxb layout, clearing REX.b bit */
352 *cursor &= 0xfe;
353 }
354 /*
355 * Similar treatment for VEX3/EVEX prefix.
356 * TODO: add XOP treatment when insn decoder supports them
357 */
358 if (insn->vex_prefix.nbytes >= 3) {
359 /*
360 * vex2: c5 rvvvvLpp (has no b bit)
361 * vex3/xop: c4/8f rxbmmmmm wvvvvLpp
362 * evex: 62 rxbR00mm wvvvv1pp zllBVaaa
363 * Setting VEX3.b (setting because it has inverted meaning).
364 * Setting EVEX.x since (in non-SIB encoding) EVEX.x
365 * is the 4th bit of MODRM.rm, and needs the same treatment.
366 * For VEX3-encoded insns, VEX3.x value has no effect in
367 * non-SIB encoding, the change is superfluous but harmless.
368 */
369 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1;
370 *cursor |= 0x60;
371 }
372
373 /*
374 * Convert from rip-relative addressing to register-relative addressing
375 * via a scratch register.
376 *
377 * This is tricky since there are insns with modrm byte
378 * which also use registers not encoded in modrm byte:
379 * [i]div/[i]mul: implicitly use dx:ax
380 * shift ops: implicitly use cx
381 * cmpxchg: implicitly uses ax
382 * cmpxchg8/16b: implicitly uses dx:ax and bx:cx
383 * Encoding: 0f c7/1 modrm
384 * The code below thinks that reg=1 (cx), chooses si as scratch.
385 * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m.
386 * First appeared in Haswell (BMI2 insn). It is vex-encoded.
387 * Example where none of bx,cx,dx can be used as scratch reg:
388 * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx
389 * [v]pcmpistri: implicitly uses cx, xmm0
390 * [v]pcmpistrm: implicitly uses xmm0
391 * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0
392 * [v]pcmpestrm: implicitly uses ax, dx, xmm0
393 * Evil SSE4.2 string comparison ops from hell.
394 * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination.
395 * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm.
396 * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi).
397 * AMD says it has no 3-operand form (vex.vvvv must be 1111)
398 * and that it can have only register operands, not mem
399 * (its modrm byte must have mode=11).
400 * If these restrictions will ever be lifted,
401 * we'll need code to prevent selection of di as scratch reg!
402 *
403 * Summary: I don't know any insns with modrm byte which
404 * use SI register implicitly. DI register is used only
405 * by one insn (maskmovq) and BX register is used
406 * only by one too (cmpxchg8b).
407 * BP is stack-segment based (may be a problem?).
408 * AX, DX, CX are off-limits (many implicit users).
409 * SP is unusable (it's stack pointer - think about "pop mem";
410 * also, rsp+disp32 needs sib encoding -> insn length change).
411 */
412
413 reg = MODRM_REG(insn); /* Fetch modrm.reg */
414 reg2 = 0xff; /* Fetch vex.vvvv */
415 if (insn->vex_prefix.nbytes)
416 reg2 = insn->vex_prefix.bytes[2];
417 /*
418 * TODO: add XOP vvvv reading.
419 *
420 * vex.vvvv field is in bits 6-3, bits are inverted.
421 * But in 32-bit mode, high-order bit may be ignored.
422 * Therefore, let's consider only 3 low-order bits.
423 */
424 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7;
425 /*
426 * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15.
427 *
428 * Choose scratch reg. Order is important: must not select bx
429 * if we can use si (cmpxchg8b case!)
430 */
431 if (reg != 6 && reg2 != 6) {
432 reg2 = 6;
433 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI;
434 } else if (reg != 7 && reg2 != 7) {
435 reg2 = 7;
436 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI;
437 /* TODO (paranoia): force maskmovq to not use di */
438 } else {
439 reg2 = 3;
440 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX;
441 }
442 /*
443 * Point cursor at the modrm byte. The next 4 bytes are the
444 * displacement. Beyond the displacement, for some instructions,
445 * is the immediate operand.
446 */
447 cursor = auprobe->insn + insn_offset_modrm(insn);
448 /*
449 * Change modrm from "00 reg 101" to "10 reg reg2". Example:
450 * 89 05 disp32 mov %eax,disp32(%rip) becomes
451 * 89 86 disp32 mov %eax,disp32(%rsi)
452 */
453 *cursor = 0x80 | (reg << 3) | reg2;
454}
455
456static inline unsigned long *
457scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs)
458{
459 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI)
460 return ®s->si;
461 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI)
462 return ®s->di;
463 return ®s->bx;
464}
465
466/*
467 * If we're emulating a rip-relative instruction, save the contents
468 * of the scratch register and store the target address in that register.
469 */
470static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
471{
472 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
473 struct uprobe_task *utask = current->utask;
474 unsigned long *sr = scratch_reg(auprobe, regs);
475
476 utask->autask.saved_scratch_register = *sr;
477 *sr = utask->vaddr + auprobe->defparam.ilen;
478 }
479}
480
481static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
482{
483 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
484 struct uprobe_task *utask = current->utask;
485 unsigned long *sr = scratch_reg(auprobe, regs);
486
487 *sr = utask->autask.saved_scratch_register;
488 }
489}
490#else /* 32-bit: */
491/*
492 * No RIP-relative addressing on 32-bit
493 */
494static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
495{
496}
497static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
498{
499}
500static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
501{
502}
503#endif /* CONFIG_X86_64 */
504
505struct uprobe_xol_ops {
506 bool (*emulate)(struct arch_uprobe *, struct pt_regs *);
507 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *);
508 int (*post_xol)(struct arch_uprobe *, struct pt_regs *);
509 void (*abort)(struct arch_uprobe *, struct pt_regs *);
510};
511
512static inline int sizeof_long(struct pt_regs *regs)
513{
514 /*
515 * Check registers for mode as in_xxx_syscall() does not apply here.
516 */
517 return user_64bit_mode(regs) ? 8 : 4;
518}
519
520static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
521{
522 riprel_pre_xol(auprobe, regs);
523 return 0;
524}
525
526static int emulate_push_stack(struct pt_regs *regs, unsigned long val)
527{
528 unsigned long new_sp = regs->sp - sizeof_long(regs);
529
530 if (copy_to_user((void __user *)new_sp, &val, sizeof_long(regs)))
531 return -EFAULT;
532
533 regs->sp = new_sp;
534 return 0;
535}
536
537/*
538 * We have to fix things up as follows:
539 *
540 * Typically, the new ip is relative to the copied instruction. We need
541 * to make it relative to the original instruction (FIX_IP). Exceptions
542 * are return instructions and absolute or indirect jump or call instructions.
543 *
544 * If the single-stepped instruction was a call, the return address that
545 * is atop the stack is the address following the copied instruction. We
546 * need to make it the address following the original instruction (FIX_CALL).
547 *
548 * If the original instruction was a rip-relative instruction such as
549 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
550 * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)".
551 * We need to restore the contents of the scratch register
552 * (FIX_RIP_reg).
553 */
554static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
555{
556 struct uprobe_task *utask = current->utask;
557
558 riprel_post_xol(auprobe, regs);
559 if (auprobe->defparam.fixups & UPROBE_FIX_IP) {
560 long correction = utask->vaddr - utask->xol_vaddr;
561 regs->ip += correction;
562 } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) {
563 regs->sp += sizeof_long(regs); /* Pop incorrect return address */
564 if (emulate_push_stack(regs, utask->vaddr + auprobe->defparam.ilen))
565 return -ERESTART;
566 }
567 /* popf; tell the caller to not touch TF */
568 if (auprobe->defparam.fixups & UPROBE_FIX_SETF)
569 utask->autask.saved_tf = true;
570
571 return 0;
572}
573
574static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
575{
576 riprel_post_xol(auprobe, regs);
577}
578
579static const struct uprobe_xol_ops default_xol_ops = {
580 .pre_xol = default_pre_xol_op,
581 .post_xol = default_post_xol_op,
582 .abort = default_abort_op,
583};
584
585static bool branch_is_call(struct arch_uprobe *auprobe)
586{
587 return auprobe->branch.opc1 == 0xe8;
588}
589
590#define CASE_COND \
591 COND(70, 71, XF(OF)) \
592 COND(72, 73, XF(CF)) \
593 COND(74, 75, XF(ZF)) \
594 COND(78, 79, XF(SF)) \
595 COND(7a, 7b, XF(PF)) \
596 COND(76, 77, XF(CF) || XF(ZF)) \
597 COND(7c, 7d, XF(SF) != XF(OF)) \
598 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF))
599
600#define COND(op_y, op_n, expr) \
601 case 0x ## op_y: DO((expr) != 0) \
602 case 0x ## op_n: DO((expr) == 0)
603
604#define XF(xf) (!!(flags & X86_EFLAGS_ ## xf))
605
606static bool is_cond_jmp_opcode(u8 opcode)
607{
608 switch (opcode) {
609 #define DO(expr) \
610 return true;
611 CASE_COND
612 #undef DO
613
614 default:
615 return false;
616 }
617}
618
619static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs)
620{
621 unsigned long flags = regs->flags;
622
623 switch (auprobe->branch.opc1) {
624 #define DO(expr) \
625 return expr;
626 CASE_COND
627 #undef DO
628
629 default: /* not a conditional jmp */
630 return true;
631 }
632}
633
634#undef XF
635#undef COND
636#undef CASE_COND
637
638static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
639{
640 unsigned long new_ip = regs->ip += auprobe->branch.ilen;
641 unsigned long offs = (long)auprobe->branch.offs;
642
643 if (branch_is_call(auprobe)) {
644 /*
645 * If it fails we execute this (mangled, see the comment in
646 * branch_clear_offset) insn out-of-line. In the likely case
647 * this should trigger the trap, and the probed application
648 * should die or restart the same insn after it handles the
649 * signal, arch_uprobe_post_xol() won't be even called.
650 *
651 * But there is corner case, see the comment in ->post_xol().
652 */
653 if (emulate_push_stack(regs, new_ip))
654 return false;
655 } else if (!check_jmp_cond(auprobe, regs)) {
656 offs = 0;
657 }
658
659 regs->ip = new_ip + offs;
660 return true;
661}
662
663static bool push_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
664{
665 unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset;
666
667 if (emulate_push_stack(regs, *src_ptr))
668 return false;
669 regs->ip += auprobe->push.ilen;
670 return true;
671}
672
673static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
674{
675 BUG_ON(!branch_is_call(auprobe));
676 /*
677 * We can only get here if branch_emulate_op() failed to push the ret
678 * address _and_ another thread expanded our stack before the (mangled)
679 * "call" insn was executed out-of-line. Just restore ->sp and restart.
680 * We could also restore ->ip and try to call branch_emulate_op() again.
681 */
682 regs->sp += sizeof_long(regs);
683 return -ERESTART;
684}
685
686static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn)
687{
688 /*
689 * Turn this insn into "call 1f; 1:", this is what we will execute
690 * out-of-line if ->emulate() fails. We only need this to generate
691 * a trap, so that the probed task receives the correct signal with
692 * the properly filled siginfo.
693 *
694 * But see the comment in ->post_xol(), in the unlikely case it can
695 * succeed. So we need to ensure that the new ->ip can not fall into
696 * the non-canonical area and trigger #GP.
697 *
698 * We could turn it into (say) "pushf", but then we would need to
699 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte
700 * of ->insn[] for set_orig_insn().
701 */
702 memset(auprobe->insn + insn_offset_immediate(insn),
703 0, insn->immediate.nbytes);
704}
705
706static const struct uprobe_xol_ops branch_xol_ops = {
707 .emulate = branch_emulate_op,
708 .post_xol = branch_post_xol_op,
709};
710
711static const struct uprobe_xol_ops push_xol_ops = {
712 .emulate = push_emulate_op,
713};
714
715/* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */
716static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
717{
718 u8 opc1 = OPCODE1(insn);
719 insn_byte_t p;
720 int i;
721
722 switch (opc1) {
723 case 0xeb: /* jmp 8 */
724 case 0xe9: /* jmp 32 */
725 break;
726 case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */
727 goto setup;
728
729 case 0xe8: /* call relative */
730 branch_clear_offset(auprobe, insn);
731 break;
732
733 case 0x0f:
734 if (insn->opcode.nbytes != 2)
735 return -ENOSYS;
736 /*
737 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches
738 * OPCODE1() of the "short" jmp which checks the same condition.
739 */
740 opc1 = OPCODE2(insn) - 0x10;
741 fallthrough;
742 default:
743 if (!is_cond_jmp_opcode(opc1))
744 return -ENOSYS;
745 }
746
747 /*
748 * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported.
749 * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix.
750 * No one uses these insns, reject any branch insns with such prefix.
751 */
752 for_each_insn_prefix(insn, i, p) {
753 if (p == 0x66)
754 return -ENOTSUPP;
755 }
756
757setup:
758 auprobe->branch.opc1 = opc1;
759 auprobe->branch.ilen = insn->length;
760 auprobe->branch.offs = insn->immediate.value;
761
762 auprobe->ops = &branch_xol_ops;
763 return 0;
764}
765
766/* Returns -ENOSYS if push_xol_ops doesn't handle this insn */
767static int push_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
768{
769 u8 opc1 = OPCODE1(insn), reg_offset = 0;
770
771 if (opc1 < 0x50 || opc1 > 0x57)
772 return -ENOSYS;
773
774 if (insn->length > 2)
775 return -ENOSYS;
776 if (insn->length == 2) {
777 /* only support rex_prefix 0x41 (x64 only) */
778#ifdef CONFIG_X86_64
779 if (insn->rex_prefix.nbytes != 1 ||
780 insn->rex_prefix.bytes[0] != 0x41)
781 return -ENOSYS;
782
783 switch (opc1) {
784 case 0x50:
785 reg_offset = offsetof(struct pt_regs, r8);
786 break;
787 case 0x51:
788 reg_offset = offsetof(struct pt_regs, r9);
789 break;
790 case 0x52:
791 reg_offset = offsetof(struct pt_regs, r10);
792 break;
793 case 0x53:
794 reg_offset = offsetof(struct pt_regs, r11);
795 break;
796 case 0x54:
797 reg_offset = offsetof(struct pt_regs, r12);
798 break;
799 case 0x55:
800 reg_offset = offsetof(struct pt_regs, r13);
801 break;
802 case 0x56:
803 reg_offset = offsetof(struct pt_regs, r14);
804 break;
805 case 0x57:
806 reg_offset = offsetof(struct pt_regs, r15);
807 break;
808 }
809#else
810 return -ENOSYS;
811#endif
812 } else {
813 switch (opc1) {
814 case 0x50:
815 reg_offset = offsetof(struct pt_regs, ax);
816 break;
817 case 0x51:
818 reg_offset = offsetof(struct pt_regs, cx);
819 break;
820 case 0x52:
821 reg_offset = offsetof(struct pt_regs, dx);
822 break;
823 case 0x53:
824 reg_offset = offsetof(struct pt_regs, bx);
825 break;
826 case 0x54:
827 reg_offset = offsetof(struct pt_regs, sp);
828 break;
829 case 0x55:
830 reg_offset = offsetof(struct pt_regs, bp);
831 break;
832 case 0x56:
833 reg_offset = offsetof(struct pt_regs, si);
834 break;
835 case 0x57:
836 reg_offset = offsetof(struct pt_regs, di);
837 break;
838 }
839 }
840
841 auprobe->push.reg_offset = reg_offset;
842 auprobe->push.ilen = insn->length;
843 auprobe->ops = &push_xol_ops;
844 return 0;
845}
846
847/**
848 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
849 * @auprobe: the probepoint information.
850 * @mm: the probed address space.
851 * @addr: virtual address at which to install the probepoint
852 * Return 0 on success or a -ve number on error.
853 */
854int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
855{
856 struct insn insn;
857 u8 fix_ip_or_call = UPROBE_FIX_IP;
858 int ret;
859
860 ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm));
861 if (ret)
862 return ret;
863
864 ret = branch_setup_xol_ops(auprobe, &insn);
865 if (ret != -ENOSYS)
866 return ret;
867
868 ret = push_setup_xol_ops(auprobe, &insn);
869 if (ret != -ENOSYS)
870 return ret;
871
872 /*
873 * Figure out which fixups default_post_xol_op() will need to perform,
874 * and annotate defparam->fixups accordingly.
875 */
876 switch (OPCODE1(&insn)) {
877 case 0x9d: /* popf */
878 auprobe->defparam.fixups |= UPROBE_FIX_SETF;
879 break;
880 case 0xc3: /* ret or lret -- ip is correct */
881 case 0xcb:
882 case 0xc2:
883 case 0xca:
884 case 0xea: /* jmp absolute -- ip is correct */
885 fix_ip_or_call = 0;
886 break;
887 case 0x9a: /* call absolute - Fix return addr, not ip */
888 fix_ip_or_call = UPROBE_FIX_CALL;
889 break;
890 case 0xff:
891 switch (MODRM_REG(&insn)) {
892 case 2: case 3: /* call or lcall, indirect */
893 fix_ip_or_call = UPROBE_FIX_CALL;
894 break;
895 case 4: case 5: /* jmp or ljmp, indirect */
896 fix_ip_or_call = 0;
897 break;
898 }
899 fallthrough;
900 default:
901 riprel_analyze(auprobe, &insn);
902 }
903
904 auprobe->defparam.ilen = insn.length;
905 auprobe->defparam.fixups |= fix_ip_or_call;
906
907 auprobe->ops = &default_xol_ops;
908 return 0;
909}
910
911/*
912 * arch_uprobe_pre_xol - prepare to execute out of line.
913 * @auprobe: the probepoint information.
914 * @regs: reflects the saved user state of current task.
915 */
916int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
917{
918 struct uprobe_task *utask = current->utask;
919
920 if (auprobe->ops->pre_xol) {
921 int err = auprobe->ops->pre_xol(auprobe, regs);
922 if (err)
923 return err;
924 }
925
926 regs->ip = utask->xol_vaddr;
927 utask->autask.saved_trap_nr = current->thread.trap_nr;
928 current->thread.trap_nr = UPROBE_TRAP_NR;
929
930 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF);
931 regs->flags |= X86_EFLAGS_TF;
932 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP))
933 set_task_blockstep(current, false);
934
935 return 0;
936}
937
938/*
939 * If xol insn itself traps and generates a signal(Say,
940 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
941 * instruction jumps back to its own address. It is assumed that anything
942 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
943 *
944 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
945 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
946 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
947 */
948bool arch_uprobe_xol_was_trapped(struct task_struct *t)
949{
950 if (t->thread.trap_nr != UPROBE_TRAP_NR)
951 return true;
952
953 return false;
954}
955
956/*
957 * Called after single-stepping. To avoid the SMP problems that can
958 * occur when we temporarily put back the original opcode to
959 * single-step, we single-stepped a copy of the instruction.
960 *
961 * This function prepares to resume execution after the single-step.
962 */
963int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
964{
965 struct uprobe_task *utask = current->utask;
966 bool send_sigtrap = utask->autask.saved_tf;
967 int err = 0;
968
969 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
970 current->thread.trap_nr = utask->autask.saved_trap_nr;
971
972 if (auprobe->ops->post_xol) {
973 err = auprobe->ops->post_xol(auprobe, regs);
974 if (err) {
975 /*
976 * Restore ->ip for restart or post mortem analysis.
977 * ->post_xol() must not return -ERESTART unless this
978 * is really possible.
979 */
980 regs->ip = utask->vaddr;
981 if (err == -ERESTART)
982 err = 0;
983 send_sigtrap = false;
984 }
985 }
986 /*
987 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP
988 * so we can get an extra SIGTRAP if we do not clear TF. We need
989 * to examine the opcode to make it right.
990 */
991 if (send_sigtrap)
992 send_sig(SIGTRAP, current, 0);
993
994 if (!utask->autask.saved_tf)
995 regs->flags &= ~X86_EFLAGS_TF;
996
997 return err;
998}
999
1000/* callback routine for handling exceptions. */
1001int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
1002{
1003 struct die_args *args = data;
1004 struct pt_regs *regs = args->regs;
1005 int ret = NOTIFY_DONE;
1006
1007 /* We are only interested in userspace traps */
1008 if (regs && !user_mode(regs))
1009 return NOTIFY_DONE;
1010
1011 switch (val) {
1012 case DIE_INT3:
1013 if (uprobe_pre_sstep_notifier(regs))
1014 ret = NOTIFY_STOP;
1015
1016 break;
1017
1018 case DIE_DEBUG:
1019 if (uprobe_post_sstep_notifier(regs))
1020 ret = NOTIFY_STOP;
1021
1022 break;
1023
1024 default:
1025 break;
1026 }
1027
1028 return ret;
1029}
1030
1031/*
1032 * This function gets called when XOL instruction either gets trapped or
1033 * the thread has a fatal signal. Reset the instruction pointer to its
1034 * probed address for the potential restart or for post mortem analysis.
1035 */
1036void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
1037{
1038 struct uprobe_task *utask = current->utask;
1039
1040 if (auprobe->ops->abort)
1041 auprobe->ops->abort(auprobe, regs);
1042
1043 current->thread.trap_nr = utask->autask.saved_trap_nr;
1044 regs->ip = utask->vaddr;
1045 /* clear TF if it was set by us in arch_uprobe_pre_xol() */
1046 if (!utask->autask.saved_tf)
1047 regs->flags &= ~X86_EFLAGS_TF;
1048}
1049
1050static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
1051{
1052 if (auprobe->ops->emulate)
1053 return auprobe->ops->emulate(auprobe, regs);
1054 return false;
1055}
1056
1057bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
1058{
1059 bool ret = __skip_sstep(auprobe, regs);
1060 if (ret && (regs->flags & X86_EFLAGS_TF))
1061 send_sig(SIGTRAP, current, 0);
1062 return ret;
1063}
1064
1065unsigned long
1066arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
1067{
1068 int rasize = sizeof_long(regs), nleft;
1069 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
1070
1071 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize))
1072 return -1;
1073
1074 /* check whether address has been already hijacked */
1075 if (orig_ret_vaddr == trampoline_vaddr)
1076 return orig_ret_vaddr;
1077
1078 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
1079 if (likely(!nleft))
1080 return orig_ret_vaddr;
1081
1082 if (nleft != rasize) {
1083 pr_err("return address clobbered: pid=%d, %%sp=%#lx, %%ip=%#lx\n",
1084 current->pid, regs->sp, regs->ip);
1085
1086 force_sig(SIGSEGV);
1087 }
1088
1089 return -1;
1090}
1091
1092bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
1093 struct pt_regs *regs)
1094{
1095 if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */
1096 return regs->sp < ret->stack;
1097 else
1098 return regs->sp <= ret->stack;
1099}
1/*
2 * User-space Probes (UProbes) for x86
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright (C) IBM Corporation, 2008-2011
19 * Authors:
20 * Srikar Dronamraju
21 * Jim Keniston
22 */
23#include <linux/kernel.h>
24#include <linux/sched.h>
25#include <linux/ptrace.h>
26#include <linux/uprobes.h>
27#include <linux/uaccess.h>
28
29#include <linux/kdebug.h>
30#include <asm/processor.h>
31#include <asm/insn.h>
32
33/* Post-execution fixups. */
34
35/* No fixup needed */
36#define UPROBE_FIX_NONE 0x0
37
38/* Adjust IP back to vicinity of actual insn */
39#define UPROBE_FIX_IP 0x1
40
41/* Adjust the return address of a call insn */
42#define UPROBE_FIX_CALL 0x2
43
44/* Instruction will modify TF, don't change it */
45#define UPROBE_FIX_SETF 0x4
46
47#define UPROBE_FIX_RIP_AX 0x8000
48#define UPROBE_FIX_RIP_CX 0x4000
49
50#define UPROBE_TRAP_NR UINT_MAX
51
52/* Adaptations for mhiramat x86 decoder v14. */
53#define OPCODE1(insn) ((insn)->opcode.bytes[0])
54#define OPCODE2(insn) ((insn)->opcode.bytes[1])
55#define OPCODE3(insn) ((insn)->opcode.bytes[2])
56#define MODRM_REG(insn) X86_MODRM_REG(insn->modrm.value)
57
58#define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
59 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
60 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
61 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
62 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
63 << (row % 32))
64
65/*
66 * Good-instruction tables for 32-bit apps. This is non-const and volatile
67 * to keep gcc from statically optimizing it out, as variable_test_bit makes
68 * some versions of gcc to think only *(unsigned long*) is used.
69 */
70static volatile u32 good_insns_32[256 / 32] = {
71 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
72 /* ---------------------------------------------- */
73 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 00 */
74 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
75 W(0x20, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* 20 */
76 W(0x30, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1) , /* 30 */
77 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
78 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
79 W(0x60, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
80 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
81 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
82 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
83 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
84 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
85 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
86 W(0xd0, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
87 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
88 W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
89 /* ---------------------------------------------- */
90 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
91};
92
93/* Using this for both 64-bit and 32-bit apps */
94static volatile u32 good_2byte_insns[256 / 32] = {
95 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
96 /* ---------------------------------------------- */
97 W(0x00, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1) | /* 00 */
98 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
99 W(0x20, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
100 W(0x30, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) , /* 30 */
101 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
102 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
103 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
104 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1) , /* 70 */
105 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
106 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
107 W(0xa0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
108 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
109 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
110 W(0xd0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
111 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
112 W(0xf0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0) /* f0 */
113 /* ---------------------------------------------- */
114 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
115};
116
117#ifdef CONFIG_X86_64
118/* Good-instruction tables for 64-bit apps */
119static volatile u32 good_insns_64[256 / 32] = {
120 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
121 /* ---------------------------------------------- */
122 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 00 */
123 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
124 W(0x20, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) | /* 20 */
125 W(0x30, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 30 */
126 W(0x40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | /* 40 */
127 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
128 W(0x60, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
129 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
130 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
131 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
132 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
133 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
134 W(0xc0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
135 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
136 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
137 W(0xf0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
138 /* ---------------------------------------------- */
139 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
140};
141#endif
142#undef W
143
144/*
145 * opcodes we'll probably never support:
146 *
147 * 6c-6d, e4-e5, ec-ed - in
148 * 6e-6f, e6-e7, ee-ef - out
149 * cc, cd - int3, int
150 * cf - iret
151 * d6 - illegal instruction
152 * f1 - int1/icebp
153 * f4 - hlt
154 * fa, fb - cli, sti
155 * 0f - lar, lsl, syscall, clts, sysret, sysenter, sysexit, invd, wbinvd, ud2
156 *
157 * invalid opcodes in 64-bit mode:
158 *
159 * 06, 0e, 16, 1e, 27, 2f, 37, 3f, 60-62, 82, c4-c5, d4-d5
160 * 63 - we support this opcode in x86_64 but not in i386.
161 *
162 * opcodes we may need to refine support for:
163 *
164 * 0f - 2-byte instructions: For many of these instructions, the validity
165 * depends on the prefix and/or the reg field. On such instructions, we
166 * just consider the opcode combination valid if it corresponds to any
167 * valid instruction.
168 *
169 * 8f - Group 1 - only reg = 0 is OK
170 * c6-c7 - Group 11 - only reg = 0 is OK
171 * d9-df - fpu insns with some illegal encodings
172 * f2, f3 - repnz, repz prefixes. These are also the first byte for
173 * certain floating-point instructions, such as addsd.
174 *
175 * fe - Group 4 - only reg = 0 or 1 is OK
176 * ff - Group 5 - only reg = 0-6 is OK
177 *
178 * others -- Do we need to support these?
179 *
180 * 0f - (floating-point?) prefetch instructions
181 * 07, 17, 1f - pop es, pop ss, pop ds
182 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
183 * but 64 and 65 (fs: and gs:) seem to be used, so we support them
184 * 67 - addr16 prefix
185 * ce - into
186 * f0 - lock prefix
187 */
188
189/*
190 * TODO:
191 * - Where necessary, examine the modrm byte and allow only valid instructions
192 * in the different Groups and fpu instructions.
193 */
194
195static bool is_prefix_bad(struct insn *insn)
196{
197 int i;
198
199 for (i = 0; i < insn->prefixes.nbytes; i++) {
200 switch (insn->prefixes.bytes[i]) {
201 case 0x26: /* INAT_PFX_ES */
202 case 0x2E: /* INAT_PFX_CS */
203 case 0x36: /* INAT_PFX_DS */
204 case 0x3E: /* INAT_PFX_SS */
205 case 0xF0: /* INAT_PFX_LOCK */
206 return true;
207 }
208 }
209 return false;
210}
211
212static int validate_insn_32bits(struct arch_uprobe *auprobe, struct insn *insn)
213{
214 insn_init(insn, auprobe->insn, false);
215
216 /* Skip good instruction prefixes; reject "bad" ones. */
217 insn_get_opcode(insn);
218 if (is_prefix_bad(insn))
219 return -ENOTSUPP;
220
221 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_32))
222 return 0;
223
224 if (insn->opcode.nbytes == 2) {
225 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
226 return 0;
227 }
228
229 return -ENOTSUPP;
230}
231
232/*
233 * Figure out which fixups arch_uprobe_post_xol() will need to perform, and
234 * annotate arch_uprobe->fixups accordingly. To start with,
235 * arch_uprobe->fixups is either zero or it reflects rip-related fixups.
236 */
237static void prepare_fixups(struct arch_uprobe *auprobe, struct insn *insn)
238{
239 bool fix_ip = true, fix_call = false; /* defaults */
240 int reg;
241
242 insn_get_opcode(insn); /* should be a nop */
243
244 switch (OPCODE1(insn)) {
245 case 0x9d:
246 /* popf */
247 auprobe->fixups |= UPROBE_FIX_SETF;
248 break;
249 case 0xc3: /* ret/lret */
250 case 0xcb:
251 case 0xc2:
252 case 0xca:
253 /* ip is correct */
254 fix_ip = false;
255 break;
256 case 0xe8: /* call relative - Fix return addr */
257 fix_call = true;
258 break;
259 case 0x9a: /* call absolute - Fix return addr, not ip */
260 fix_call = true;
261 fix_ip = false;
262 break;
263 case 0xff:
264 insn_get_modrm(insn);
265 reg = MODRM_REG(insn);
266 if (reg == 2 || reg == 3) {
267 /* call or lcall, indirect */
268 /* Fix return addr; ip is correct. */
269 fix_call = true;
270 fix_ip = false;
271 } else if (reg == 4 || reg == 5) {
272 /* jmp or ljmp, indirect */
273 /* ip is correct. */
274 fix_ip = false;
275 }
276 break;
277 case 0xea: /* jmp absolute -- ip is correct */
278 fix_ip = false;
279 break;
280 default:
281 break;
282 }
283 if (fix_ip)
284 auprobe->fixups |= UPROBE_FIX_IP;
285 if (fix_call)
286 auprobe->fixups |= UPROBE_FIX_CALL;
287}
288
289#ifdef CONFIG_X86_64
290/*
291 * If arch_uprobe->insn doesn't use rip-relative addressing, return
292 * immediately. Otherwise, rewrite the instruction so that it accesses
293 * its memory operand indirectly through a scratch register. Set
294 * arch_uprobe->fixups and arch_uprobe->rip_rela_target_address
295 * accordingly. (The contents of the scratch register will be saved
296 * before we single-step the modified instruction, and restored
297 * afterward.)
298 *
299 * We do this because a rip-relative instruction can access only a
300 * relatively small area (+/- 2 GB from the instruction), and the XOL
301 * area typically lies beyond that area. At least for instructions
302 * that store to memory, we can't execute the original instruction
303 * and "fix things up" later, because the misdirected store could be
304 * disastrous.
305 *
306 * Some useful facts about rip-relative instructions:
307 *
308 * - There's always a modrm byte.
309 * - There's never a SIB byte.
310 * - The displacement is always 4 bytes.
311 */
312static void
313handle_riprel_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
314{
315 u8 *cursor;
316 u8 reg;
317
318 if (mm->context.ia32_compat)
319 return;
320
321 auprobe->rip_rela_target_address = 0x0;
322 if (!insn_rip_relative(insn))
323 return;
324
325 /*
326 * insn_rip_relative() would have decoded rex_prefix, modrm.
327 * Clear REX.b bit (extension of MODRM.rm field):
328 * we want to encode rax/rcx, not r8/r9.
329 */
330 if (insn->rex_prefix.nbytes) {
331 cursor = auprobe->insn + insn_offset_rex_prefix(insn);
332 *cursor &= 0xfe; /* Clearing REX.B bit */
333 }
334
335 /*
336 * Point cursor at the modrm byte. The next 4 bytes are the
337 * displacement. Beyond the displacement, for some instructions,
338 * is the immediate operand.
339 */
340 cursor = auprobe->insn + insn_offset_modrm(insn);
341 insn_get_length(insn);
342
343 /*
344 * Convert from rip-relative addressing to indirect addressing
345 * via a scratch register. Change the r/m field from 0x5 (%rip)
346 * to 0x0 (%rax) or 0x1 (%rcx), and squeeze out the offset field.
347 */
348 reg = MODRM_REG(insn);
349 if (reg == 0) {
350 /*
351 * The register operand (if any) is either the A register
352 * (%rax, %eax, etc.) or (if the 0x4 bit is set in the
353 * REX prefix) %r8. In any case, we know the C register
354 * is NOT the register operand, so we use %rcx (register
355 * #1) for the scratch register.
356 */
357 auprobe->fixups = UPROBE_FIX_RIP_CX;
358 /* Change modrm from 00 000 101 to 00 000 001. */
359 *cursor = 0x1;
360 } else {
361 /* Use %rax (register #0) for the scratch register. */
362 auprobe->fixups = UPROBE_FIX_RIP_AX;
363 /* Change modrm from 00 xxx 101 to 00 xxx 000 */
364 *cursor = (reg << 3);
365 }
366
367 /* Target address = address of next instruction + (signed) offset */
368 auprobe->rip_rela_target_address = (long)insn->length + insn->displacement.value;
369
370 /* Displacement field is gone; slide immediate field (if any) over. */
371 if (insn->immediate.nbytes) {
372 cursor++;
373 memmove(cursor, cursor + insn->displacement.nbytes, insn->immediate.nbytes);
374 }
375 return;
376}
377
378static int validate_insn_64bits(struct arch_uprobe *auprobe, struct insn *insn)
379{
380 insn_init(insn, auprobe->insn, true);
381
382 /* Skip good instruction prefixes; reject "bad" ones. */
383 insn_get_opcode(insn);
384 if (is_prefix_bad(insn))
385 return -ENOTSUPP;
386
387 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns_64))
388 return 0;
389
390 if (insn->opcode.nbytes == 2) {
391 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
392 return 0;
393 }
394 return -ENOTSUPP;
395}
396
397static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
398{
399 if (mm->context.ia32_compat)
400 return validate_insn_32bits(auprobe, insn);
401 return validate_insn_64bits(auprobe, insn);
402}
403#else /* 32-bit: */
404static void handle_riprel_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
405{
406 /* No RIP-relative addressing on 32-bit */
407}
408
409static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, struct insn *insn)
410{
411 return validate_insn_32bits(auprobe, insn);
412}
413#endif /* CONFIG_X86_64 */
414
415/**
416 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
417 * @mm: the probed address space.
418 * @arch_uprobe: the probepoint information.
419 * @addr: virtual address at which to install the probepoint
420 * Return 0 on success or a -ve number on error.
421 */
422int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
423{
424 int ret;
425 struct insn insn;
426
427 auprobe->fixups = 0;
428 ret = validate_insn_bits(auprobe, mm, &insn);
429 if (ret != 0)
430 return ret;
431
432 handle_riprel_insn(auprobe, mm, &insn);
433 prepare_fixups(auprobe, &insn);
434
435 return 0;
436}
437
438#ifdef CONFIG_X86_64
439/*
440 * If we're emulating a rip-relative instruction, save the contents
441 * of the scratch register and store the target address in that register.
442 */
443static void
444pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs,
445 struct arch_uprobe_task *autask)
446{
447 if (auprobe->fixups & UPROBE_FIX_RIP_AX) {
448 autask->saved_scratch_register = regs->ax;
449 regs->ax = current->utask->vaddr;
450 regs->ax += auprobe->rip_rela_target_address;
451 } else if (auprobe->fixups & UPROBE_FIX_RIP_CX) {
452 autask->saved_scratch_register = regs->cx;
453 regs->cx = current->utask->vaddr;
454 regs->cx += auprobe->rip_rela_target_address;
455 }
456}
457#else
458static void
459pre_xol_rip_insn(struct arch_uprobe *auprobe, struct pt_regs *regs,
460 struct arch_uprobe_task *autask)
461{
462 /* No RIP-relative addressing on 32-bit */
463}
464#endif
465
466/*
467 * arch_uprobe_pre_xol - prepare to execute out of line.
468 * @auprobe: the probepoint information.
469 * @regs: reflects the saved user state of current task.
470 */
471int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
472{
473 struct arch_uprobe_task *autask;
474
475 autask = ¤t->utask->autask;
476 autask->saved_trap_nr = current->thread.trap_nr;
477 current->thread.trap_nr = UPROBE_TRAP_NR;
478 regs->ip = current->utask->xol_vaddr;
479 pre_xol_rip_insn(auprobe, regs, autask);
480
481 autask->saved_tf = !!(regs->flags & X86_EFLAGS_TF);
482 regs->flags |= X86_EFLAGS_TF;
483 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP))
484 set_task_blockstep(current, false);
485
486 return 0;
487}
488
489/*
490 * This function is called by arch_uprobe_post_xol() to adjust the return
491 * address pushed by a call instruction executed out of line.
492 */
493static int adjust_ret_addr(unsigned long sp, long correction)
494{
495 int rasize, ncopied;
496 long ra = 0;
497
498 if (is_ia32_task())
499 rasize = 4;
500 else
501 rasize = 8;
502
503 ncopied = copy_from_user(&ra, (void __user *)sp, rasize);
504 if (unlikely(ncopied))
505 return -EFAULT;
506
507 ra += correction;
508 ncopied = copy_to_user((void __user *)sp, &ra, rasize);
509 if (unlikely(ncopied))
510 return -EFAULT;
511
512 return 0;
513}
514
515#ifdef CONFIG_X86_64
516static bool is_riprel_insn(struct arch_uprobe *auprobe)
517{
518 return ((auprobe->fixups & (UPROBE_FIX_RIP_AX | UPROBE_FIX_RIP_CX)) != 0);
519}
520
521static void
522handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction)
523{
524 if (is_riprel_insn(auprobe)) {
525 struct arch_uprobe_task *autask;
526
527 autask = ¤t->utask->autask;
528 if (auprobe->fixups & UPROBE_FIX_RIP_AX)
529 regs->ax = autask->saved_scratch_register;
530 else
531 regs->cx = autask->saved_scratch_register;
532
533 /*
534 * The original instruction includes a displacement, and so
535 * is 4 bytes longer than what we've just single-stepped.
536 * Fall through to handle stuff like "jmpq *...(%rip)" and
537 * "callq *...(%rip)".
538 */
539 if (correction)
540 *correction += 4;
541 }
542}
543#else
544static void
545handle_riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs, long *correction)
546{
547 /* No RIP-relative addressing on 32-bit */
548}
549#endif
550
551/*
552 * If xol insn itself traps and generates a signal(Say,
553 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
554 * instruction jumps back to its own address. It is assumed that anything
555 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
556 *
557 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
558 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
559 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
560 */
561bool arch_uprobe_xol_was_trapped(struct task_struct *t)
562{
563 if (t->thread.trap_nr != UPROBE_TRAP_NR)
564 return true;
565
566 return false;
567}
568
569/*
570 * Called after single-stepping. To avoid the SMP problems that can
571 * occur when we temporarily put back the original opcode to
572 * single-step, we single-stepped a copy of the instruction.
573 *
574 * This function prepares to resume execution after the single-step.
575 * We have to fix things up as follows:
576 *
577 * Typically, the new ip is relative to the copied instruction. We need
578 * to make it relative to the original instruction (FIX_IP). Exceptions
579 * are return instructions and absolute or indirect jump or call instructions.
580 *
581 * If the single-stepped instruction was a call, the return address that
582 * is atop the stack is the address following the copied instruction. We
583 * need to make it the address following the original instruction (FIX_CALL).
584 *
585 * If the original instruction was a rip-relative instruction such as
586 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
587 * instruction using a scratch register -- e.g., "movl %edx,(%rax)".
588 * We need to restore the contents of the scratch register and adjust
589 * the ip, keeping in mind that the instruction we executed is 4 bytes
590 * shorter than the original instruction (since we squeezed out the offset
591 * field). (FIX_RIP_AX or FIX_RIP_CX)
592 */
593int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
594{
595 struct uprobe_task *utask;
596 long correction;
597 int result = 0;
598
599 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
600
601 utask = current->utask;
602 current->thread.trap_nr = utask->autask.saved_trap_nr;
603 correction = (long)(utask->vaddr - utask->xol_vaddr);
604 handle_riprel_post_xol(auprobe, regs, &correction);
605 if (auprobe->fixups & UPROBE_FIX_IP)
606 regs->ip += correction;
607
608 if (auprobe->fixups & UPROBE_FIX_CALL)
609 result = adjust_ret_addr(regs->sp, correction);
610
611 /*
612 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP
613 * so we can get an extra SIGTRAP if we do not clear TF. We need
614 * to examine the opcode to make it right.
615 */
616 if (utask->autask.saved_tf)
617 send_sig(SIGTRAP, current, 0);
618 else if (!(auprobe->fixups & UPROBE_FIX_SETF))
619 regs->flags &= ~X86_EFLAGS_TF;
620
621 return result;
622}
623
624/* callback routine for handling exceptions. */
625int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
626{
627 struct die_args *args = data;
628 struct pt_regs *regs = args->regs;
629 int ret = NOTIFY_DONE;
630
631 /* We are only interested in userspace traps */
632 if (regs && !user_mode_vm(regs))
633 return NOTIFY_DONE;
634
635 switch (val) {
636 case DIE_INT3:
637 if (uprobe_pre_sstep_notifier(regs))
638 ret = NOTIFY_STOP;
639
640 break;
641
642 case DIE_DEBUG:
643 if (uprobe_post_sstep_notifier(regs))
644 ret = NOTIFY_STOP;
645
646 default:
647 break;
648 }
649
650 return ret;
651}
652
653/*
654 * This function gets called when XOL instruction either gets trapped or
655 * the thread has a fatal signal, so reset the instruction pointer to its
656 * probed address.
657 */
658void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
659{
660 struct uprobe_task *utask = current->utask;
661
662 current->thread.trap_nr = utask->autask.saved_trap_nr;
663 handle_riprel_post_xol(auprobe, regs, NULL);
664 instruction_pointer_set(regs, utask->vaddr);
665
666 /* clear TF if it was set by us in arch_uprobe_pre_xol() */
667 if (!utask->autask.saved_tf)
668 regs->flags &= ~X86_EFLAGS_TF;
669}
670
671/*
672 * Skip these instructions as per the currently known x86 ISA.
673 * rep=0x66*; nop=0x90
674 */
675static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
676{
677 int i;
678
679 for (i = 0; i < MAX_UINSN_BYTES; i++) {
680 if (auprobe->insn[i] == 0x66)
681 continue;
682
683 if (auprobe->insn[i] == 0x90) {
684 regs->ip += i + 1;
685 return true;
686 }
687
688 break;
689 }
690 return false;
691}
692
693bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
694{
695 bool ret = __skip_sstep(auprobe, regs);
696 if (ret && (regs->flags & X86_EFLAGS_TF))
697 send_sig(SIGTRAP, current, 0);
698 return ret;
699}
700
701unsigned long
702arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
703{
704 int rasize, ncopied;
705 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
706
707 rasize = is_ia32_task() ? 4 : 8;
708 ncopied = copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize);
709 if (unlikely(ncopied))
710 return -1;
711
712 /* check whether address has been already hijacked */
713 if (orig_ret_vaddr == trampoline_vaddr)
714 return orig_ret_vaddr;
715
716 ncopied = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
717 if (likely(!ncopied))
718 return orig_ret_vaddr;
719
720 if (ncopied != rasize) {
721 pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, "
722 "%%ip=%#lx\n", current->pid, regs->sp, regs->ip);
723
724 force_sig_info(SIGSEGV, SEND_SIG_FORCED, current);
725 }
726
727 return -1;
728}