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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * S390 version
4 * Copyright IBM Corp. 1999
5 * Author(s): Hartmut Penner (hp@de.ibm.com),
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/processor.h"
9 * Copyright (C) 1994, Linus Torvalds
10 */
11
12#ifndef __ASM_S390_PROCESSOR_H
13#define __ASM_S390_PROCESSOR_H
14
15#include <linux/bits.h>
16
17#define CIF_NOHZ_DELAY 2 /* delay HZ disable for a tick */
18#define CIF_FPU 3 /* restore FPU registers */
19#define CIF_ENABLED_WAIT 5 /* in enabled wait state */
20#define CIF_MCCK_GUEST 6 /* machine check happening in guest */
21#define CIF_DEDICATED_CPU 7 /* this CPU is dedicated */
22
23#define _CIF_NOHZ_DELAY BIT(CIF_NOHZ_DELAY)
24#define _CIF_FPU BIT(CIF_FPU)
25#define _CIF_ENABLED_WAIT BIT(CIF_ENABLED_WAIT)
26#define _CIF_MCCK_GUEST BIT(CIF_MCCK_GUEST)
27#define _CIF_DEDICATED_CPU BIT(CIF_DEDICATED_CPU)
28
29#define RESTART_FLAG_CTLREGS _AC(1 << 0, U)
30
31#ifndef __ASSEMBLY__
32
33#include <linux/cpumask.h>
34#include <linux/linkage.h>
35#include <linux/irqflags.h>
36#include <asm/cpu.h>
37#include <asm/page.h>
38#include <asm/ptrace.h>
39#include <asm/setup.h>
40#include <asm/runtime_instr.h>
41#include <asm/fpu/types.h>
42#include <asm/fpu/internal.h>
43#include <asm/irqflags.h>
44
45typedef long (*sys_call_ptr_t)(struct pt_regs *regs);
46
47static inline void set_cpu_flag(int flag)
48{
49 S390_lowcore.cpu_flags |= (1UL << flag);
50}
51
52static inline void clear_cpu_flag(int flag)
53{
54 S390_lowcore.cpu_flags &= ~(1UL << flag);
55}
56
57static inline int test_cpu_flag(int flag)
58{
59 return !!(S390_lowcore.cpu_flags & (1UL << flag));
60}
61
62/*
63 * Test CIF flag of another CPU. The caller needs to ensure that
64 * CPU hotplug can not happen, e.g. by disabling preemption.
65 */
66static inline int test_cpu_flag_of(int flag, int cpu)
67{
68 struct lowcore *lc = lowcore_ptr[cpu];
69 return !!(lc->cpu_flags & (1UL << flag));
70}
71
72#define arch_needs_cpu() test_cpu_flag(CIF_NOHZ_DELAY)
73
74static inline void get_cpu_id(struct cpuid *ptr)
75{
76 asm volatile("stidp %0" : "=Q" (*ptr));
77}
78
79void s390_adjust_jiffies(void);
80void s390_update_cpu_mhz(void);
81void cpu_detect_mhz_feature(void);
82
83extern const struct seq_operations cpuinfo_op;
84extern void execve_tail(void);
85extern void __bpon(void);
86unsigned long vdso_size(void);
87
88/*
89 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
90 */
91
92#define TASK_SIZE (test_thread_flag(TIF_31BIT) ? \
93 _REGION3_SIZE : TASK_SIZE_MAX)
94#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
95 (_REGION3_SIZE >> 1) : (_REGION2_SIZE >> 1))
96#define TASK_SIZE_MAX (-PAGE_SIZE)
97
98#define VDSO_BASE (STACK_TOP + PAGE_SIZE)
99#define VDSO_LIMIT (test_thread_flag(TIF_31BIT) ? _REGION3_SIZE : _REGION2_SIZE)
100#define STACK_TOP (VDSO_LIMIT - vdso_size() - PAGE_SIZE)
101#define STACK_TOP_MAX (_REGION2_SIZE - vdso_size() - PAGE_SIZE)
102
103#define HAVE_ARCH_PICK_MMAP_LAYOUT
104
105/*
106 * Thread structure
107 */
108struct thread_struct {
109 unsigned int acrs[NUM_ACRS];
110 unsigned long ksp; /* kernel stack pointer */
111 unsigned long user_timer; /* task cputime in user space */
112 unsigned long guest_timer; /* task cputime in kvm guest */
113 unsigned long system_timer; /* task cputime in kernel space */
114 unsigned long hardirq_timer; /* task cputime in hardirq context */
115 unsigned long softirq_timer; /* task cputime in softirq context */
116 const sys_call_ptr_t *sys_call_table; /* system call table address */
117 unsigned long gmap_addr; /* address of last gmap fault. */
118 unsigned int gmap_write_flag; /* gmap fault write indication */
119 unsigned int gmap_int_code; /* int code of last gmap fault */
120 unsigned int gmap_pfault; /* signal of a pending guest pfault */
121
122 /* Per-thread information related to debugging */
123 struct per_regs per_user; /* User specified PER registers */
124 struct per_event per_event; /* Cause of the last PER trap */
125 unsigned long per_flags; /* Flags to control debug behavior */
126 unsigned int system_call; /* system call number in signal */
127 unsigned long last_break; /* last breaking-event-address. */
128 /* pfault_wait is used to block the process on a pfault event */
129 unsigned long pfault_wait;
130 struct list_head list;
131 /* cpu runtime instrumentation */
132 struct runtime_instr_cb *ri_cb;
133 struct gs_cb *gs_cb; /* Current guarded storage cb */
134 struct gs_cb *gs_bc_cb; /* Broadcast guarded storage cb */
135 struct pgm_tdb trap_tdb; /* Transaction abort diagnose block */
136 /*
137 * Warning: 'fpu' is dynamically-sized. It *MUST* be at
138 * the end.
139 */
140 struct fpu fpu; /* FP and VX register save area */
141};
142
143/* Flag to disable transactions. */
144#define PER_FLAG_NO_TE 1UL
145/* Flag to enable random transaction aborts. */
146#define PER_FLAG_TE_ABORT_RAND 2UL
147/* Flag to specify random transaction abort mode:
148 * - abort each transaction at a random instruction before TEND if set.
149 * - abort random transactions at a random instruction if cleared.
150 */
151#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
152
153typedef struct thread_struct thread_struct;
154
155#define ARCH_MIN_TASKALIGN 8
156
157#define INIT_THREAD { \
158 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
159 .fpu.regs = (void *) init_task.thread.fpu.fprs, \
160 .last_break = 1, \
161}
162
163/*
164 * Do necessary setup to start up a new thread.
165 */
166#define start_thread(regs, new_psw, new_stackp) do { \
167 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
168 regs->psw.addr = new_psw; \
169 regs->gprs[15] = new_stackp; \
170 execve_tail(); \
171} while (0)
172
173#define start_thread31(regs, new_psw, new_stackp) do { \
174 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
175 regs->psw.addr = new_psw; \
176 regs->gprs[15] = new_stackp; \
177 execve_tail(); \
178} while (0)
179
180/* Forward declaration, a strange C thing */
181struct task_struct;
182struct mm_struct;
183struct seq_file;
184struct pt_regs;
185
186void show_registers(struct pt_regs *regs);
187void show_cacheinfo(struct seq_file *m);
188
189/* Free guarded storage control block */
190void guarded_storage_release(struct task_struct *tsk);
191void gs_load_bc_cb(struct pt_regs *regs);
192
193unsigned long __get_wchan(struct task_struct *p);
194#define task_pt_regs(tsk) ((struct pt_regs *) \
195 (task_stack_page(tsk) + THREAD_SIZE) - 1)
196#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
197#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
198
199/* Has task runtime instrumentation enabled ? */
200#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
201
202/* avoid using global register due to gcc bug in versions < 8.4 */
203#define current_stack_pointer (__current_stack_pointer())
204
205static __always_inline unsigned long __current_stack_pointer(void)
206{
207 unsigned long sp;
208
209 asm volatile("lgr %0,15" : "=d" (sp));
210 return sp;
211}
212
213static __always_inline unsigned short stap(void)
214{
215 unsigned short cpu_address;
216
217 asm volatile("stap %0" : "=Q" (cpu_address));
218 return cpu_address;
219}
220
221#define cpu_relax() barrier()
222
223#define ECAG_CACHE_ATTRIBUTE 0
224#define ECAG_CPU_ATTRIBUTE 1
225
226static inline unsigned long __ecag(unsigned int asi, unsigned char parm)
227{
228 unsigned long val;
229
230 asm volatile("ecag %0,0,0(%1)" : "=d" (val) : "a" (asi << 8 | parm));
231 return val;
232}
233
234static inline void psw_set_key(unsigned int key)
235{
236 asm volatile("spka 0(%0)" : : "d" (key));
237}
238
239/*
240 * Set PSW to specified value.
241 */
242static inline void __load_psw(psw_t psw)
243{
244 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
245}
246
247/*
248 * Set PSW mask to specified value, while leaving the
249 * PSW addr pointing to the next instruction.
250 */
251static __always_inline void __load_psw_mask(unsigned long mask)
252{
253 unsigned long addr;
254 psw_t psw;
255
256 psw.mask = mask;
257
258 asm volatile(
259 " larl %0,1f\n"
260 " stg %0,%1\n"
261 " lpswe %2\n"
262 "1:"
263 : "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");
264}
265
266/*
267 * Extract current PSW mask
268 */
269static inline unsigned long __extract_psw(void)
270{
271 unsigned int reg1, reg2;
272
273 asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2));
274 return (((unsigned long) reg1) << 32) | ((unsigned long) reg2);
275}
276
277static inline void local_mcck_enable(void)
278{
279 __load_psw_mask(__extract_psw() | PSW_MASK_MCHECK);
280}
281
282static inline void local_mcck_disable(void)
283{
284 __load_psw_mask(__extract_psw() & ~PSW_MASK_MCHECK);
285}
286
287/*
288 * Rewind PSW instruction address by specified number of bytes.
289 */
290static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
291{
292 unsigned long mask;
293
294 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
295 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
296 (1UL << 24) - 1;
297 return (psw.addr - ilc) & mask;
298}
299
300/*
301 * Function to drop a processor into disabled wait state
302 */
303static __always_inline void __noreturn disabled_wait(void)
304{
305 psw_t psw;
306
307 psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
308 psw.addr = _THIS_IP_;
309 __load_psw(psw);
310 while (1);
311}
312
313#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
314
315extern int s390_isolate_bp(void);
316extern int s390_isolate_bp_guest(void);
317
318static __always_inline bool regs_irqs_disabled(struct pt_regs *regs)
319{
320 return arch_irqs_disabled_flags(regs->psw.mask);
321}
322
323#endif /* __ASSEMBLY__ */
324
325#endif /* __ASM_S390_PROCESSOR_H */
1/*
2 * S390 version
3 * Copyright IBM Corp. 1999
4 * Author(s): Hartmut Penner (hp@de.ibm.com),
5 * Martin Schwidefsky (schwidefsky@de.ibm.com)
6 *
7 * Derived from "include/asm-i386/processor.h"
8 * Copyright (C) 1994, Linus Torvalds
9 */
10
11#ifndef __ASM_S390_PROCESSOR_H
12#define __ASM_S390_PROCESSOR_H
13
14#ifndef __ASSEMBLY__
15
16#include <linux/linkage.h>
17#include <linux/irqflags.h>
18#include <asm/cpu.h>
19#include <asm/page.h>
20#include <asm/ptrace.h>
21#include <asm/setup.h>
22#include <asm/runtime_instr.h>
23
24/*
25 * Default implementation of macro that returns current
26 * instruction pointer ("program counter").
27 */
28#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
29
30static inline void get_cpu_id(struct cpuid *ptr)
31{
32 asm volatile("stidp %0" : "=Q" (*ptr));
33}
34
35extern void s390_adjust_jiffies(void);
36extern const struct seq_operations cpuinfo_op;
37extern int sysctl_ieee_emulation_warnings;
38extern void execve_tail(void);
39
40/*
41 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
42 */
43#ifndef CONFIG_64BIT
44
45#define TASK_SIZE (1UL << 31)
46#define TASK_MAX_SIZE (1UL << 31)
47#define TASK_UNMAPPED_BASE (1UL << 30)
48
49#else /* CONFIG_64BIT */
50
51#define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit)
52#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \
53 (1UL << 30) : (1UL << 41))
54#define TASK_SIZE TASK_SIZE_OF(current)
55#define TASK_MAX_SIZE (1UL << 53)
56
57#endif /* CONFIG_64BIT */
58
59#ifndef CONFIG_64BIT
60#define STACK_TOP (1UL << 31)
61#define STACK_TOP_MAX (1UL << 31)
62#else /* CONFIG_64BIT */
63#define STACK_TOP (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
64#define STACK_TOP_MAX (1UL << 42)
65#endif /* CONFIG_64BIT */
66
67#define HAVE_ARCH_PICK_MMAP_LAYOUT
68
69typedef struct {
70 __u32 ar4;
71} mm_segment_t;
72
73/*
74 * Thread structure
75 */
76struct thread_struct {
77 s390_fp_regs fp_regs;
78 unsigned int acrs[NUM_ACRS];
79 unsigned long ksp; /* kernel stack pointer */
80 mm_segment_t mm_segment;
81 unsigned long gmap_addr; /* address of last gmap fault. */
82 unsigned int gmap_pfault; /* signal of a pending guest pfault */
83 struct per_regs per_user; /* User specified PER registers */
84 struct per_event per_event; /* Cause of the last PER trap */
85 unsigned long per_flags; /* Flags to control debug behavior */
86 /* pfault_wait is used to block the process on a pfault event */
87 unsigned long pfault_wait;
88 struct list_head list;
89 /* cpu runtime instrumentation */
90 struct runtime_instr_cb *ri_cb;
91 int ri_signum;
92#ifdef CONFIG_64BIT
93 unsigned char trap_tdb[256]; /* Transaction abort diagnose block */
94#endif
95};
96
97/* Flag to disable transactions. */
98#define PER_FLAG_NO_TE 1UL
99/* Flag to enable random transaction aborts. */
100#define PER_FLAG_TE_ABORT_RAND 2UL
101/* Flag to specify random transaction abort mode:
102 * - abort each transaction at a random instruction before TEND if set.
103 * - abort random transactions at a random instruction if cleared.
104 */
105#define PER_FLAG_TE_ABORT_RAND_TEND 4UL
106
107typedef struct thread_struct thread_struct;
108
109/*
110 * Stack layout of a C stack frame.
111 */
112#ifndef __PACK_STACK
113struct stack_frame {
114 unsigned long back_chain;
115 unsigned long empty1[5];
116 unsigned long gprs[10];
117 unsigned int empty2[8];
118};
119#else
120struct stack_frame {
121 unsigned long empty1[5];
122 unsigned int empty2[8];
123 unsigned long gprs[10];
124 unsigned long back_chain;
125};
126#endif
127
128#define ARCH_MIN_TASKALIGN 8
129
130#define INIT_THREAD { \
131 .ksp = sizeof(init_stack) + (unsigned long) &init_stack, \
132}
133
134/*
135 * Do necessary setup to start up a new thread.
136 */
137#define start_thread(regs, new_psw, new_stackp) do { \
138 regs->psw.mask = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA; \
139 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
140 regs->gprs[15] = new_stackp; \
141 execve_tail(); \
142} while (0)
143
144#define start_thread31(regs, new_psw, new_stackp) do { \
145 regs->psw.mask = PSW_USER_BITS | PSW_MASK_BA; \
146 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
147 regs->gprs[15] = new_stackp; \
148 crst_table_downgrade(current->mm, 1UL << 31); \
149 execve_tail(); \
150} while (0)
151
152/* Forward declaration, a strange C thing */
153struct task_struct;
154struct mm_struct;
155struct seq_file;
156
157#ifdef CONFIG_64BIT
158extern void show_cacheinfo(struct seq_file *m);
159#else
160static inline void show_cacheinfo(struct seq_file *m) { }
161#endif
162
163/* Free all resources held by a thread. */
164extern void release_thread(struct task_struct *);
165
166/*
167 * Return saved PC of a blocked thread.
168 */
169extern unsigned long thread_saved_pc(struct task_struct *t);
170
171unsigned long get_wchan(struct task_struct *p);
172#define task_pt_regs(tsk) ((struct pt_regs *) \
173 (task_stack_page(tsk) + THREAD_SIZE) - 1)
174#define KSTK_EIP(tsk) (task_pt_regs(tsk)->psw.addr)
175#define KSTK_ESP(tsk) (task_pt_regs(tsk)->gprs[15])
176
177/* Has task runtime instrumentation enabled ? */
178#define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
179
180static inline unsigned short stap(void)
181{
182 unsigned short cpu_address;
183
184 asm volatile("stap %0" : "=m" (cpu_address));
185 return cpu_address;
186}
187
188/*
189 * Give up the time slice of the virtual PU.
190 */
191static inline void cpu_relax(void)
192{
193 if (MACHINE_HAS_DIAG44)
194 asm volatile("diag 0,0,68");
195 barrier();
196}
197
198#define arch_mutex_cpu_relax() barrier()
199
200static inline void psw_set_key(unsigned int key)
201{
202 asm volatile("spka 0(%0)" : : "d" (key));
203}
204
205/*
206 * Set PSW to specified value.
207 */
208static inline void __load_psw(psw_t psw)
209{
210#ifndef CONFIG_64BIT
211 asm volatile("lpsw %0" : : "Q" (psw) : "cc");
212#else
213 asm volatile("lpswe %0" : : "Q" (psw) : "cc");
214#endif
215}
216
217/*
218 * Set PSW mask to specified value, while leaving the
219 * PSW addr pointing to the next instruction.
220 */
221static inline void __load_psw_mask (unsigned long mask)
222{
223 unsigned long addr;
224 psw_t psw;
225
226 psw.mask = mask;
227
228#ifndef CONFIG_64BIT
229 asm volatile(
230 " basr %0,0\n"
231 "0: ahi %0,1f-0b\n"
232 " st %0,%O1+4(%R1)\n"
233 " lpsw %1\n"
234 "1:"
235 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
236#else /* CONFIG_64BIT */
237 asm volatile(
238 " larl %0,1f\n"
239 " stg %0,%O1+8(%R1)\n"
240 " lpswe %1\n"
241 "1:"
242 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
243#endif /* CONFIG_64BIT */
244}
245
246/*
247 * Rewind PSW instruction address by specified number of bytes.
248 */
249static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
250{
251#ifndef CONFIG_64BIT
252 if (psw.addr & PSW_ADDR_AMODE)
253 /* 31 bit mode */
254 return (psw.addr - ilc) | PSW_ADDR_AMODE;
255 /* 24 bit mode */
256 return (psw.addr - ilc) & ((1UL << 24) - 1);
257#else
258 unsigned long mask;
259
260 mask = (psw.mask & PSW_MASK_EA) ? -1UL :
261 (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
262 (1UL << 24) - 1;
263 return (psw.addr - ilc) & mask;
264#endif
265}
266
267/*
268 * Function to drop a processor into disabled wait state
269 */
270static inline void __noreturn disabled_wait(unsigned long code)
271{
272 unsigned long ctl_buf;
273 psw_t dw_psw;
274
275 dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
276 dw_psw.addr = code;
277 /*
278 * Store status and then load disabled wait psw,
279 * the processor is dead afterwards
280 */
281#ifndef CONFIG_64BIT
282 asm volatile(
283 " stctl 0,0,0(%2)\n"
284 " ni 0(%2),0xef\n" /* switch off protection */
285 " lctl 0,0,0(%2)\n"
286 " stpt 0xd8\n" /* store timer */
287 " stckc 0xe0\n" /* store clock comparator */
288 " stpx 0x108\n" /* store prefix register */
289 " stam 0,15,0x120\n" /* store access registers */
290 " std 0,0x160\n" /* store f0 */
291 " std 2,0x168\n" /* store f2 */
292 " std 4,0x170\n" /* store f4 */
293 " std 6,0x178\n" /* store f6 */
294 " stm 0,15,0x180\n" /* store general registers */
295 " stctl 0,15,0x1c0\n" /* store control registers */
296 " oi 0x1c0,0x10\n" /* fake protection bit */
297 " lpsw 0(%1)"
298 : "=m" (ctl_buf)
299 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
300#else /* CONFIG_64BIT */
301 asm volatile(
302 " stctg 0,0,0(%2)\n"
303 " ni 4(%2),0xef\n" /* switch off protection */
304 " lctlg 0,0,0(%2)\n"
305 " lghi 1,0x1000\n"
306 " stpt 0x328(1)\n" /* store timer */
307 " stckc 0x330(1)\n" /* store clock comparator */
308 " stpx 0x318(1)\n" /* store prefix register */
309 " stam 0,15,0x340(1)\n"/* store access registers */
310 " stfpc 0x31c(1)\n" /* store fpu control */
311 " std 0,0x200(1)\n" /* store f0 */
312 " std 1,0x208(1)\n" /* store f1 */
313 " std 2,0x210(1)\n" /* store f2 */
314 " std 3,0x218(1)\n" /* store f3 */
315 " std 4,0x220(1)\n" /* store f4 */
316 " std 5,0x228(1)\n" /* store f5 */
317 " std 6,0x230(1)\n" /* store f6 */
318 " std 7,0x238(1)\n" /* store f7 */
319 " std 8,0x240(1)\n" /* store f8 */
320 " std 9,0x248(1)\n" /* store f9 */
321 " std 10,0x250(1)\n" /* store f10 */
322 " std 11,0x258(1)\n" /* store f11 */
323 " std 12,0x260(1)\n" /* store f12 */
324 " std 13,0x268(1)\n" /* store f13 */
325 " std 14,0x270(1)\n" /* store f14 */
326 " std 15,0x278(1)\n" /* store f15 */
327 " stmg 0,15,0x280(1)\n"/* store general registers */
328 " stctg 0,15,0x380(1)\n"/* store control registers */
329 " oi 0x384(1),0x10\n"/* fake protection bit */
330 " lpswe 0(%1)"
331 : "=m" (ctl_buf)
332 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
333#endif /* CONFIG_64BIT */
334 while (1);
335}
336
337/*
338 * Use to set psw mask except for the first byte which
339 * won't be changed by this function.
340 */
341static inline void
342__set_psw_mask(unsigned long mask)
343{
344 __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
345}
346
347#define local_mcck_enable() \
348 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
349#define local_mcck_disable() \
350 __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
351
352/*
353 * Basic Machine Check/Program Check Handler.
354 */
355
356extern void s390_base_mcck_handler(void);
357extern void s390_base_pgm_handler(void);
358extern void s390_base_ext_handler(void);
359
360extern void (*s390_base_mcck_handler_fn)(void);
361extern void (*s390_base_pgm_handler_fn)(void);
362extern void (*s390_base_ext_handler_fn)(void);
363
364#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
365
366extern int memcpy_real(void *, void *, size_t);
367extern void memcpy_absolute(void *, void *, size_t);
368
369#define mem_assign_absolute(dest, val) { \
370 __typeof__(dest) __tmp = (val); \
371 \
372 BUILD_BUG_ON(sizeof(__tmp) != sizeof(val)); \
373 memcpy_absolute(&(dest), &__tmp, sizeof(__tmp)); \
374}
375
376/*
377 * Helper macro for exception table entries
378 */
379#define EX_TABLE(_fault, _target) \
380 ".section __ex_table,\"a\"\n" \
381 ".align 4\n" \
382 ".long (" #_fault ") - .\n" \
383 ".long (" #_target ") - .\n" \
384 ".previous\n"
385
386#else /* __ASSEMBLY__ */
387
388#define EX_TABLE(_fault, _target) \
389 .section __ex_table,"a" ; \
390 .align 4 ; \
391 .long (_fault) - . ; \
392 .long (_target) - . ; \
393 .previous
394
395#endif /* __ASSEMBLY__ */
396
397#endif /* __ASM_S390_PROCESSOR_H */