Loading...
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16enum fields {
17 RS = 0x001,
18 RT = 0x002,
19 RD = 0x004,
20 RE = 0x008,
21 SIMM = 0x010,
22 UIMM = 0x020,
23 BIMM = 0x040,
24 JIMM = 0x080,
25 FUNC = 0x100,
26 SET = 0x200,
27 SCIMM = 0x400,
28 SIMM9 = 0x800,
29};
30
31#define OP_MASK 0x3f
32#define OP_SH 26
33#define RD_MASK 0x1f
34#define RD_SH 11
35#define RE_MASK 0x1f
36#define RE_SH 6
37#define IMM_MASK 0xffff
38#define IMM_SH 0
39#define JIMM_MASK 0x3ffffff
40#define JIMM_SH 0
41#define FUNC_MASK 0x3f
42#define FUNC_SH 0
43#define SET_MASK 0x7
44#define SET_SH 0
45#define SIMM9_SH 7
46#define SIMM9_MASK 0x1ff
47
48enum opcode {
49 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
50 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
51 insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
52 insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
53 insn_ddivu_r6, insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu,
54 insn_divu_r6, insn_dmfc0, insn_dmodu, insn_dmtc0, insn_dmultu,
55 insn_dmulu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd, insn_dsll,
56 insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav, insn_dsrl,
57 insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext, insn_ins,
58 insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu, insn_ld,
59 insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
60 insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
61 insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
62 insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor,
63 insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
64 insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
65 insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
66 insn_srav, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,
67 insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,
68 insn_wsbh, insn_xor, insn_xori, insn_yield,
69 insn_invalid /* insn_invalid must be last */
70};
71
72struct insn {
73 u32 match;
74 enum fields fields;
75};
76
77static inline u32 build_rs(u32 arg)
78{
79 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
80
81 return (arg & RS_MASK) << RS_SH;
82}
83
84static inline u32 build_rt(u32 arg)
85{
86 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
87
88 return (arg & RT_MASK) << RT_SH;
89}
90
91static inline u32 build_rd(u32 arg)
92{
93 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
94
95 return (arg & RD_MASK) << RD_SH;
96}
97
98static inline u32 build_re(u32 arg)
99{
100 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
101
102 return (arg & RE_MASK) << RE_SH;
103}
104
105static inline u32 build_simm(s32 arg)
106{
107 WARN(arg > 0x7fff || arg < -0x8000,
108 KERN_WARNING "Micro-assembler field overflow\n");
109
110 return arg & 0xffff;
111}
112
113static inline u32 build_uimm(u32 arg)
114{
115 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
116
117 return arg & IMM_MASK;
118}
119
120static inline u32 build_scimm(u32 arg)
121{
122 WARN(arg & ~SCIMM_MASK,
123 KERN_WARNING "Micro-assembler field overflow\n");
124
125 return (arg & SCIMM_MASK) << SCIMM_SH;
126}
127
128static inline u32 build_scimm9(s32 arg)
129{
130 WARN((arg > 0xff || arg < -0x100),
131 KERN_WARNING "Micro-assembler field overflow\n");
132
133 return (arg & SIMM9_MASK) << SIMM9_SH;
134}
135
136static inline u32 build_func(u32 arg)
137{
138 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
139
140 return arg & FUNC_MASK;
141}
142
143static inline u32 build_set(u32 arg)
144{
145 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
146
147 return arg & SET_MASK;
148}
149
150static void build_insn(u32 **buf, enum opcode opc, ...);
151
152#define I_u1u2u3(op) \
153Ip_u1u2u3(op) \
154{ \
155 build_insn(buf, insn##op, a, b, c); \
156} \
157UASM_EXPORT_SYMBOL(uasm_i##op);
158
159#define I_s3s1s2(op) \
160Ip_s3s1s2(op) \
161{ \
162 build_insn(buf, insn##op, b, c, a); \
163} \
164UASM_EXPORT_SYMBOL(uasm_i##op);
165
166#define I_u2u1u3(op) \
167Ip_u2u1u3(op) \
168{ \
169 build_insn(buf, insn##op, b, a, c); \
170} \
171UASM_EXPORT_SYMBOL(uasm_i##op);
172
173#define I_u3u2u1(op) \
174Ip_u3u2u1(op) \
175{ \
176 build_insn(buf, insn##op, c, b, a); \
177} \
178UASM_EXPORT_SYMBOL(uasm_i##op);
179
180#define I_u3u1u2(op) \
181Ip_u3u1u2(op) \
182{ \
183 build_insn(buf, insn##op, b, c, a); \
184} \
185UASM_EXPORT_SYMBOL(uasm_i##op);
186
187#define I_u1u2s3(op) \
188Ip_u1u2s3(op) \
189{ \
190 build_insn(buf, insn##op, a, b, c); \
191} \
192UASM_EXPORT_SYMBOL(uasm_i##op);
193
194#define I_u2s3u1(op) \
195Ip_u2s3u1(op) \
196{ \
197 build_insn(buf, insn##op, c, a, b); \
198} \
199UASM_EXPORT_SYMBOL(uasm_i##op);
200
201#define I_u2u1s3(op) \
202Ip_u2u1s3(op) \
203{ \
204 build_insn(buf, insn##op, b, a, c); \
205} \
206UASM_EXPORT_SYMBOL(uasm_i##op);
207
208#define I_u2u1msbu3(op) \
209Ip_u2u1msbu3(op) \
210{ \
211 build_insn(buf, insn##op, b, a, c+d-1, c); \
212} \
213UASM_EXPORT_SYMBOL(uasm_i##op);
214
215#define I_u2u1msb32u3(op) \
216Ip_u2u1msbu3(op) \
217{ \
218 build_insn(buf, insn##op, b, a, c+d-33, c); \
219} \
220UASM_EXPORT_SYMBOL(uasm_i##op);
221
222#define I_u2u1msb32msb3(op) \
223Ip_u2u1msbu3(op) \
224{ \
225 build_insn(buf, insn##op, b, a, c+d-33, c-32); \
226} \
227UASM_EXPORT_SYMBOL(uasm_i##op);
228
229#define I_u2u1msbdu3(op) \
230Ip_u2u1msbu3(op) \
231{ \
232 build_insn(buf, insn##op, b, a, d-1, c); \
233} \
234UASM_EXPORT_SYMBOL(uasm_i##op);
235
236#define I_u1u2(op) \
237Ip_u1u2(op) \
238{ \
239 build_insn(buf, insn##op, a, b); \
240} \
241UASM_EXPORT_SYMBOL(uasm_i##op);
242
243#define I_u2u1(op) \
244Ip_u1u2(op) \
245{ \
246 build_insn(buf, insn##op, b, a); \
247} \
248UASM_EXPORT_SYMBOL(uasm_i##op);
249
250#define I_u1s2(op) \
251Ip_u1s2(op) \
252{ \
253 build_insn(buf, insn##op, a, b); \
254} \
255UASM_EXPORT_SYMBOL(uasm_i##op);
256
257#define I_u1(op) \
258Ip_u1(op) \
259{ \
260 build_insn(buf, insn##op, a); \
261} \
262UASM_EXPORT_SYMBOL(uasm_i##op);
263
264#define I_0(op) \
265Ip_0(op) \
266{ \
267 build_insn(buf, insn##op); \
268} \
269UASM_EXPORT_SYMBOL(uasm_i##op);
270
271I_u2u1s3(_addiu)
272I_u3u1u2(_addu)
273I_u2u1u3(_andi)
274I_u3u1u2(_and)
275I_u1u2s3(_beq)
276I_u1u2s3(_beql)
277I_u1s2(_bgez)
278I_u1s2(_bgezl)
279I_u1s2(_bgtz)
280I_u1s2(_blez)
281I_u1s2(_bltz)
282I_u1s2(_bltzl)
283I_u1u2s3(_bne)
284I_u1(_break)
285I_u2s3u1(_cache)
286I_u1u2(_cfc1)
287I_u2u1(_cfcmsa)
288I_u1u2(_ctc1)
289I_u2u1(_ctcmsa)
290I_u1u2(_ddivu)
291I_u3u1u2(_ddivu_r6)
292I_u1u2u3(_dmfc0)
293I_u3u1u2(_dmodu)
294I_u1u2u3(_dmtc0)
295I_u1u2(_dmultu)
296I_u3u1u2(_dmulu)
297I_u2u1s3(_daddiu)
298I_u3u1u2(_daddu)
299I_u1(_di);
300I_u1u2(_divu)
301I_u3u1u2(_divu_r6)
302I_u2u1(_dsbh);
303I_u2u1(_dshd);
304I_u2u1u3(_dsll)
305I_u2u1u3(_dsll32)
306I_u3u2u1(_dsllv)
307I_u2u1u3(_dsra)
308I_u2u1u3(_dsra32)
309I_u3u2u1(_dsrav)
310I_u2u1u3(_dsrl)
311I_u2u1u3(_dsrl32)
312I_u3u2u1(_dsrlv)
313I_u2u1u3(_drotr)
314I_u2u1u3(_drotr32)
315I_u3u1u2(_dsubu)
316I_0(_eret)
317I_u2u1msbdu3(_ext)
318I_u2u1msbu3(_ins)
319I_u1(_j)
320I_u1(_jal)
321I_u2u1(_jalr)
322I_u1(_jr)
323I_u2s3u1(_lb)
324I_u2s3u1(_lbu)
325I_u2s3u1(_ld)
326I_u2s3u1(_lh)
327I_u2s3u1(_lhu)
328I_u2s3u1(_ll)
329I_u2s3u1(_lld)
330I_u1s2(_lui)
331I_u2s3u1(_lw)
332I_u2s3u1(_lwu)
333I_u1u2u3(_mfc0)
334I_u1u2u3(_mfhc0)
335I_u3u1u2(_modu)
336I_u3u1u2(_movn)
337I_u3u1u2(_movz)
338I_u1(_mfhi)
339I_u1(_mflo)
340I_u1u2u3(_mtc0)
341I_u1u2u3(_mthc0)
342I_u1(_mthi)
343I_u1(_mtlo)
344I_u3u1u2(_mul)
345I_u1u2(_multu)
346I_u3u1u2(_mulu)
347I_u3u1u2(_muhu)
348I_u3u1u2(_nor)
349I_u3u1u2(_or)
350I_u2u1u3(_ori)
351I_0(_rfe)
352I_u2s3u1(_sb)
353I_u2s3u1(_sc)
354I_u2s3u1(_scd)
355I_u2s3u1(_sd)
356I_u3u1u2(_seleqz)
357I_u3u1u2(_selnez)
358I_u2s3u1(_sh)
359I_u2u1u3(_sll)
360I_u3u2u1(_sllv)
361I_s3s1s2(_slt)
362I_u2u1s3(_slti)
363I_u2u1s3(_sltiu)
364I_u3u1u2(_sltu)
365I_u2u1u3(_sra)
366I_u3u2u1(_srav)
367I_u2u1u3(_srl)
368I_u3u2u1(_srlv)
369I_u2u1u3(_rotr)
370I_u3u1u2(_subu)
371I_u2s3u1(_sw)
372I_u1(_sync)
373I_0(_tlbp)
374I_0(_tlbr)
375I_0(_tlbwi)
376I_0(_tlbwr)
377I_u1(_wait);
378I_u2u1(_wsbh)
379I_u3u1u2(_xor)
380I_u2u1u3(_xori)
381I_u2u1(_yield)
382I_u2u1msbu3(_dins);
383I_u2u1msb32u3(_dinsm);
384I_u2u1msb32msb3(_dinsu);
385I_u1(_syscall);
386I_u1u2s3(_bbit0);
387I_u1u2s3(_bbit1);
388I_u3u1u2(_lwx)
389I_u3u1u2(_ldx)
390I_u1u2(_ldpte)
391I_u2u1u3(_lddir)
392
393#ifdef CONFIG_CPU_CAVIUM_OCTEON
394#include <asm/octeon/octeon.h>
395void uasm_i_pref(u32 **buf, unsigned int a, signed int b,
396 unsigned int c)
397{
398 if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && a <= 24 && a != 5)
399 /*
400 * As per erratum Core-14449, replace prefetches 0-4,
401 * 6-24 with 'pref 28'.
402 */
403 build_insn(buf, insn_pref, c, 28, b);
404 else
405 build_insn(buf, insn_pref, c, a, b);
406}
407UASM_EXPORT_SYMBOL(uasm_i_pref);
408#else
409I_u2s3u1(_pref)
410#endif
411
412/* Handle labels. */
413void uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
414{
415 (*lab)->addr = addr;
416 (*lab)->lab = lid;
417 (*lab)++;
418}
419UASM_EXPORT_SYMBOL(uasm_build_label);
420
421int uasm_in_compat_space_p(long addr)
422{
423 /* Is this address in 32bit compat space? */
424 return addr == (int)addr;
425}
426UASM_EXPORT_SYMBOL(uasm_in_compat_space_p);
427
428static int uasm_rel_highest(long val)
429{
430#ifdef CONFIG_64BIT
431 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
432#else
433 return 0;
434#endif
435}
436
437static int uasm_rel_higher(long val)
438{
439#ifdef CONFIG_64BIT
440 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
441#else
442 return 0;
443#endif
444}
445
446int uasm_rel_hi(long val)
447{
448 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
449}
450UASM_EXPORT_SYMBOL(uasm_rel_hi);
451
452int uasm_rel_lo(long val)
453{
454 return ((val & 0xffff) ^ 0x8000) - 0x8000;
455}
456UASM_EXPORT_SYMBOL(uasm_rel_lo);
457
458void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr)
459{
460 if (!uasm_in_compat_space_p(addr)) {
461 uasm_i_lui(buf, rs, uasm_rel_highest(addr));
462 if (uasm_rel_higher(addr))
463 uasm_i_daddiu(buf, rs, rs, uasm_rel_higher(addr));
464 if (uasm_rel_hi(addr)) {
465 uasm_i_dsll(buf, rs, rs, 16);
466 uasm_i_daddiu(buf, rs, rs,
467 uasm_rel_hi(addr));
468 uasm_i_dsll(buf, rs, rs, 16);
469 } else
470 uasm_i_dsll32(buf, rs, rs, 0);
471 } else
472 uasm_i_lui(buf, rs, uasm_rel_hi(addr));
473}
474UASM_EXPORT_SYMBOL(UASM_i_LA_mostly);
475
476void UASM_i_LA(u32 **buf, unsigned int rs, long addr)
477{
478 UASM_i_LA_mostly(buf, rs, addr);
479 if (uasm_rel_lo(addr)) {
480 if (!uasm_in_compat_space_p(addr))
481 uasm_i_daddiu(buf, rs, rs,
482 uasm_rel_lo(addr));
483 else
484 uasm_i_addiu(buf, rs, rs,
485 uasm_rel_lo(addr));
486 }
487}
488UASM_EXPORT_SYMBOL(UASM_i_LA);
489
490/* Handle relocations. */
491void uasm_r_mips_pc16(struct uasm_reloc **rel, u32 *addr, int lid)
492{
493 (*rel)->addr = addr;
494 (*rel)->type = R_MIPS_PC16;
495 (*rel)->lab = lid;
496 (*rel)++;
497}
498UASM_EXPORT_SYMBOL(uasm_r_mips_pc16);
499
500static inline void __resolve_relocs(struct uasm_reloc *rel,
501 struct uasm_label *lab);
502
503void uasm_resolve_relocs(struct uasm_reloc *rel,
504 struct uasm_label *lab)
505{
506 struct uasm_label *l;
507
508 for (; rel->lab != UASM_LABEL_INVALID; rel++)
509 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
510 if (rel->lab == l->lab)
511 __resolve_relocs(rel, l);
512}
513UASM_EXPORT_SYMBOL(uasm_resolve_relocs);
514
515void uasm_move_relocs(struct uasm_reloc *rel, u32 *first, u32 *end,
516 long off)
517{
518 for (; rel->lab != UASM_LABEL_INVALID; rel++)
519 if (rel->addr >= first && rel->addr < end)
520 rel->addr += off;
521}
522UASM_EXPORT_SYMBOL(uasm_move_relocs);
523
524void uasm_move_labels(struct uasm_label *lab, u32 *first, u32 *end,
525 long off)
526{
527 for (; lab->lab != UASM_LABEL_INVALID; lab++)
528 if (lab->addr >= first && lab->addr < end)
529 lab->addr += off;
530}
531UASM_EXPORT_SYMBOL(uasm_move_labels);
532
533void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
534 u32 *first, u32 *end, u32 *target)
535{
536 long off = (long)(target - first);
537
538 memcpy(target, first, (end - first) * sizeof(u32));
539
540 uasm_move_relocs(rel, first, end, off);
541 uasm_move_labels(lab, first, end, off);
542}
543UASM_EXPORT_SYMBOL(uasm_copy_handler);
544
545int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr)
546{
547 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
548 if (rel->addr == addr
549 && (rel->type == R_MIPS_PC16
550 || rel->type == R_MIPS_26))
551 return 1;
552 }
553
554 return 0;
555}
556UASM_EXPORT_SYMBOL(uasm_insn_has_bdelay);
557
558/* Convenience functions for labeled branches. */
559void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg,
560 int lid)
561{
562 uasm_r_mips_pc16(r, *p, lid);
563 uasm_i_bltz(p, reg, 0);
564}
565UASM_EXPORT_SYMBOL(uasm_il_bltz);
566
567void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid)
568{
569 uasm_r_mips_pc16(r, *p, lid);
570 uasm_i_b(p, 0);
571}
572UASM_EXPORT_SYMBOL(uasm_il_b);
573
574void uasm_il_beq(u32 **p, struct uasm_reloc **r, unsigned int r1,
575 unsigned int r2, int lid)
576{
577 uasm_r_mips_pc16(r, *p, lid);
578 uasm_i_beq(p, r1, r2, 0);
579}
580UASM_EXPORT_SYMBOL(uasm_il_beq);
581
582void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg,
583 int lid)
584{
585 uasm_r_mips_pc16(r, *p, lid);
586 uasm_i_beqz(p, reg, 0);
587}
588UASM_EXPORT_SYMBOL(uasm_il_beqz);
589
590void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg,
591 int lid)
592{
593 uasm_r_mips_pc16(r, *p, lid);
594 uasm_i_beqzl(p, reg, 0);
595}
596UASM_EXPORT_SYMBOL(uasm_il_beqzl);
597
598void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
599 unsigned int reg2, int lid)
600{
601 uasm_r_mips_pc16(r, *p, lid);
602 uasm_i_bne(p, reg1, reg2, 0);
603}
604UASM_EXPORT_SYMBOL(uasm_il_bne);
605
606void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg,
607 int lid)
608{
609 uasm_r_mips_pc16(r, *p, lid);
610 uasm_i_bnez(p, reg, 0);
611}
612UASM_EXPORT_SYMBOL(uasm_il_bnez);
613
614void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg,
615 int lid)
616{
617 uasm_r_mips_pc16(r, *p, lid);
618 uasm_i_bgezl(p, reg, 0);
619}
620UASM_EXPORT_SYMBOL(uasm_il_bgezl);
621
622void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg,
623 int lid)
624{
625 uasm_r_mips_pc16(r, *p, lid);
626 uasm_i_bgez(p, reg, 0);
627}
628UASM_EXPORT_SYMBOL(uasm_il_bgez);
629
630void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
631 unsigned int bit, int lid)
632{
633 uasm_r_mips_pc16(r, *p, lid);
634 uasm_i_bbit0(p, reg, bit, 0);
635}
636UASM_EXPORT_SYMBOL(uasm_il_bbit0);
637
638void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
639 unsigned int bit, int lid)
640{
641 uasm_r_mips_pc16(r, *p, lid);
642 uasm_i_bbit1(p, reg, bit, 0);
643}
644UASM_EXPORT_SYMBOL(uasm_il_bbit1);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16enum fields {
17 RS = 0x001,
18 RT = 0x002,
19 RD = 0x004,
20 RE = 0x008,
21 SIMM = 0x010,
22 UIMM = 0x020,
23 BIMM = 0x040,
24 JIMM = 0x080,
25 FUNC = 0x100,
26 SET = 0x200,
27 SCIMM = 0x400
28};
29
30#define OP_MASK 0x3f
31#define OP_SH 26
32#define RD_MASK 0x1f
33#define RD_SH 11
34#define RE_MASK 0x1f
35#define RE_SH 6
36#define IMM_MASK 0xffff
37#define IMM_SH 0
38#define JIMM_MASK 0x3ffffff
39#define JIMM_SH 0
40#define FUNC_MASK 0x3f
41#define FUNC_SH 0
42#define SET_MASK 0x7
43#define SET_SH 0
44
45enum opcode {
46 insn_invalid,
47 insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
48 insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
49 insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
50 insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
51 insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
52 insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx,
53 insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0,
54 insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd,
55 insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
56 insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor,
57 insn_xori,
58};
59
60struct insn {
61 enum opcode opcode;
62 u32 match;
63 enum fields fields;
64};
65
66static inline u32 build_rs(u32 arg)
67{
68 WARN(arg & ~RS_MASK, KERN_WARNING "Micro-assembler field overflow\n");
69
70 return (arg & RS_MASK) << RS_SH;
71}
72
73static inline u32 build_rt(u32 arg)
74{
75 WARN(arg & ~RT_MASK, KERN_WARNING "Micro-assembler field overflow\n");
76
77 return (arg & RT_MASK) << RT_SH;
78}
79
80static inline u32 build_rd(u32 arg)
81{
82 WARN(arg & ~RD_MASK, KERN_WARNING "Micro-assembler field overflow\n");
83
84 return (arg & RD_MASK) << RD_SH;
85}
86
87static inline u32 build_re(u32 arg)
88{
89 WARN(arg & ~RE_MASK, KERN_WARNING "Micro-assembler field overflow\n");
90
91 return (arg & RE_MASK) << RE_SH;
92}
93
94static inline u32 build_simm(s32 arg)
95{
96 WARN(arg > 0x7fff || arg < -0x8000,
97 KERN_WARNING "Micro-assembler field overflow\n");
98
99 return arg & 0xffff;
100}
101
102static inline u32 build_uimm(u32 arg)
103{
104 WARN(arg & ~IMM_MASK, KERN_WARNING "Micro-assembler field overflow\n");
105
106 return arg & IMM_MASK;
107}
108
109static inline u32 build_scimm(u32 arg)
110{
111 WARN(arg & ~SCIMM_MASK,
112 KERN_WARNING "Micro-assembler field overflow\n");
113
114 return (arg & SCIMM_MASK) << SCIMM_SH;
115}
116
117static inline u32 build_func(u32 arg)
118{
119 WARN(arg & ~FUNC_MASK, KERN_WARNING "Micro-assembler field overflow\n");
120
121 return arg & FUNC_MASK;
122}
123
124static inline u32 build_set(u32 arg)
125{
126 WARN(arg & ~SET_MASK, KERN_WARNING "Micro-assembler field overflow\n");
127
128 return arg & SET_MASK;
129}
130
131static void build_insn(u32 **buf, enum opcode opc, ...);
132
133#define I_u1u2u3(op) \
134Ip_u1u2u3(op) \
135{ \
136 build_insn(buf, insn##op, a, b, c); \
137} \
138UASM_EXPORT_SYMBOL(uasm_i##op);
139
140#define I_u2u1u3(op) \
141Ip_u2u1u3(op) \
142{ \
143 build_insn(buf, insn##op, b, a, c); \
144} \
145UASM_EXPORT_SYMBOL(uasm_i##op);
146
147#define I_u3u1u2(op) \
148Ip_u3u1u2(op) \
149{ \
150 build_insn(buf, insn##op, b, c, a); \
151} \
152UASM_EXPORT_SYMBOL(uasm_i##op);
153
154#define I_u1u2s3(op) \
155Ip_u1u2s3(op) \
156{ \
157 build_insn(buf, insn##op, a, b, c); \
158} \
159UASM_EXPORT_SYMBOL(uasm_i##op);
160
161#define I_u2s3u1(op) \
162Ip_u2s3u1(op) \
163{ \
164 build_insn(buf, insn##op, c, a, b); \
165} \
166UASM_EXPORT_SYMBOL(uasm_i##op);
167
168#define I_u2u1s3(op) \
169Ip_u2u1s3(op) \
170{ \
171 build_insn(buf, insn##op, b, a, c); \
172} \
173UASM_EXPORT_SYMBOL(uasm_i##op);
174
175#define I_u2u1msbu3(op) \
176Ip_u2u1msbu3(op) \
177{ \
178 build_insn(buf, insn##op, b, a, c+d-1, c); \
179} \
180UASM_EXPORT_SYMBOL(uasm_i##op);
181
182#define I_u2u1msb32u3(op) \
183Ip_u2u1msbu3(op) \
184{ \
185 build_insn(buf, insn##op, b, a, c+d-33, c); \
186} \
187UASM_EXPORT_SYMBOL(uasm_i##op);
188
189#define I_u2u1msbdu3(op) \
190Ip_u2u1msbu3(op) \
191{ \
192 build_insn(buf, insn##op, b, a, d-1, c); \
193} \
194UASM_EXPORT_SYMBOL(uasm_i##op);
195
196#define I_u1u2(op) \
197Ip_u1u2(op) \
198{ \
199 build_insn(buf, insn##op, a, b); \
200} \
201UASM_EXPORT_SYMBOL(uasm_i##op);
202
203#define I_u1s2(op) \
204Ip_u1s2(op) \
205{ \
206 build_insn(buf, insn##op, a, b); \
207} \
208UASM_EXPORT_SYMBOL(uasm_i##op);
209
210#define I_u1(op) \
211Ip_u1(op) \
212{ \
213 build_insn(buf, insn##op, a); \
214} \
215UASM_EXPORT_SYMBOL(uasm_i##op);
216
217#define I_0(op) \
218Ip_0(op) \
219{ \
220 build_insn(buf, insn##op); \
221} \
222UASM_EXPORT_SYMBOL(uasm_i##op);
223
224I_u2u1s3(_addiu)
225I_u3u1u2(_addu)
226I_u2u1u3(_andi)
227I_u3u1u2(_and)
228I_u1u2s3(_beq)
229I_u1u2s3(_beql)
230I_u1s2(_bgez)
231I_u1s2(_bgezl)
232I_u1s2(_bltz)
233I_u1s2(_bltzl)
234I_u1u2s3(_bne)
235I_u2s3u1(_cache)
236I_u1u2u3(_dmfc0)
237I_u1u2u3(_dmtc0)
238I_u2u1s3(_daddiu)
239I_u3u1u2(_daddu)
240I_u2u1u3(_dsll)
241I_u2u1u3(_dsll32)
242I_u2u1u3(_dsra)
243I_u2u1u3(_dsrl)
244I_u2u1u3(_dsrl32)
245I_u2u1u3(_drotr)
246I_u2u1u3(_drotr32)
247I_u3u1u2(_dsubu)
248I_0(_eret)
249I_u2u1msbdu3(_ext)
250I_u2u1msbu3(_ins)
251I_u1(_j)
252I_u1(_jal)
253I_u1(_jr)
254I_u2s3u1(_ld)
255I_u2s3u1(_ll)
256I_u2s3u1(_lld)
257I_u1s2(_lui)
258I_u2s3u1(_lw)
259I_u1u2u3(_mfc0)
260I_u1u2u3(_mtc0)
261I_u2u1u3(_ori)
262I_u3u1u2(_or)
263I_0(_rfe)
264I_u2s3u1(_sc)
265I_u2s3u1(_scd)
266I_u2s3u1(_sd)
267I_u2u1u3(_sll)
268I_u2u1u3(_sra)
269I_u2u1u3(_srl)
270I_u2u1u3(_rotr)
271I_u3u1u2(_subu)
272I_u2s3u1(_sw)
273I_0(_tlbp)
274I_0(_tlbr)
275I_0(_tlbwi)
276I_0(_tlbwr)
277I_u3u1u2(_xor)
278I_u2u1u3(_xori)
279I_u2u1msbu3(_dins);
280I_u2u1msb32u3(_dinsm);
281I_u1(_syscall);
282I_u1u2s3(_bbit0);
283I_u1u2s3(_bbit1);
284I_u3u1u2(_lwx)
285I_u3u1u2(_ldx)
286
287#ifdef CONFIG_CPU_CAVIUM_OCTEON
288#include <asm/octeon/octeon.h>
289void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
290 unsigned int c)
291{
292 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
293 /*
294 * As per erratum Core-14449, replace prefetches 0-4,
295 * 6-24 with 'pref 28'.
296 */
297 build_insn(buf, insn_pref, c, 28, b);
298 else
299 build_insn(buf, insn_pref, c, a, b);
300}
301UASM_EXPORT_SYMBOL(ISAFUNC(uasm_i_pref));
302#else
303I_u2s3u1(_pref)
304#endif
305
306/* Handle labels. */
307void ISAFUNC(uasm_build_label)(struct uasm_label **lab, u32 *addr, int lid)
308{
309 (*lab)->addr = addr;
310 (*lab)->lab = lid;
311 (*lab)++;
312}
313UASM_EXPORT_SYMBOL(ISAFUNC(uasm_build_label));
314
315int ISAFUNC(uasm_in_compat_space_p)(long addr)
316{
317 /* Is this address in 32bit compat space? */
318#ifdef CONFIG_64BIT
319 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
320#else
321 return 1;
322#endif
323}
324UASM_EXPORT_SYMBOL(ISAFUNC(uasm_in_compat_space_p));
325
326static int uasm_rel_highest(long val)
327{
328#ifdef CONFIG_64BIT
329 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
330#else
331 return 0;
332#endif
333}
334
335static int uasm_rel_higher(long val)
336{
337#ifdef CONFIG_64BIT
338 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
339#else
340 return 0;
341#endif
342}
343
344int ISAFUNC(uasm_rel_hi)(long val)
345{
346 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
347}
348UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_hi));
349
350int ISAFUNC(uasm_rel_lo)(long val)
351{
352 return ((val & 0xffff) ^ 0x8000) - 0x8000;
353}
354UASM_EXPORT_SYMBOL(ISAFUNC(uasm_rel_lo));
355
356void ISAFUNC(UASM_i_LA_mostly)(u32 **buf, unsigned int rs, long addr)
357{
358 if (!ISAFUNC(uasm_in_compat_space_p)(addr)) {
359 ISAFUNC(uasm_i_lui)(buf, rs, uasm_rel_highest(addr));
360 if (uasm_rel_higher(addr))
361 ISAFUNC(uasm_i_daddiu)(buf, rs, rs, uasm_rel_higher(addr));
362 if (ISAFUNC(uasm_rel_hi(addr))) {
363 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
364 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
365 ISAFUNC(uasm_rel_hi)(addr));
366 ISAFUNC(uasm_i_dsll)(buf, rs, rs, 16);
367 } else
368 ISAFUNC(uasm_i_dsll32)(buf, rs, rs, 0);
369 } else
370 ISAFUNC(uasm_i_lui)(buf, rs, ISAFUNC(uasm_rel_hi(addr)));
371}
372UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA_mostly));
373
374void ISAFUNC(UASM_i_LA)(u32 **buf, unsigned int rs, long addr)
375{
376 ISAFUNC(UASM_i_LA_mostly)(buf, rs, addr);
377 if (ISAFUNC(uasm_rel_lo(addr))) {
378 if (!ISAFUNC(uasm_in_compat_space_p)(addr))
379 ISAFUNC(uasm_i_daddiu)(buf, rs, rs,
380 ISAFUNC(uasm_rel_lo(addr)));
381 else
382 ISAFUNC(uasm_i_addiu)(buf, rs, rs,
383 ISAFUNC(uasm_rel_lo(addr)));
384 }
385}
386UASM_EXPORT_SYMBOL(ISAFUNC(UASM_i_LA));
387
388/* Handle relocations. */
389void ISAFUNC(uasm_r_mips_pc16)(struct uasm_reloc **rel, u32 *addr, int lid)
390{
391 (*rel)->addr = addr;
392 (*rel)->type = R_MIPS_PC16;
393 (*rel)->lab = lid;
394 (*rel)++;
395}
396UASM_EXPORT_SYMBOL(ISAFUNC(uasm_r_mips_pc16));
397
398static inline void __resolve_relocs(struct uasm_reloc *rel,
399 struct uasm_label *lab);
400
401void ISAFUNC(uasm_resolve_relocs)(struct uasm_reloc *rel,
402 struct uasm_label *lab)
403{
404 struct uasm_label *l;
405
406 for (; rel->lab != UASM_LABEL_INVALID; rel++)
407 for (l = lab; l->lab != UASM_LABEL_INVALID; l++)
408 if (rel->lab == l->lab)
409 __resolve_relocs(rel, l);
410}
411UASM_EXPORT_SYMBOL(ISAFUNC(uasm_resolve_relocs));
412
413void ISAFUNC(uasm_move_relocs)(struct uasm_reloc *rel, u32 *first, u32 *end,
414 long off)
415{
416 for (; rel->lab != UASM_LABEL_INVALID; rel++)
417 if (rel->addr >= first && rel->addr < end)
418 rel->addr += off;
419}
420UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_relocs));
421
422void ISAFUNC(uasm_move_labels)(struct uasm_label *lab, u32 *first, u32 *end,
423 long off)
424{
425 for (; lab->lab != UASM_LABEL_INVALID; lab++)
426 if (lab->addr >= first && lab->addr < end)
427 lab->addr += off;
428}
429UASM_EXPORT_SYMBOL(ISAFUNC(uasm_move_labels));
430
431void ISAFUNC(uasm_copy_handler)(struct uasm_reloc *rel, struct uasm_label *lab,
432 u32 *first, u32 *end, u32 *target)
433{
434 long off = (long)(target - first);
435
436 memcpy(target, first, (end - first) * sizeof(u32));
437
438 ISAFUNC(uasm_move_relocs(rel, first, end, off));
439 ISAFUNC(uasm_move_labels(lab, first, end, off));
440}
441UASM_EXPORT_SYMBOL(ISAFUNC(uasm_copy_handler));
442
443int ISAFUNC(uasm_insn_has_bdelay)(struct uasm_reloc *rel, u32 *addr)
444{
445 for (; rel->lab != UASM_LABEL_INVALID; rel++) {
446 if (rel->addr == addr
447 && (rel->type == R_MIPS_PC16
448 || rel->type == R_MIPS_26))
449 return 1;
450 }
451
452 return 0;
453}
454UASM_EXPORT_SYMBOL(ISAFUNC(uasm_insn_has_bdelay));
455
456/* Convenience functions for labeled branches. */
457void ISAFUNC(uasm_il_bltz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
458 int lid)
459{
460 uasm_r_mips_pc16(r, *p, lid);
461 ISAFUNC(uasm_i_bltz)(p, reg, 0);
462}
463UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bltz));
464
465void ISAFUNC(uasm_il_b)(u32 **p, struct uasm_reloc **r, int lid)
466{
467 uasm_r_mips_pc16(r, *p, lid);
468 ISAFUNC(uasm_i_b)(p, 0);
469}
470UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_b));
471
472void ISAFUNC(uasm_il_beqz)(u32 **p, struct uasm_reloc **r, unsigned int reg,
473 int lid)
474{
475 uasm_r_mips_pc16(r, *p, lid);
476 ISAFUNC(uasm_i_beqz)(p, reg, 0);
477}
478UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqz));
479
480void ISAFUNC(uasm_il_beqzl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
481 int lid)
482{
483 uasm_r_mips_pc16(r, *p, lid);
484 ISAFUNC(uasm_i_beqzl)(p, reg, 0);
485}
486UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_beqzl));
487
488void ISAFUNC(uasm_il_bne)(u32 **p, struct uasm_reloc **r, unsigned int reg1,
489 unsigned int reg2, int lid)
490{
491 uasm_r_mips_pc16(r, *p, lid);
492 ISAFUNC(uasm_i_bne)(p, reg1, reg2, 0);
493}
494UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bne));
495
496void ISAFUNC(uasm_il_bnez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
497 int lid)
498{
499 uasm_r_mips_pc16(r, *p, lid);
500 ISAFUNC(uasm_i_bnez)(p, reg, 0);
501}
502UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bnez));
503
504void ISAFUNC(uasm_il_bgezl)(u32 **p, struct uasm_reloc **r, unsigned int reg,
505 int lid)
506{
507 uasm_r_mips_pc16(r, *p, lid);
508 ISAFUNC(uasm_i_bgezl)(p, reg, 0);
509}
510UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgezl));
511
512void ISAFUNC(uasm_il_bgez)(u32 **p, struct uasm_reloc **r, unsigned int reg,
513 int lid)
514{
515 uasm_r_mips_pc16(r, *p, lid);
516 ISAFUNC(uasm_i_bgez)(p, reg, 0);
517}
518UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bgez));
519
520void ISAFUNC(uasm_il_bbit0)(u32 **p, struct uasm_reloc **r, unsigned int reg,
521 unsigned int bit, int lid)
522{
523 uasm_r_mips_pc16(r, *p, lid);
524 ISAFUNC(uasm_i_bbit0)(p, reg, bit, 0);
525}
526UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit0));
527
528void ISAFUNC(uasm_il_bbit1)(u32 **p, struct uasm_reloc **r, unsigned int reg,
529 unsigned int bit, int lid)
530{
531 uasm_r_mips_pc16(r, *p, lid);
532 ISAFUNC(uasm_i_bbit1)(p, reg, bit, 0);
533}
534UASM_EXPORT_SYMBOL(ISAFUNC(uasm_il_bbit1));