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1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "sun5i.dtsi"
46
47#include <dt-bindings/dma/sun4i-a10.h>
48
49/ {
50 aliases {
51 ethernet0 = &emac;
52 };
53
54 chosen {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 framebuffer-lcd0-hdmi {
60 compatible = "allwinner,simple-framebuffer",
61 "simple-framebuffer";
62 allwinner,pipeline = "de_be0-lcd0-hdmi";
63 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_HDMI>,
64 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DRAM_DE_BE>,
65 <&ccu CLK_DE_BE>, <&ccu CLK_HDMI>;
66 status = "disabled";
67 };
68 };
69
70 display-engine {
71 compatible = "allwinner,sun5i-a10s-display-engine";
72 allwinner,pipelines = <&fe0>;
73 };
74
75 soc {
76 hdmi: hdmi@1c16000 {
77 compatible = "allwinner,sun5i-a10s-hdmi";
78 reg = <0x01c16000 0x1000>;
79 interrupts = <58>;
80 clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
81 <&ccu CLK_PLL_VIDEO0_2X>,
82 <&ccu CLK_PLL_VIDEO1_2X>;
83 clock-names = "ahb", "mod", "pll-0", "pll-1";
84 dmas = <&dma SUN4I_DMA_NORMAL 16>,
85 <&dma SUN4I_DMA_NORMAL 16>,
86 <&dma SUN4I_DMA_DEDICATED 24>;
87 dma-names = "ddc-tx", "ddc-rx", "audio-tx";
88 status = "disabled";
89
90 ports {
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 hdmi_in: port@0 {
95 reg = <0>;
96
97 hdmi_in_tcon0: endpoint {
98 remote-endpoint = <&tcon0_out_hdmi>;
99 };
100 };
101
102 hdmi_out: port@1 {
103 reg = <1>;
104 };
105 };
106 };
107
108 pwm: pwm@1c20e00 {
109 compatible = "allwinner,sun5i-a10s-pwm";
110 reg = <0x01c20e00 0xc>;
111 clocks = <&ccu CLK_HOSC>;
112 #pwm-cells = <3>;
113 status = "disabled";
114 };
115 };
116};
117
118&ccu {
119 compatible = "allwinner,sun5i-a10s-ccu";
120};
121
122&mmc1 {
123 pinctrl-names = "default";
124 pinctrl-0 = <&mmc1_pins>;
125};
126
127&pio {
128 compatible = "allwinner,sun5i-a10s-pinctrl";
129
130 uart0_pb_pins: uart0-pb-pins {
131 pins = "PB19", "PB20";
132 function = "uart0";
133 };
134
135 uart2_pc_pins: uart2-pc-pins {
136 pins = "PC18", "PC19";
137 function = "uart2";
138 };
139
140 emac_pa_pins: emac-pa-pins {
141 pins = "PA0", "PA1", "PA2",
142 "PA3", "PA4", "PA5", "PA6",
143 "PA7", "PA8", "PA9", "PA10",
144 "PA11", "PA12", "PA13", "PA14",
145 "PA15", "PA16";
146 function = "emac";
147 };
148
149 mmc1_pins: mmc1-pins {
150 pins = "PG3", "PG4", "PG5",
151 "PG6", "PG7", "PG8";
152 function = "mmc1";
153 drive-strength = <30>;
154 };
155
156 spi2_pb_pins: spi2-pb-pins {
157 pins = "PB12", "PB13", "PB14";
158 function = "spi2";
159 };
160
161 spi2_cs0_pb_pin: spi2-cs0-pb-pin {
162 pins = "PB11";
163 function = "spi2";
164 };
165};
166
167&tcon0_out {
168 tcon0_out_hdmi: endpoint@2 {
169 reg = <2>;
170 remote-endpoint = <&hdmi_in_tcon0>;
171 allwinner,tcon-channel = <1>;
172 };
173};
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&intc>;
18
19 aliases {
20 ethernet0 = &emac;
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 };
26
27 cpus {
28 cpu@0 {
29 compatible = "arm,cortex-a8";
30 };
31 };
32
33 memory {
34 reg = <0x40000000 0x20000000>;
35 };
36
37 clocks {
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges;
41
42 /*
43 * This is a dummy clock, to be used as placeholder on
44 * other mux clocks when a specific parent clock is not
45 * yet implemented. It should be dropped when the driver
46 * is complete.
47 */
48 dummy: dummy {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <0>;
52 };
53
54 osc24M: clk@01c20050 {
55 #clock-cells = <0>;
56 compatible = "allwinner,sun4i-a10-osc-clk";
57 reg = <0x01c20050 0x4>;
58 clock-frequency = <24000000>;
59 clock-output-names = "osc24M";
60 };
61
62 osc32k: clk@0 {
63 #clock-cells = <0>;
64 compatible = "fixed-clock";
65 clock-frequency = <32768>;
66 clock-output-names = "osc32k";
67 };
68
69 pll1: clk@01c20000 {
70 #clock-cells = <0>;
71 compatible = "allwinner,sun4i-a10-pll1-clk";
72 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>;
74 clock-output-names = "pll1";
75 };
76
77 pll4: clk@01c20018 {
78 #clock-cells = <0>;
79 compatible = "allwinner,sun4i-a10-pll1-clk";
80 reg = <0x01c20018 0x4>;
81 clocks = <&osc24M>;
82 clock-output-names = "pll4";
83 };
84
85 pll5: clk@01c20020 {
86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-a10-pll5-clk";
88 reg = <0x01c20020 0x4>;
89 clocks = <&osc24M>;
90 clock-output-names = "pll5_ddr", "pll5_other";
91 };
92
93 pll6: clk@01c20028 {
94 #clock-cells = <1>;
95 compatible = "allwinner,sun4i-a10-pll6-clk";
96 reg = <0x01c20028 0x4>;
97 clocks = <&osc24M>;
98 clock-output-names = "pll6_sata", "pll6_other", "pll6";
99 };
100
101 /* dummy is 200M */
102 cpu: cpu@01c20054 {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-a10-cpu-clk";
105 reg = <0x01c20054 0x4>;
106 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
107 clock-output-names = "cpu";
108 };
109
110 axi: axi@01c20054 {
111 #clock-cells = <0>;
112 compatible = "allwinner,sun4i-a10-axi-clk";
113 reg = <0x01c20054 0x4>;
114 clocks = <&cpu>;
115 clock-output-names = "axi";
116 };
117
118 axi_gates: clk@01c2005c {
119 #clock-cells = <1>;
120 compatible = "allwinner,sun4i-a10-axi-gates-clk";
121 reg = <0x01c2005c 0x4>;
122 clocks = <&axi>;
123 clock-output-names = "axi_dram";
124 };
125
126 ahb: ahb@01c20054 {
127 #clock-cells = <0>;
128 compatible = "allwinner,sun4i-a10-ahb-clk";
129 reg = <0x01c20054 0x4>;
130 clocks = <&axi>;
131 clock-output-names = "ahb";
132 };
133
134 ahb_gates: clk@01c20060 {
135 #clock-cells = <1>;
136 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
137 reg = <0x01c20060 0x8>;
138 clocks = <&ahb>;
139 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
140 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
141 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
142 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
143 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
144 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
145 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
146 };
147
148 apb0: apb0@01c20054 {
149 #clock-cells = <0>;
150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>;
152 clocks = <&ahb>;
153 clock-output-names = "apb0";
154 };
155
156 apb0_gates: clk@01c20068 {
157 #clock-cells = <1>;
158 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
159 reg = <0x01c20068 0x4>;
160 clocks = <&apb0>;
161 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
162 "apb0_ir", "apb0_keypad";
163 };
164
165 apb1_mux: apb1_mux@01c20058 {
166 #clock-cells = <0>;
167 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
168 reg = <0x01c20058 0x4>;
169 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
170 clock-output-names = "apb1_mux";
171 };
172
173 apb1: apb1@01c20058 {
174 #clock-cells = <0>;
175 compatible = "allwinner,sun4i-a10-apb1-clk";
176 reg = <0x01c20058 0x4>;
177 clocks = <&apb1_mux>;
178 clock-output-names = "apb1";
179 };
180
181 apb1_gates: clk@01c2006c {
182 #clock-cells = <1>;
183 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
184 reg = <0x01c2006c 0x4>;
185 clocks = <&apb1>;
186 clock-output-names = "apb1_i2c0", "apb1_i2c1",
187 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
188 "apb1_uart2", "apb1_uart3";
189 };
190
191 nand_clk: clk@01c20080 {
192 #clock-cells = <0>;
193 compatible = "allwinner,sun4i-a10-mod0-clk";
194 reg = <0x01c20080 0x4>;
195 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
196 clock-output-names = "nand";
197 };
198
199 ms_clk: clk@01c20084 {
200 #clock-cells = <0>;
201 compatible = "allwinner,sun4i-a10-mod0-clk";
202 reg = <0x01c20084 0x4>;
203 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
204 clock-output-names = "ms";
205 };
206
207 mmc0_clk: clk@01c20088 {
208 #clock-cells = <0>;
209 compatible = "allwinner,sun4i-a10-mod0-clk";
210 reg = <0x01c20088 0x4>;
211 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
212 clock-output-names = "mmc0";
213 };
214
215 mmc1_clk: clk@01c2008c {
216 #clock-cells = <0>;
217 compatible = "allwinner,sun4i-a10-mod0-clk";
218 reg = <0x01c2008c 0x4>;
219 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
220 clock-output-names = "mmc1";
221 };
222
223 mmc2_clk: clk@01c20090 {
224 #clock-cells = <0>;
225 compatible = "allwinner,sun4i-a10-mod0-clk";
226 reg = <0x01c20090 0x4>;
227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
228 clock-output-names = "mmc2";
229 };
230
231 ts_clk: clk@01c20098 {
232 #clock-cells = <0>;
233 compatible = "allwinner,sun4i-a10-mod0-clk";
234 reg = <0x01c20098 0x4>;
235 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
236 clock-output-names = "ts";
237 };
238
239 ss_clk: clk@01c2009c {
240 #clock-cells = <0>;
241 compatible = "allwinner,sun4i-a10-mod0-clk";
242 reg = <0x01c2009c 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
244 clock-output-names = "ss";
245 };
246
247 spi0_clk: clk@01c200a0 {
248 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-a10-mod0-clk";
250 reg = <0x01c200a0 0x4>;
251 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
252 clock-output-names = "spi0";
253 };
254
255 spi1_clk: clk@01c200a4 {
256 #clock-cells = <0>;
257 compatible = "allwinner,sun4i-a10-mod0-clk";
258 reg = <0x01c200a4 0x4>;
259 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
260 clock-output-names = "spi1";
261 };
262
263 spi2_clk: clk@01c200a8 {
264 #clock-cells = <0>;
265 compatible = "allwinner,sun4i-a10-mod0-clk";
266 reg = <0x01c200a8 0x4>;
267 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
268 clock-output-names = "spi2";
269 };
270
271 ir0_clk: clk@01c200b0 {
272 #clock-cells = <0>;
273 compatible = "allwinner,sun4i-a10-mod0-clk";
274 reg = <0x01c200b0 0x4>;
275 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
276 clock-output-names = "ir0";
277 };
278
279 usb_clk: clk@01c200cc {
280 #clock-cells = <1>;
281 #reset-cells = <1>;
282 compatible = "allwinner,sun5i-a13-usb-clk";
283 reg = <0x01c200cc 0x4>;
284 clocks = <&pll6 1>;
285 clock-output-names = "usb_ohci0", "usb_phy";
286 };
287
288 mbus_clk: clk@01c2015c {
289 #clock-cells = <0>;
290 compatible = "allwinner,sun4i-a10-mod0-clk";
291 reg = <0x01c2015c 0x4>;
292 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
293 clock-output-names = "mbus";
294 };
295 };
296
297 soc@01c00000 {
298 compatible = "simple-bus";
299 #address-cells = <1>;
300 #size-cells = <1>;
301 ranges;
302
303 spi0: spi@01c05000 {
304 compatible = "allwinner,sun4i-a10-spi";
305 reg = <0x01c05000 0x1000>;
306 interrupts = <10>;
307 clocks = <&ahb_gates 20>, <&spi0_clk>;
308 clock-names = "ahb", "mod";
309 status = "disabled";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 };
313
314 spi1: spi@01c06000 {
315 compatible = "allwinner,sun4i-a10-spi";
316 reg = <0x01c06000 0x1000>;
317 interrupts = <11>;
318 clocks = <&ahb_gates 21>, <&spi1_clk>;
319 clock-names = "ahb", "mod";
320 status = "disabled";
321 #address-cells = <1>;
322 #size-cells = <0>;
323 };
324
325 emac: ethernet@01c0b000 {
326 compatible = "allwinner,sun4i-a10-emac";
327 reg = <0x01c0b000 0x1000>;
328 interrupts = <55>;
329 clocks = <&ahb_gates 17>;
330 status = "disabled";
331 };
332
333 mdio@01c0b080 {
334 compatible = "allwinner,sun4i-a10-mdio";
335 reg = <0x01c0b080 0x14>;
336 status = "disabled";
337 #address-cells = <1>;
338 #size-cells = <0>;
339 };
340
341 usbphy: phy@01c13400 {
342 #phy-cells = <1>;
343 compatible = "allwinner,sun5i-a13-usb-phy";
344 reg = <0x01c13400 0x10 0x01c14800 0x4>;
345 reg-names = "phy_ctrl", "pmu1";
346 clocks = <&usb_clk 8>;
347 clock-names = "usb_phy";
348 resets = <&usb_clk 1>;
349 reset-names = "usb1_reset";
350 status = "disabled";
351 };
352
353 ehci0: usb@01c14000 {
354 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
355 reg = <0x01c14000 0x100>;
356 interrupts = <39>;
357 clocks = <&ahb_gates 1>;
358 phys = <&usbphy 1>;
359 phy-names = "usb";
360 status = "disabled";
361 };
362
363 ohci0: usb@01c14400 {
364 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
365 reg = <0x01c14400 0x100>;
366 interrupts = <40>;
367 clocks = <&usb_clk 6>, <&ahb_gates 2>;
368 phys = <&usbphy 1>;
369 phy-names = "usb";
370 status = "disabled";
371 };
372
373 spi2: spi@01c17000 {
374 compatible = "allwinner,sun4i-a10-spi";
375 reg = <0x01c17000 0x1000>;
376 interrupts = <12>;
377 clocks = <&ahb_gates 22>, <&spi2_clk>;
378 clock-names = "ahb", "mod";
379 status = "disabled";
380 #address-cells = <1>;
381 #size-cells = <0>;
382 };
383
384 intc: interrupt-controller@01c20400 {
385 compatible = "allwinner,sun4i-a10-ic";
386 reg = <0x01c20400 0x400>;
387 interrupt-controller;
388 #interrupt-cells = <1>;
389 };
390
391 pio: pinctrl@01c20800 {
392 compatible = "allwinner,sun5i-a10s-pinctrl";
393 reg = <0x01c20800 0x400>;
394 interrupts = <28>;
395 clocks = <&apb0_gates 5>;
396 gpio-controller;
397 interrupt-controller;
398 #address-cells = <1>;
399 #size-cells = <0>;
400 #gpio-cells = <3>;
401
402 uart0_pins_a: uart0@0 {
403 allwinner,pins = "PB19", "PB20";
404 allwinner,function = "uart0";
405 allwinner,drive = <0>;
406 allwinner,pull = <0>;
407 };
408
409 uart2_pins_a: uart2@0 {
410 allwinner,pins = "PC18", "PC19";
411 allwinner,function = "uart2";
412 allwinner,drive = <0>;
413 allwinner,pull = <0>;
414 };
415
416 uart3_pins_a: uart3@0 {
417 allwinner,pins = "PG9", "PG10";
418 allwinner,function = "uart3";
419 allwinner,drive = <0>;
420 allwinner,pull = <0>;
421 };
422
423 emac_pins_a: emac0@0 {
424 allwinner,pins = "PA0", "PA1", "PA2",
425 "PA3", "PA4", "PA5", "PA6",
426 "PA7", "PA8", "PA9", "PA10",
427 "PA11", "PA12", "PA13", "PA14",
428 "PA15", "PA16";
429 allwinner,function = "emac";
430 allwinner,drive = <0>;
431 allwinner,pull = <0>;
432 };
433
434 i2c0_pins_a: i2c0@0 {
435 allwinner,pins = "PB0", "PB1";
436 allwinner,function = "i2c0";
437 allwinner,drive = <0>;
438 allwinner,pull = <0>;
439 };
440
441 i2c1_pins_a: i2c1@0 {
442 allwinner,pins = "PB15", "PB16";
443 allwinner,function = "i2c1";
444 allwinner,drive = <0>;
445 allwinner,pull = <0>;
446 };
447
448 i2c2_pins_a: i2c2@0 {
449 allwinner,pins = "PB17", "PB18";
450 allwinner,function = "i2c2";
451 allwinner,drive = <0>;
452 allwinner,pull = <0>;
453 };
454 };
455
456 timer@01c20c00 {
457 compatible = "allwinner,sun4i-a10-timer";
458 reg = <0x01c20c00 0x90>;
459 interrupts = <22>;
460 clocks = <&osc24M>;
461 };
462
463 wdt: watchdog@01c20c90 {
464 compatible = "allwinner,sun4i-a10-wdt";
465 reg = <0x01c20c90 0x10>;
466 };
467
468 sid: eeprom@01c23800 {
469 compatible = "allwinner,sun4i-a10-sid";
470 reg = <0x01c23800 0x10>;
471 };
472
473 rtp: rtp@01c25000 {
474 compatible = "allwinner,sun4i-a10-ts";
475 reg = <0x01c25000 0x100>;
476 interrupts = <29>;
477 };
478
479 uart0: serial@01c28000 {
480 compatible = "snps,dw-apb-uart";
481 reg = <0x01c28000 0x400>;
482 interrupts = <1>;
483 reg-shift = <2>;
484 reg-io-width = <4>;
485 clocks = <&apb1_gates 16>;
486 status = "disabled";
487 };
488
489 uart1: serial@01c28400 {
490 compatible = "snps,dw-apb-uart";
491 reg = <0x01c28400 0x400>;
492 interrupts = <2>;
493 reg-shift = <2>;
494 reg-io-width = <4>;
495 clocks = <&apb1_gates 17>;
496 status = "disabled";
497 };
498
499 uart2: serial@01c28800 {
500 compatible = "snps,dw-apb-uart";
501 reg = <0x01c28800 0x400>;
502 interrupts = <3>;
503 reg-shift = <2>;
504 reg-io-width = <4>;
505 clocks = <&apb1_gates 18>;
506 status = "disabled";
507 };
508
509 uart3: serial@01c28c00 {
510 compatible = "snps,dw-apb-uart";
511 reg = <0x01c28c00 0x400>;
512 interrupts = <4>;
513 reg-shift = <2>;
514 reg-io-width = <4>;
515 clocks = <&apb1_gates 19>;
516 status = "disabled";
517 };
518
519 i2c0: i2c@01c2ac00 {
520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "allwinner,sun4i-i2c";
523 reg = <0x01c2ac00 0x400>;
524 interrupts = <7>;
525 clocks = <&apb1_gates 0>;
526 clock-frequency = <100000>;
527 status = "disabled";
528 };
529
530 i2c1: i2c@01c2b000 {
531 #address-cells = <1>;
532 #size-cells = <0>;
533 compatible = "allwinner,sun4i-i2c";
534 reg = <0x01c2b000 0x400>;
535 interrupts = <8>;
536 clocks = <&apb1_gates 1>;
537 clock-frequency = <100000>;
538 status = "disabled";
539 };
540
541 i2c2: i2c@01c2b400 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "allwinner,sun4i-i2c";
545 reg = <0x01c2b400 0x400>;
546 interrupts = <9>;
547 clocks = <&apb1_gates 2>;
548 clock-frequency = <100000>;
549 status = "disabled";
550 };
551
552 timer@01c60000 {
553 compatible = "allwinner,sun5i-a13-hstimer";
554 reg = <0x01c60000 0x1000>;
555 interrupts = <82>, <83>;
556 clocks = <&ahb_gates 28>;
557 };
558 };
559};